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0104a74028
Preloading a few cache lines ahead brings a significant speedup in memcpy throughput. Note, the particular (optimal) value was empirically determined on a Cortex-A9 (Zynq-7000) SoC @ 666Mhz. It is best combined with L2 prefetching enabled (including double linefills and prefetch offset 7). Yet, even without L2 prefetching this seems to be the sweet spot. genodelabs/genode#4456
61 lines
1.6 KiB
C++
61 lines
1.6 KiB
C++
/*
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* \brief ARM-specific memcpy
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* \author Sebastian Sumpf
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* \author Stefan Kalkowski
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* \date 2012-08-02
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*/
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/*
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* Copyright (C) 2012-2017 Genode Labs GmbH
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*
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* This file is part of the Genode OS framework, which is distributed
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* under the terms of the GNU Affero General Public License version 3.
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*/
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#ifndef _INCLUDE__SPEC__ARM__CPU__STRING_H_
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#define _INCLUDE__SPEC__ARM__CPU__STRING_H_
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namespace Genode {
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/**
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* Copy memory block
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*
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* \param dst destination memory block
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* \param src source memory block
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* \param size number of bytes to copy
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*
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* \return Number of bytes not copied
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*/
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inline size_t memcpy_cpu(void *dst, const void *src, size_t size)
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{
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unsigned char *d = (unsigned char *)dst, *s = (unsigned char *)src;
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/* fetch the first cache line */
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asm volatile ("pld [%0, #0]\n\t" : "+r" (s));
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/* check 32-byte (cache line) alignment */
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size_t d_align = (size_t)d & 0x1f;
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size_t s_align = (size_t)s & 0x1f;
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/* only same word-alignments work for the following LDM/STM loop */
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if ((d_align & 0x3) != (s_align & 0x3))
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return size;
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/* copy to 32-byte alignment */
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for (; (size > 0) && (s_align > 0) && (s_align < 32);
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s_align++, *d++ = *s++, size--);
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/* copy 32 byte chunks */
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for (; size >= 32; size -= 32) {
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asm volatile ("ldmia %0!, {r3 - r10} \n\t"
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"pld [%0, #160]\n\t"
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"stmia %1!, {r3 - r10} \n\t"
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: "+r" (s), "+r" (d)
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:: "r3","r4","r5","r6","r7","r8","r9","r10");
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}
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return size;
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}
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}
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#endif /* _INCLUDE__SPEC__ARM__CPU__STRING_H_ */
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