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71 lines
1.9 KiB
C++
71 lines
1.9 KiB
C++
/*
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* \brief MMIO and IRQ definitions common to Xilinx Zynq platforms
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* \author Mark Albers
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* \author Timo Wischer
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* \author Johannes Schlatow
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* \date 2014-12-15
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*/
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/*
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* Copyright (C) 2014-2017 Genode Labs GmbH
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*
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* This file is part of the Genode OS framework, which is distributed
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* under the terms of the GNU Affero General Public License version 3.
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*/
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#ifndef _INCLUDE__DRIVERS__DEFS__ZYNQ_H_
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#define _INCLUDE__DRIVERS__DEFS__ZYNQ_H_
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namespace Zynq {
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enum {
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/* device IO memory */
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MMIO_0_BASE = 0xe0000000, /* IOP devices */
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MMIO_0_SIZE = 0x10000000,
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MMIO_1_BASE = 0xF8000000, /* Programmable register via APB */
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MMIO_1_SIZE = 0x02000000,
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QSPI_MMIO_BASE = 0xFC000000, /* Quad-SPI */
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QSPI_MMIO_SIZE = 0x01000000,
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OCM_MMIO_BASE = 0xFFFC0000, /* OCM upper address range */
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OCM_MMIO_SIZE = 0x00040000,
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/* normal RAM */
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RAM_0_BASE = 0x00000000,
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RAM_0_SIZE = 0x40000000, /* 1GiB */
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/* AXI */
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AXI_0_MMIO_BASE = 0x40000000, /* PL AXI Slave port #0 */
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AXI_0_MMIO_SIZE = 0x40000000,
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AXI_1_MMIO_BASE = 0x80000000, /* PL AXI Slave port #1 */
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AXI_1_MMIO_SIZE = 0x40000000,
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/* UART controllers */
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UART_0_MMIO_BASE = MMIO_0_BASE,
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UART_SIZE = 0x1000,
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UART_CLOCK = 50*1000*1000,
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/* CPU */
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CORTEX_A9_PRIVATE_MEM_BASE = 0xf8f00000,
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CORTEX_A9_PRIVATE_MEM_SIZE = 0x00002000,
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/* entrypoint address of secondary cpu */
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CORE1_ENTRY = 0xfffffff0,
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/* CPU cache */
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PL310_MMIO_BASE = MMIO_1_BASE + 0xF02000,
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PL310_MMIO_SIZE = 0x1000,
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CACHE_LINE_SIZE_LOG2 = 2, /* FIXME get correct value from board spec */
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/* TTC (triple timer counter) */
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TTC0_MMIO_BASE = MMIO_1_BASE + 0x1000,
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TTC0_MMIO_SIZE = 0xfff,
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TTC0_IRQ_0 = 42,
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/* Ethernet MAC PS */
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EMAC_0_MMIO_BASE = 0xE000B000,
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EMAC_0_MMIO_SIZE = 0x1000,
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EMAC_0_IRQ = 54,
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};
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};
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#endif /* _INCLUDE__DRIVERS__DEFS__ZYNQ_H_ */
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