Martin Stein 18cee192e2 hw: don't do redundant inter-processor interrupts ...

At least with the ARM generic interrupt controller, inter-processor interrupts
are edge triggered and banked for all source processors. Thus it might be
possible that such an interrupt gets triggered redundantly until the targeted
processor is able to grab the kernel lock. As we're only interested in making
a processor recognize accumulative updates to its scheduler, we can omit
further interrupts if there is one pending already at the targeted processor.

ref #1088

2014-03-14 13:17:37 +01:00

..

doc

Merge panda_a2 and panda SPEC (fix #505, fix #506)

2012-11-23 12:20:27 +01:00

include

hw: set affinity of core threads

2014-03-14 13:16:05 +01:00

lib/mk

hw: merge base-common and kernel_interface lib

2014-02-25 14:58:08 +01:00

mk

hw_arndale: idle threads on secondary processors

2014-03-04 15:03:43 +01:00

run

hw: adjust expected serial start-message in run

2013-11-25 09:46:08 +01:00

src

hw: don't do redundant inter-processor interrupts

2014-03-14 13:17:37 +01:00