/*
 * \brief  Driver for the Versatile Express A9X4 board
 * \author Martin stein
 * \date   2011-11-03
 */

/*
 * Copyright (C) 2011-2013 Genode Labs GmbH
 *
 * This file is part of the Genode OS framework, which is distributed
 * under the terms of the GNU General Public License version 2.
 */

#ifndef _INCLUDE__DRIVERS__BOARD_BASE_H_
#define _INCLUDE__DRIVERS__BOARD_BASE_H_

namespace Genode
{
	/**
	 * Driver for the Versatile Express A9X4 board
	 *
	 * Implies the uATX motherboard and the CoreTile Express A9X4 daughterboard
	 */
	struct Board_base
	{
		enum
		{
			/* MMIO */
			MMIO_0_BASE = 0x10000000,
			MMIO_0_SIZE = 0x10000000,
			MMIO_1_BASE = 0x4C000000,
			MMIO_1_SIZE = 0x04000000,

			/* RAM */
			RAM_0_BASE = 0x00000000,
			RAM_0_SIZE = 0x04000000,
			RAM_1_BASE = 0x60000000,
			RAM_1_SIZE = 0x20000000,
			RAM_2_BASE = 0x84000000,
			RAM_2_SIZE = 0x1c000000,
			RAM_3_BASE = 0x48000000,
			RAM_3_SIZE = 0x02000000,

			/* UART */
			PL011_0_MMIO_BASE = MMIO_0_BASE + 0x9000,
			PL011_0_MMIO_SIZE = 0x1000,
			PL011_0_CLOCK = 24*1000*1000,
			PL011_0_IRQ = 5,

			/* timer/counter */
			SP804_0_1_MMIO_BASE = MMIO_0_BASE + 0x11000,
			SP804_0_1_MMIO_SIZE = 0x1000,
			SP804_0_1_CLOCK = 1000*1000,
			SP804_0_1_IRQ = 34,

			/* clocks */
			TCREF_CLOCK = 66670*1000,

			/* TrustZone Address Space Controller */
			TZASC_MMIO_BASE = 0x100ec000,
			TZASC_MMIO_SIZE = 0x1000,

			/* TrustZone Protection Controller */
			TZPC_MMIO_BASE = 0x100e6000,
			TZPC_MMIO_SIZE = 0x1000,

			/* CPU */
			CORTEX_A9_PRIVATE_MEM_BASE = 0x1e000000,
			CORTEX_A9_PRIVATE_MEM_SIZE = 0x2000,
			CORTEX_A9_CLOCK = TCREF_CLOCK,

			/* wether board provides security extension */
			SECURITY_EXTENSION = 1,

			/* CPU cache */
			CACHE_LINE_SIZE_LOG2 = 2, /* FIXME get correct value from board spec */
		};
	};
}

#endif /* _INCLUDE__DRIVERS__BOARD_BASE_H_ */