# core symbols drmAddBufs T drmAddContextPrivateMapping T drmAddContextTag T drmAddMap T drmAgpAcquire T drmAgpAlloc T drmAgpBase T drmAgpBind T drmAgpDeviceId T drmAgpEnable T drmAgpFree T drmAgpGetMode T drmAgpMemoryAvail T drmAgpMemoryUsed T drmAgpRelease T drmAgpSize T drmAgpUnbind T drmAgpVendorId T drmAgpVersionMajor T drmAgpVersionMinor T drmAuthMagic T drmAvailable T drmCheckModesettingSupported T drmClose T drmCloseOnce T drmCommandNone T drmCommandRead T drmCommandWrite T drmCommandWriteRead T drmCreateContext T drmCreateDrawable T drmCrtcGetSequence T drmCrtcQueueSequence T drmCtlInstHandler T drmCtlUninstHandler T drmDelContextTag T drmDestroyContext T drmDestroyDrawable T drmDevicesEqual T drmDMA T drmDropMaster T drmError T drmFinish T drmFree T drmFreeBufs T drmFreeBusid T drmFreeDevice T drmFreeDevices T drmFreeReservedContextList T drmFreeVersion T drmGetBufInfo T drmGetBusid T drmGetCap T drmGetClient T drmGetContextFlags T drmGetContextPrivateMapping T drmGetContextTag T drmGetDevice T drmGetDevice2 T drmGetDeviceNameFromFd T drmGetDeviceNameFromFd2 T drmGetDevices T drmGetDevices2 T drmGetEntry T drmGetHashTable T drmGetInterruptFromBusID T drmGetLibVersion T drmGetLock T drmGetMagic T drmGetMap T drmGetNodeTypeFromFd T drmGetPrimaryDeviceNameFromFd T drmGetRenderDeviceNameFromFd T drmGetReservedContextList T drmGetStats T drmGetVersion T drmHandleEvent T drmHashCreate T drmHashDelete T drmHashDestroy T drmHashFirst T drmHashInsert T drmHashLookup T drmHashNext T drmIoctl T drmIsKMS T drmIsMaster T drmMalloc T drmMap T drmMapBufs T drmMarkBufs T drmModeAddFB T drmModeAddFB2 T drmModeAddFB2WithModifiers T drmModeAtomicAddProperty T drmModeAtomicAlloc T drmModeAtomicCommit T drmModeAtomicDuplicate T drmModeAtomicFree T drmModeAtomicGetCursor T drmModeAtomicMerge T drmModeAtomicSetCursor T drmModeAttachMode T drmModeConnectorSetProperty T drmModeCreateLease T drmModeCreatePropertyBlob T drmModeCrtcGetGamma T drmModeCrtcSetGamma T drmModeDestroyPropertyBlob T drmModeDetachMode T drmModeDirtyFB T drmModeFreeConnector T drmModeFreeCrtc T drmModeFreeEncoder T drmModeFreeFB T drmModeFreeFB2 T drmModeFreeModeInfo T drmModeFreeObjectProperties T drmModeFreePlane T drmModeFreePlaneResources T drmModeFreeProperty T drmModeFreePropertyBlob T drmModeFreeResources T drmModeGetConnector T drmModeGetConnectorCurrent T drmModeGetCrtc T drmModeGetEncoder T drmModeGetFB T drmModeGetFB2 T drmModeGetLease T drmModeGetPlane T drmModeGetPlaneResources T drmModeGetProperty T drmModeGetPropertyBlob T drmModeGetResources T drmModeListLessees T drmModeMoveCursor T drmModeObjectGetProperties T drmModeObjectSetProperty T drmModePageFlip T drmModePageFlipTarget T drmModeRevokeLease T drmModeRmFB T drmModeSetCrtc T drmModeSetCursor T drmModeSetCursor2 T drmModeSetPlane T drmMsg T drmOpen T drmOpenControl T drmOpenOnce T drmOpenOnceWithType T drmOpenRender T drmOpenWithType T drmPrimeFDToHandle T drmPrimeHandleToFD T drmRandom T drmRandomCreate T drmRandomDestroy T drmRandomDouble T drmRmMap T drmScatterGatherAlloc T drmScatterGatherFree T drmSetBusid T drmSetClientCap T drmSetContextFlags T drmSetInterfaceVersion T drmSetMaster T drmSetServerInfo T drmSLCreate T drmSLDelete T drmSLDestroy T drmSLDump T drmSLFirst T drmSLInsert T drmSLLookup T drmSLLookupNeighbors T drmSLNext T drmSwitchToContext T drmSyncobjCreate T drmSyncobjDestroy T drmSyncobjExportSyncFile T drmSyncobjFDToHandle T drmSyncobjHandleToFD T drmSyncobjImportSyncFile T drmSyncobjQuery T drmSyncobjQuery2 T drmSyncobjReset T drmSyncobjSignal T drmSyncobjTimelineSignal T drmSyncobjTimelineWait T drmSyncobjTransfer T drmSyncobjWait T drmUnlock T drmUnmap T drmUnmapBufs T drmUpdateDrawableInfo T drmWaitVBlank T # Etnaviv symbols etna_device_new T etna_device_new_dup T etna_device_ref T etna_device_del T etna_device_fd T etna_gpu_new T etna_gpu_del T etna_gpu_get_param T etna_pipe_new T etna_pipe_del T etna_pipe_wait T etna_pipe_wait_ns T etna_bo_new T etna_bo_from_name T etna_bo_from_dmabuf T etna_bo_ref T etna_bo_del T etna_bo_get_name T etna_bo_handle T etna_bo_dmabuf T etna_bo_size T etna_bo_map T etna_bo_cpu_prep T etna_bo_cpu_fini T etna_cmd_stream_new T etna_cmd_stream_del T etna_cmd_stream_timestamp T etna_cmd_stream_flush T etna_cmd_stream_flush2 T etna_cmd_stream_finish T etna_cmd_stream_perf T etna_cmd_stream_reloc T etna_perfmon_create T etna_perfmon_del T etna_perfmon_get_dom_by_name T etna_perfmon_get_sig_by_name T # Intel symbols drm_intel_bo_alloc T drm_intel_bo_alloc_for_render T drm_intel_bo_alloc_tiled T drm_intel_bo_alloc_userptr T drm_intel_bo_busy T drm_intel_bo_disable_reuse T drm_intel_bo_emit_reloc T drm_intel_bo_emit_reloc_fence T drm_intel_bo_exec T drm_intel_bo_fake_alloc_static T drm_intel_bo_fake_disable_backing_store T drm_intel_bo_flink T drm_intel_bo_gem_create_from_name T drm_intel_bo_gem_create_from_prime T drm_intel_bo_gem_export_to_prime T drm_intel_bo_get_subdata T drm_intel_bo_get_tiling T drm_intel_bo_is_reusable T drm_intel_bo_madvise T drm_intel_bo_map T drm_intel_bo_mrb_exec T drm_intel_bo_pin T drm_intel_bo_reference T drm_intel_bo_references T drm_intel_bo_set_softpin_offset T drm_intel_bo_set_tiling T drm_intel_bo_subdata T drm_intel_bo_unmap T drm_intel_bo_unpin T drm_intel_bo_unreference T drm_intel_bo_use_48b_address_range T drm_intel_bo_wait_rendering T drm_intel_bufmgr_check_aperture_space T drm_intel_bufmgr_destroy T drm_intel_bufmgr_fake_contended_lock_take T drm_intel_bufmgr_fake_evict_all T drm_intel_bufmgr_fake_init T drm_intel_bufmgr_fake_set_exec_callback T drm_intel_bufmgr_fake_set_fence_callback T drm_intel_bufmgr_fake_set_last_dispatch T drm_intel_bufmgr_gem_can_disable_implicit_sync T drm_intel_bufmgr_gem_enable_fenced_relocs T drm_intel_bufmgr_gem_enable_reuse T drm_intel_bufmgr_gem_get_devid T drm_intel_bufmgr_gem_init T drm_intel_bufmgr_gem_set_aub_annotations T drm_intel_bufmgr_gem_set_aub_dump T drm_intel_bufmgr_gem_set_aub_filename T drm_intel_bufmgr_gem_set_vma_cache_size T drm_intel_bufmgr_set_debug T drm_intel_decode T drm_intel_decode_context_alloc T drm_intel_decode_context_free T drm_intel_decode_set_batch_pointer T drm_intel_decode_set_dump_past_end T drm_intel_decode_set_head_tail T drm_intel_decode_set_output_file T drm_intel_gem_bo_aub_dump_bmp T drm_intel_gem_bo_clear_relocs T drm_intel_gem_bo_context_exec T drm_intel_gem_bo_disable_implicit_sync T drm_intel_gem_bo_enable_implicit_sync T drm_intel_gem_bo_fence_exec T drm_intel_gem_bo_get_reloc_count T drm_intel_gem_bo_map__cpu T drm_intel_gem_bo_map__gtt T drm_intel_gem_bo_map__wc T drm_intel_gem_bo_map_gtt T drm_intel_gem_bo_map_unsynchronized T drm_intel_gem_bo_start_gtt_access T drm_intel_gem_bo_unmap_gtt T drm_intel_gem_bo_wait T drm_intel_gem_context_create T drm_intel_gem_context_destroy T drm_intel_gem_context_get_id T drm_intel_get_aperture_sizes T drm_intel_get_eu_total T drm_intel_get_min_eu_in_pool T drm_intel_get_pipe_from_crtc_id T drm_intel_get_pooled_eu T drm_intel_get_reset_stats T drm_intel_get_subslice_total T