genode

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Commit Graph

Author	SHA1	Message	Date
Norman Feske	40a5af42eb	Clean up base-library structure This patch moves the base library from src/base to src/lib/base, flattens the library-internal directory structure, and moves the common parts of the library-description files to base/lib/mk/base.inc and base/lib/mk/base-common.inc. Furthermore, the patch fixes a few cosmetic issues (whitespace and comments only) that I encountered while browsing the result. Fixes #1952	2016-05-09 13:24:11 +02:00
Mark Vels	1668983efa	base-hw: RISC-V Rocket Core on Zynq This commit adds rocket core on the Zynq FPGA support to base HW. It also takes advantage of the new timer infrastructure introduced with the privileged 1.8 and adds improved TLB flush support. fixes #1880	2016-02-26 11:36:51 +01:00
Sebastian Sumpf	c246a0d194	base-hw: initial RISC-V support using the spike instruction emulator issue #1880	2016-02-26 11:36:51 +01:00

Author

SHA1

Message

Date

Norman Feske

40a5af42eb

Clean up base-library structure

This patch moves the base library from src/base to src/lib/base,
flattens the library-internal directory structure, and moves the common
parts of the library-description files to base/lib/mk/base.inc and
base/lib/mk/base-common.inc.

Furthermore, the patch fixes a few cosmetic issues (whitespace and
comments only) that I encountered while browsing the result.

Fixes #1952

2016-05-09 13:24:11 +02:00

Mark Vels

1668983efa

base-hw: RISC-V Rocket Core on Zynq

This commit adds rocket core on the Zynq FPGA support to base HW. It also takes
advantage of the new timer infrastructure introduced with the privileged 1.8 and
adds improved TLB flush support.

fixes #1880

2016-02-26 11:36:51 +01:00

Sebastian Sumpf

c246a0d194

base-hw: initial RISC-V support

using the spike instruction emulator

issue #1880

2016-02-26 11:36:51 +01:00

3 Commits