Commit Graph

5 Commits

Author SHA1 Message Date
Stefan Kalkowski
80fa23da5e hw: increase timing accuracy of kernel (fix #3081)
* Introduce 64-bit tick counter
* Let the timer always count when possible, also if it already fired
* Simplify the kernel syscall API to have one current time call,
  which returns the elapsed microseconds since boot
2019-03-18 15:56:23 +01:00
Stefan Kalkowski
96eb82574a hw: fix race in core's pager code (fix #2301)
* Acknowledge receive of page-fault signal with ack_signal,
  but restart thread execution separately
* use kill_signal_context when disolving a pager_object to prevent race
* Remove bureaucracy in form of Thread_event and Signal_ack_handler
* remove dead code in riscv, namely Thread_base definition
* translation_table_insertions function for ARM drops out,
  which was overcautious
2017-03-15 12:24:41 +01:00
Norman Feske
29b8d609c9 Adjust file headers to refer to the AGPLv3 2017-02-28 12:59:29 +01:00
Mark Vels
1668983efa base-hw: RISC-V Rocket Core on Zynq
This commit adds rocket core on the Zynq FPGA support to base HW. It also takes
advantage of the new timer infrastructure introduced with the privileged 1.8 and
adds improved TLB flush support.

fixes #1880
2016-02-26 11:36:51 +01:00
Sebastian Sumpf
c246a0d194 base-hw: initial RISC-V support
using the spike instruction emulator

issue #1880
2016-02-26 11:36:51 +01:00