Commit Graph

4 Commits

Author SHA1 Message Date
Stefan Kalkowski
7e1692d997 core: unify handling of boot modules
Instead of solving the problem to deliver ROM modules to core while booting
differently for the several kernels (multi-boot, elfweaver, core re-linking),
this commit unifies the approaches. It always builds core as a library, and
after all binaries are built from a run-script, the run-tool will link an
ELF image out of the core-library and all boot modules. Thereby, core can
access its ROM modules directly.

This approach now works for all kernels except Linux.

With this solution, there is no [build_dir]/bin/core binary available anymore.
For debugging purposes you will find a core binary without boot modules, but
with debug symbols under [run_dir].core.

Fix #2095
2016-11-08 15:26:27 +01:00
Sebastian Sumpf
d17134baef ldso: Support for RISC-V
issue #1880
2016-02-26 11:36:51 +01:00
Mark Vels
1668983efa base-hw: RISC-V Rocket Core on Zynq
This commit adds rocket core on the Zynq FPGA support to base HW. It also takes
advantage of the new timer infrastructure introduced with the privileged 1.8 and
adds improved TLB flush support.

fixes #1880
2016-02-26 11:36:51 +01:00
Sebastian Sumpf
c246a0d194 base-hw: initial RISC-V support
using the spike instruction emulator

issue #1880
2016-02-26 11:36:51 +01:00