4 Commits

Author	SHA1	Message	Date
Stefan Kalkowski	42db1e112b	hw: introduce kernel/user address space split ... * introduces central memory map for core/kernel * on 32-bit platforms the kernel/core starts at 0x80000000 * on 64-bit platforms the kernel/core starts at 0xffffffc000000000 * mark kernel/core mappings as global ones (tagged TLB) * move the exception vector to begin of core's binary, thereby bootstrap knows from where to map it appropriately * do not map boot modules into core anymore * constrain core's virtual heap memory area * differentiate in between user's and core's main thread's UTCB, which now resides inside the kernel segment Ref #2091	2017-10-19 13:31:17 +02:00
Sebastian Sumpf	c3cf7f3c3a	riscv: ISA-1.9.1 and GCC-6.3.0 adaptions ... Adds 1.9.1 support to base-hw Note: * the kernel timer is not working * dynamic linking is currently not supported	2017-05-31 13:16:24 +02:00
Stefan Kalkowski	67ba7b89a7	hw: separate bootstrap and core strictly ... * Introduce Hw namespace and library files under src/lib/hw * Introduce Bootstrap namespace * Move all initialization logic into Bootstrap namespace Ref #2388	2017-05-31 13:15:52 +02:00
Stefan Kalkowski	cf943dac65	hw: bootstrap into kernel ... Put the initialization of the cpu cores, setup of page-tables, enabling of MMU and caches into a separate component that is only used to bootstrap the kernel resp. core. Ref #2092	2017-02-23 14:54:42 +01:00