Commit Graph

8 Commits

Author SHA1 Message Date
Norman Feske
cfd013a01a os/include: use C++20 function template syntax
Issue #5227
2024-05-29 09:18:12 +02:00
Martin Stein
1336b0a751 mmio: upper-bounds checks
The classes Genode::Mmio, Genode::Register_set, Genode::Attached_mmio, and
Platform::Device::Mmio now receive a template parameter 'size_t SIZE'. In each
type that derives from one of these classes, it is now statically checked that
the range of each Genode::Register::Register- and
Genode::Register_set::Register_array-deriving sub-type is within [0..SIZE).

That said, SIZE is the minimum size of the memory region provided to the above
mentioned Mmio classes in order to avoid page faults or memory corruption when
accessing the registers and register arrays declared inside.

Note, that the range end of a register array is not the end of the last item
but the end of integer access that is used for accessing the last bit in the
last item.

The constructors of Genode::Mmio, Genode::Attached_mmio, and
Platform::Device::Mmio now receive an argument 'Byte_range_ptr range' that is
expected to be the range of the backing memory region. In each type that derives
from on of these classes, it is now dynamically checked that 'range.num_bytes
>= SIZE', thereby implementing the above mention protection against page faults
and memory corruption.

The rest of the commit adapts the code throughout the Genode Labs repositories
regarding the changes. Note that for that code inside Core, the commits mostly
uses a simplified approach by constructing MMIO objects with range
[base..base+SIZE) and not with a mapping- or specification-related range size.
This should be fixed in the future.

Furthermore, there are types that derive from an MMIO class but don't declare
any registers or register arrays (especially with Platform::Device::Mmio). In
this case SIZE is set to 0. This way, the parameters must be actively corrected
by someone who later wants to add registers or register arrays, plus the places
can be easily found by grep'ing for Mmio<0>.

Fix #4081
2024-02-26 08:59:07 +01:00
Stefan Kalkowski
adc594a7e6 os: remove conversion warnings/errors from virtio
The read_config and write_config functions in the generic virtio
headers used by all drivers lead to compiler warnings resp. errors
if effective-c++ switch is enabled. Moreover, the functions require
to define the access width as parameter. We can better turn them
into template functions using the value type to read resp. write to
derive the access width.

Ref genodelabs/genode#4344
2023-02-27 08:22:49 +01:00
Stefan Kalkowski
ec6f89111e virtio_pci: use generic platform API
Ref genodelabs/genode#4578
2022-10-12 12:09:34 +02:00
Stefan Kalkowski
bb285bf758 Convert virtio to use Platform::Session::dma_addr
Issue #2243
2022-02-15 10:17:28 +01:00
Stefan Kalkowski
7db602faec os: deprecate platform API for x86, rpi, imx53
* Move platform APIs to "legacy/" subdirectory
* Rename old pc, imx53, and rpi platform_drv
  to "legacy_*_platform_drv"

Fix #4359
2022-01-19 12:38:12 +01:00
Stefan Kalkowski
421d2bed40 platform driver: make device info XML optional
* The device XML information dataspace is only provided,
  when the client's policy states `info="yes"`
* The device XM information gets changed to include the
  physical resource names (I/O memory and IRQ addresses)
  instead of virtual ids and page offset

Fix #4077
2021-05-05 11:31:16 +02:00
Piotr Tworek
7fbb245710 os: add VirtIO device helper classes.
To simplify writing native VirtIO drivers for Genode add helper classes
representing VirtIO device and queue. The queue implementation should
be platform independant. The device abstraction however is closely tied
to the VirtIO transport being used (PCI/MMIO). Both PCI and MMIO
implementations expose the same public API so the actual driver logic
should be the same regardless of which transport is used.

Its also important to note that the PCI version of Virtio::Device
currently does not support MSI-X interrupts. Unfortunately my kowledge
about PCI bus is very limited and my main area of interest was to get
VirtIO drivers working on virt_qemu ARM/Aarch64 platform. As such all
the VirtIO drivers I plan to submit will work with PCI bus, but might
not use some extended capabilities.

Ref #3825
2020-10-09 13:35:57 +02:00