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pci: extend Pci utilities for bridge drivers
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@ -142,8 +142,15 @@ struct Pci::Config : Genode::Mmio
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struct Capability_pointer : Register<0x34, 8> {};
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struct Irq_line : Register<0x3c, 8> {};
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struct Irq_pin : Register<0x3d, 8> {};
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struct Irq_line : Register<0x3c, 8>
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{
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enum { UNKNOWN = 0xff };
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};
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struct Irq_pin : Register<0x3d, 8>
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{
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enum { NO_INT = 0, INTA, INTB, INTC, INTD };
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};
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/**********************
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@ -418,6 +425,9 @@ struct Pci::Config : Genode::Mmio
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Genode::Constructible<Pci_express_capability> pci_e_cap {};
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Genode::Constructible<Advanced_error_reporting_capability> adv_err_cap {};
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Base_address bar0 { base() + BASE_ADDRESS_0 };
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Base_address bar1 { base() + BASE_ADDRESS_0 + 0x4 };
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void clear_errors() {
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if (adv_err_cap.constructed()) adv_err_cap->clear(); }
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@ -522,6 +532,11 @@ struct Pci::Config_type0 : Pci::Config
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struct Expansion_rom_base_addr : Register<0x30, 32> {};
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using Pci::Config::Config;
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Base_address bar2 { base() + BASE_ADDRESS_0 + 0x8 };
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Base_address bar3 { base() + BASE_ADDRESS_0 + 0xc };
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Base_address bar4 { base() + BASE_ADDRESS_0 + 0x10 };
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Base_address bar5 { base() + BASE_ADDRESS_0 + 0x14 };
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};
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@ -536,7 +551,8 @@ struct Pci::Config_type1 : Pci::Config
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struct Io_base_limit : Register<0x1c, 16> {};
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struct Memory_base_limit : Register<0x20, 32> {};
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struct Memory_base : Register<0x20, 16> {};
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struct Memory_limit : Register<0x22, 16> {};
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struct Prefetchable_memory_base : Register<0x24, 32> {};
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struct Prefetchable_memory_base_upper : Register<0x28, 32> {};
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