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hw & arm_v6: clean up TLB driver

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ref #1006
This commit is contained in:
Martin Stein 2013-12-20 15:19:35 +01:00 committed by Norman Feske
parent 1730e10469
commit f0c54a7ca3
1 changed files with 69 additions and 75 deletions
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144
base-hw/src/core/tlb/arm_v6.h
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@ -24,90 +24,84 @@ namespace Arm_v6
/**
* First level translation table
*/
class Section_table : public Arm::Section_table
{
public:
/**
* Link to second level translation-table
*/
struct Page_table_descriptor : Arm::Section_table::Page_table_descriptor
{
/**
* Compose descriptor value
*/
static access_t create(Arm::Page_table * const pt,
Section_table *)
{
return Arm::Section_table::Page_table_descriptor::create(pt);
}
};
/**
* Section translation descriptor
*/
struct Section : Arm::Section_table::Section
{
struct P : Bitfield<9, 1> { }; /* enable ECC */
/**
* Compose descriptor value
*/
static access_t create(Page_flags const &flags,
addr_t const pa, Section_table *)
{
return Arm::Section_table::Section::create(flags, pa) |
P::bits(0);
}
};
/**
* Insert one atomic translation into this table
*
* For details see 'Arm::Section_table::insert_translation'
*/
size_t
insert_translation(addr_t const vo, addr_t const pa,
size_t const size_log2,
Page_flags const &flags,
void * const extra_space = 0) {
return Arm::Section_table::
insert_translation<Section_table>(vo, pa, size_log2, flags,
this, extra_space); }
/**
* Insert translations for given area, do not permit displacement
*
* \param vo virtual offset within this table
* \param s area size
* \param io_mem wether the area maps MMIO
*/
void map_core_area(addr_t vo, size_t s, bool const io_mem) {
Arm::Section_table::map_core_area<Section_table>(vo, s, io_mem,
this); }
};
class Section_table;
}
class Arm_v6::Section_table : public Arm::Section_table
{
private:
typedef Arm::Section_table Base;
public:
/**
* Link to second level translation-table
*/
struct Page_table_descriptor : Base::Page_table_descriptor
{
/**
* Compose descriptor value
*/
static access_t create(Arm::Page_table * const pt, Section_table *)
{
return Base::Page_table_descriptor::create(pt);
}
};
/**
* Section translation descriptor
*/
struct Section : Base::Section
{
/**
* Compose descriptor value
*/
static access_t create(Page_flags const & flags,
addr_t const pa, Section_table *)
{
return Base::Section::create(flags, pa);
}
};
/**
* Insert one atomic translation into this table
*
* For details see 'Base::insert_translation'
*/
size_t insert_translation(addr_t const vo, addr_t const pa,
size_t const size_l2,
Page_flags const & f,
void * const p = 0)
{
return Base::insert_translation(vo, pa, size_l2, f, this, p);
}
/**
* Insert translations for given area, do not permit displacement
*
* \param vo virtual offset within this table
* \param s area size
* \param io_mem wether the area maps MMIO
*/
void map_core_area(addr_t vo, size_t s, bool const io_mem)
{
Base::map_core_area(vo, s, io_mem, this);
}
};
template <typename T>
static typename T::access_t
Arm::memory_region_attr(Page_flags const &flags)
Arm::memory_region_attr(Pageflags const & flags)
{
typedef typename T::Tex Tex;
typedef typename T::C C;
typedef typename T::B B;
/*
* FIXME: upgrade to write-back & write-allocate when !d & c
*/
if(flags.device)
return 0;
if(flags.cacheable)
return Tex::bits(5) | C::bits(0) | B::bits(1);
return Tex::bits(6) | C::bits(1) | B::bits(0);
if(flags.device) { return 0; }
if(flags.cacheable) { return Tex::bits(5) | B::bits(1); }
return Tex::bits(6) | C::bits(1);
}
#endif /* _TLB__ARM_V6_H_ */
#endif /* _TLB__ARM_V6_H_ */