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base-hw: reorganize core-driver headers

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Ref #570
This commit is contained in:
Martin Stein 2012-12-03 17:21:35 +01:00 committed by Norman Feske
parent f1d599ae8a
commit ee6f25a028
33 changed files with 379 additions and 98 deletions
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2
base-hw/include/platform/imx31/drivers/serial_log.h
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@ -15,7 +15,7 @@
#define _INCLUDE__PLATFORM__IMX31__DRIVERS__SERIAL_LOG_H_
/* Genode includes */
#include <drivers/board.h>
#include <imx31/board.h>
#include <drivers/uart/imx31_uart_base.h>
namespace Genode

3
base-hw/lib/mk/platform_imx31/platform_support.mk
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@ -5,7 +5,8 @@
#
# add include paths
INC_DIR += $(REP_DIR)/src/core/include \
INC_DIR += $(REP_DIR)/src/core \
$(REP_DIR)/src/core/include \
$(REP_DIR)/src/core/include/imx31 \
$(BASE_DIR)/src/core/include

3
base-hw/lib/mk/platform_panda/platform_support.mk
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@ -5,7 +5,8 @@
#
# add include paths
INC_DIR += $(REP_DIR)/src/core/include \
INC_DIR += $(REP_DIR)/src/core \
$(REP_DIR)/src/core/include \
$(BASE_DIR)/src/core/include
# add C++ sources

3
base-hw/lib/mk/platform_pbxa9/platform_support.mk
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@ -5,7 +5,8 @@
#
# add include paths
INC_DIR += $(REP_DIR)/src/core/include \
INC_DIR += $(REP_DIR)/src/core \
$(REP_DIR)/src/core/include \
$(BASE_DIR)/src/core/include
# add C++ sources

5
base-hw/lib/mk/trustzone/vea9x4_platform_support.mk
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@ -5,7 +5,8 @@
#
# add include paths
INC_DIR += $(REP_DIR)/src/core/include \
INC_DIR += $(REP_DIR)/src/core \
$(REP_DIR)/src/core/include \
$(BASE_DIR)/src/core/include
SRC_CC = platform_services.cc \
@ -14,4 +15,4 @@ SRC_CC = platform_services.cc \
vpath platform_support.cc $(REP_DIR)/src/core/vea9x4/trustzone
vpath platform_services.cc $(REP_DIR)/src/core/vea9x4/trustzone
vpath vm_session_component.cc $(REP_DIR)/src/core
vpath vm_session_component.cc $(REP_DIR)/src/core

3
base-hw/lib/mk/vea9x4_platform_support.mk
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@ -5,7 +5,8 @@
#
# add include paths
INC_DIR += $(REP_DIR)/src/core/include \
INC_DIR += $(REP_DIR)/src/core \
$(REP_DIR)/src/core/include \
$(BASE_DIR)/src/core/include
# avoid building of this lib with other platforms

95
base-hw/src/core/board/imx31.h Normal file
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@ -0,0 +1,95 @@
/*
* \brief Board driver for core
* \author Martin Stein
* \date 2012-11-01
*/
#ifndef _BOARD__IMX31_H_
#define _BOARD__IMX31_H_
/* Genode includes */
#include <platform/imx31/drivers/board_base.h>
namespace Genode
{
/**
* AHB-lite 2v6 to IP bus interface
*/
class Aips : public Mmio
{
/**
* Configuration of the masters
*/
struct Mpr { enum { ALL_UNBUFFERED_AND_FULLY_TRUSTED = 0x77777777 }; };
struct Mpr1 : Register<0x0, 32>, Mpr { };
struct Mpr2 : Register<0x4, 32>, Mpr { };
/**
* Configuration of the platform peripherals
*/
struct Pacr { enum { ALL_UNBUFFERED_AND_FULLY_UNPROTECTED = 0 }; };
struct Pacr1 : Register<0x20, 32>, Pacr { };
struct Pacr2 : Register<0x24, 32>, Pacr { };
struct Pacr3 : Register<0x28, 32>, Pacr { };
struct Pacr4 : Register<0x2c, 32>, Pacr { };
/**
* Configuration of the off-platform peripherals
*/
struct Opacr1 : Register<0x40, 32>, Pacr { };
struct Opacr2 : Register<0x44, 32>, Pacr { };
struct Opacr3 : Register<0x48, 32>, Pacr { };
struct Opacr4 : Register<0x4c, 32>, Pacr { };
struct Opacr5 : Register<0x50, 32>, Pacr { };
public:
/**
* Constructor
*/
Aips(addr_t const base) : Mmio(base) { }
/**
* Configure this module appropriately for the first kernel run
*/
void prepare_kernel()
{
/* avoid AIPS intervention at any memory access */
write<Mpr1>(Mpr::ALL_UNBUFFERED_AND_FULLY_TRUSTED);
write<Mpr2>(Mpr::ALL_UNBUFFERED_AND_FULLY_TRUSTED);
write<Pacr1>(Pacr::ALL_UNBUFFERED_AND_FULLY_UNPROTECTED);
write<Pacr2>(Pacr::ALL_UNBUFFERED_AND_FULLY_UNPROTECTED);
write<Pacr3>(Pacr::ALL_UNBUFFERED_AND_FULLY_UNPROTECTED);
write<Pacr4>(Pacr::ALL_UNBUFFERED_AND_FULLY_UNPROTECTED);
write<Opacr1>(Pacr::ALL_UNBUFFERED_AND_FULLY_UNPROTECTED);
write<Opacr2>(Pacr::ALL_UNBUFFERED_AND_FULLY_UNPROTECTED);
write<Opacr3>(Pacr::ALL_UNBUFFERED_AND_FULLY_UNPROTECTED);
write<Opacr4>(Pacr::ALL_UNBUFFERED_AND_FULLY_UNPROTECTED);
write<Opacr5>(Pacr::ALL_UNBUFFERED_AND_FULLY_UNPROTECTED);
}
};
struct Board : Board_base
{
/**
* static AIPS 1 instance
*/
static Aips * aips_1() { static Aips a(AIPS_1_MMIO_BASE); return &a; }
/**
* Static AIPS 2 instance
*/
static Aips * aips_2() { static Aips a(AIPS_2_MMIO_BASE); return &a; }
/**
* Configure this module appropriately for the first kernel run
*/
static void prepare_kernel()
{
aips_1()->prepare_kernel();
aips_2()->prepare_kernel();
}
};
}
#endif /* _BOARD__IMX31_H_ */

10
base-hw/src/core/include/arm/cpu.h → base-hw/src/core/cpu/arm.h
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@ -1,5 +1,5 @@
/*
* \brief Simple driver for the ARM core
* \brief CPU driver for core
* \author Martin stein
* \date 2012-09-11
*/
@ -11,8 +11,8 @@
* under the terms of the GNU General Public License version 2.
*/
#ifndef _INCLUDE__ARM__CPU_H_
#define _INCLUDE__ARM__CPU_H_
#ifndef _CPU__ARM_H_
#define _CPU__ARM_H_
/* Genode includes */
#include <util/register.h>
@ -23,7 +23,7 @@ namespace Arm
using namespace Genode;
/**
* ARM core
* CPU driver for core
*/
struct Cpu
{
@ -646,5 +646,5 @@ namespace Arm
};
}
#endif /* _INCLUDE__ARM__CPU_H_ */
#endif /* _CPU__ARM_H_ */

15
base-hw/src/core/include/arm/v6/cpu.h → base-hw/src/core/cpu/arm_v6.h
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@ -1,6 +1,7 @@
/*
* \brief Simple driver for the ARMv6 CPU core
* \brief CPU driver for core
* \author Norman Feske
* \author Martin stein
* \date 2012-08-30
*/
@ -11,22 +12,22 @@
* under the terms of the GNU General Public License version 2.
*/
#ifndef _INCLUDE__ARM_V6__CPU_H_
#define _INCLUDE__ARM_V6__CPU_H_
#ifndef _CPU__ARM_V6_H_
#define _CPU__ARM_V6_H_
/* Genode includes */
#include <drivers/board.h>
#include <board/imx31.h>
#include <base/printf.h>
/* core includes */
#include <arm/cpu.h>
#include <cpu/arm.h>
namespace Arm_v6
{
using namespace Genode;
/**
* ARMv6 core
* CPU driver for core
*/
struct Cpu : Arm::Cpu
{
@ -170,5 +171,5 @@ void Arm::Cpu::flush_data_caches() {
asm volatile ("mcr p15, 0, %[rd], c7, c14, 0" :: [rd]"r"(0) : ); }
#endif /* _INCLUDE__ARM_V6__CPU_H_ */
#endif /* _CPU__ARM_V6_H_ */

12
base-hw/src/core/include/arm/v7/cpu.h → base-hw/src/core/cpu/arm_v7.h
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@ -1,5 +1,5 @@
/*
* \brief Simple driver for the ARMv7 core
* \brief CPU driver for core
* \author Martin stein
* \date 2011-11-03
*/
@ -11,21 +11,21 @@
* under the terms of the GNU General Public License version 2.
*/
#ifndef _INCLUDE__ARM_V7__CPU_H_
#define _INCLUDE__ARM_V7__CPU_H_
#ifndef _CPU__ARM_V7_H_
#define _CPU__ARM_V7_H_
/* Genode includes */
#include <drivers/board_base.h>
/* core includes */
#include <arm/cpu.h>
#include <cpu/arm.h>
namespace Arm_v7
{
using namespace Genode;
/**
* ARMv7 core
* CPU driver for core
*/
struct Cpu : Arm::Cpu
{
@ -305,5 +305,5 @@ Arm::Cpu::Psr::access_t Arm::Cpu::Psr::init_user_with_trustzone()
}
#endif /* _INCLUDE__ARM_V7__CPU_H_ */
#endif /* _CPU__ARM_V7_H_ */

12
base-hw/src/core/include/cortex_a9/cpu.h → base-hw/src/core/cpu/cortex_a9.h
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@ -1,5 +1,5 @@
/*
* \brief Simple driver for the Cortex A9
* \brief CPU driver for core
* \author Martin stein
* \date 2011-11-03
*/
@ -11,21 +11,21 @@
* under the terms of the GNU General Public License version 2.
*/
#ifndef _INCLUDE__CORTEX_A9__CPU_H_
#define _INCLUDE__CORTEX_A9__CPU_H_
#ifndef _CPU__CORTEX_A9_H_
#define _CPU__CORTEX_A9_H_
/* Genode includes */
#include <drivers/board_base.h>
/* core includes */
#include <arm/v7/cpu.h>
#include <cpu/arm_v7.h>
namespace Cortex_a9
{
using namespace Genode;
/**
* Cortex A9 CPU
* CPU driver for core
*/
struct Cpu : Arm_v7::Cpu
{
@ -50,5 +50,5 @@ namespace Cortex_a9
};
}
#endif /* _INCLUDE__CORTEX_A9__CPU_H_ */
#endif /* _CPU__CORTEX_A9_H_ */

16
base-hw/src/core/include/imx31/drivers/board.h → base-hw/src/core/imx31/board.h
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@ -1,14 +1,14 @@
/*
* \brief Board definitions for core
* \brief Board driver for core
* \author Martin Stein
* \date 2012-11-01
*/
#ifndef _INCLUDE__IMX31__DRIVERS__BOARD_H_
#define _INCLUDE__IMX31__DRIVERS__BOARD_H_
#ifndef _BOARD__IMX31_H_
#define _BOARD__IMX31_H_
/* Genode includes */
#include <platform/imx31/drivers/board_base.h>
#include <drivers/board_base.h>
namespace Genode
{
@ -69,10 +69,13 @@ namespace Genode
}
};
/**
* Board driver for core
*/
struct Board : Board_base
{
/**
* static AIPS 1 instance
* Static AIPS 1 instance
*/
static Aips * aips_1() { static Aips a(AIPS_1_MMIO_BASE); return &a; }
@ -92,5 +95,4 @@ namespace Genode
};
}
#endif /* _INCLUDE__IMX31__DRIVERS__BOARD_H_ */
#endif /* _BOARD__IMX31_H_ */

4
base-hw/src/core/imx31/platform_support.cc
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@ -12,8 +12,8 @@
*/
/* Genode includes */
#include <drivers/board.h>
#include <imx31/pic.h>
#include <board/imx31.h>
#include <pic/imx31.h>
/* core includes */
#include <platform.h>

4
base-hw/src/core/imx31/tlb.h
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@ -15,8 +15,8 @@
#define _SRC__CORE__IMX31__TLB_H_
/* Genode includes */
#include <arm/v6/section_table.h>
#include <drivers/board.h>
#include <tlb/arm_v6.h>
#include <board/imx31.h>
/**
* Software TLB-controls

6
base-hw/src/core/include/cortex_a9/kernel_support.h
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@ -15,9 +15,9 @@
#define _CORE__INCLUDE__CORTEX_A9__KERNEL_SUPPORT_H_
/* core includes */
#include <cortex_a9/cpu.h>
#include <cortex_a9/timer.h>
#include <cortex_a9/no_trustzone/pic.h>
#include <cpu/cortex_a9.h>
#include <timer/cortex_a9.h>
#include <pic/cortex_a9_no_trustzone.h>
/**
* CPU driver

6
base-hw/src/core/include/imx31/kernel_support.h
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@ -16,9 +16,9 @@
#define _CORE__INCLUDE__IMX31__KERNEL_SUPPORT_H_
/* Genode includes */
#include <arm/v6/cpu.h>
#include <imx31/timer.h>
#include <imx31/pic.h>
#include <cpu/arm_v6.h>
#include <timer/imx31.h>
#include <pic/imx31.h>
struct Cpu : Arm_v6::Cpu { };

4
base-hw/src/core/panda/platform_support.cc
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@ -15,8 +15,8 @@
#include <drivers/board_base.h>
/* core includes */
#include <cortex_a9/cpu.h>
#include <cortex_a9/no_trustzone/pic.h>
#include <cpu/cortex_a9.h>
#include <pic/cortex_a9_no_trustzone.h>
#include <platform.h>
using namespace Genode;

2
base-hw/src/core/panda/tlb.h
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@ -18,7 +18,7 @@
#include <drivers/board_base.h>
/* core includes */
#include <arm/v7/section_table.h>
#include <tlb/arm_v7.h>
/**
* Software TLB-controls

4
base-hw/src/core/pbxa9/platform_support.cc
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@ -16,8 +16,8 @@
/* core includes */
#include <platform.h>
#include <cortex_a9/cpu.h>
#include <cortex_a9/no_trustzone/pic.h>
#include <cpu/cortex_a9.h>
#include <pic/cortex_a9_no_trustzone.h>
using namespace Genode;

2
base-hw/src/core/pbxa9/tlb.h
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@ -18,7 +18,7 @@
#include <drivers/board_base.h>
/* core includes */
#include <arm/v7/section_table.h>
#include <tlb/arm_v7.h>
/**
* Software TLB-controls

6
base-hw/src/core/include/cortex_a9/pic.h → base-hw/src/core/pic/cortex_a9.h
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@ -11,8 +11,8 @@
* under the terms of the GNU General Public License version 2.
*/
#ifndef _INCLUDE__CORTEX_A9__PIC_H_
#define _INCLUDE__CORTEX_A9__PIC_H_
#ifndef _PIC__CORTEX_A9_H_
#define _PIC__CORTEX_A9_H_
/* Genode includes */
#include <util/mmio.h>
@ -288,5 +288,5 @@ namespace Cortex_a9
};
}
#endif /* _INCLUDE__CORTEX_A9__PIC_H_ */
#endif /* _PIC__CORTEX_A9_H_ */

10
base-hw/src/core/include/cortex_a9/no_trustzone/pic.h → base-hw/src/core/pic/cortex_a9_no_trustzone.h
View File

@ -11,12 +11,12 @@
* under the terms of the GNU General Public License version 2.
*/
#ifndef _INCLUDE__CORTEX_A9__NO_TRUSTZONE__PIC_H_
#define _INCLUDE__CORTEX_A9__NO_TRUSTZONE__PIC_H_
#ifndef _PIC__CORTEX_A9_NO_TRUSTZONE_H_
#define _PIC__CORTEX_A9_NO_TRUSTZONE_H_
/* core includes */
#include <cortex_a9/cpu.h>
#include <cortex_a9/pic.h>
#include <cpu/cortex_a9.h>
#include <pic/cortex_a9.h>
namespace Cortex_a9_no_trustzone
{
@ -66,5 +66,5 @@ namespace Cortex_a9_no_trustzone
};
}
#endif /* _INCLUDE__CORTEX_A9__NO_TRUSTZONE__PIC_H_ */
#endif /* _PIC__CORTEX_A9_NO_TRUSTZONE_H_ */

10
base-hw/src/core/include/imx31/pic.h → base-hw/src/core/pic/imx31.h
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@ -12,12 +12,14 @@
* under the terms of the GNU General Public License version 2.
*/
#ifndef _INCLUDE__IMX31__PIC_H_
#define _INCLUDE__IMX31__PIC_H_
#ifndef _PIC__IMX31_H_
#define _PIC__IMX31_H_
/* Genode includes */
#include <util/mmio.h>
#include <drivers/board.h>
/* core includes */
#include <imx31/board.h>
namespace Imx31
{
@ -193,5 +195,5 @@ namespace Imx31
};
}
#endif /* _INCLUDE__IMX31__PIC_H_ */
#endif /* _PIC__IMX31_H_ */

10
base-hw/src/core/include/vea9x4_trustzone/pic.h → base-hw/src/core/pic/vea9x4_trustzone.h
View File

@ -11,12 +11,12 @@
* under the terms of the GNU General Public License version 2.
*/
#ifndef _INCLUDE__VEA9X4_TRUSTZONE__PIC_H_
#define _INCLUDE__VEA9X4_TRUSTZONE__PIC_H_
#ifndef _PIC__VEA9X4_TRUSTZONE_H_
#define _PIC__VEA9X4_TRUSTZONE_H_
/* core includes */
#include <cortex_a9/cpu.h>
#include <cortex_a9/pic.h>
#include <cpu/cortex_a9.h>
#include <pic/cortex_a9.h>
namespace Vea9x4_trustzone
{
@ -64,5 +64,5 @@ namespace Vea9x4_trustzone
};
}
#endif /* _INCLUDE__VEA9X4_TRUSTZONE__PIC_H_ */
#endif /* _PIC__VEA9X4_TRUSTZONE_H_ */

8
base-hw/src/core/include/cortex_a9/timer.h → base-hw/src/core/timer/cortex_a9.h
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@ -11,14 +11,14 @@
* under the terms of the GNU General Public License version 2.
*/
#ifndef _INCLUDE__CORTEX_A9__TIMER_H_
#define _INCLUDE__CORTEX_A9__TIMER_H_
#ifndef _TIMER__CORTEX_A9_H_
#define _TIMER__CORTEX_A9_H_
/* Genode includes */
#include <util/mmio.h>
/* core includes */
#include <cortex_a9/cpu.h>
#include <cpu/cortex_a9.h>
namespace Cortex_a9
{
@ -127,5 +127,5 @@ namespace Cortex_a9
};
}
#endif /* _INCLUDE__CORTEX_A9__TIMER_H_ */
#endif /* _TIMER__CORTEX_A9_H_ */

176
base-hw/src/core/timer/imx31.h Normal file
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@ -0,0 +1,176 @@
/*
* \brief Timer for core
* \author Martin Stein
* \author Norman Feske
* \date 2012-08-30
*/
/*
* Copyright (C) 2012 Genode Labs GmbH
*
* This file is part of the Genode OS framework, which is distributed
* under the terms of the GNU General Public License version 2.
*/
#ifndef _TIMER__IMX31_H_
#define _TIMER__IMX31_H_
/* Genode includes */
#include <util/mmio.h>
namespace Imx31
{
using namespace Genode;
/**
* Core timer
*/
class Timer : public Mmio
{
enum { TICS_PER_MS = 32 };
/**
* Control register
*/
struct Cr : Register<0x0, 32>
{
struct En : Bitfield<0, 1> { }; /* enable timer */
struct En_mod : Bitfield<1, 1> /* reload or continue on enable */
{
enum { RELOAD = 1 };
};
struct Oci_en : Bitfield<2, 1> { }; /* interrupt on compare */
struct Rld : Bitfield<3, 1> /* reload or roll-over */
{
enum { RELOAD_FROM_LR = 1 };
};
struct Prescaler : Bitfield<4, 12> /* clock input divisor */
{
enum { DIVIDE_BY_1 = 0 };
};
struct Swr : Bitfield<16, 1> { }; /* software reset bit */
struct Iovw : Bitfield<17, 1> { }; /* enable overwrite */
struct Dbg_en : Bitfield<18, 1> { }; /* enable in debug mode */
struct Wait_en : Bitfield<19, 1> { }; /* enable in wait mode */
struct Doz_en : Bitfield<20, 1> { }; /* enable in doze mode */
struct Stop_en : Bitfield<21, 1> { }; /* enable in stop mode */
struct Om : Bitfield<22, 2> /* mode of the output pin */
{
enum { DISCONNECTED = 0 };
};
struct Clk_src : Bitfield<24, 2> /* select clock input */
{
enum { IPG_CLK_32K = 3 };
};
/**
* Register value that configures the timer for a one-shot run
*/
static access_t prepare_one_shot()
{
return En::bits(0) |
En_mod::bits(En_mod::RELOAD) |
Oci_en::bits(1) |
Rld::bits(Rld::RELOAD_FROM_LR) |
Prescaler::bits(Prescaler::DIVIDE_BY_1) |
Swr::bits(0) |
Iovw::bits(0) |
Dbg_en::bits(0) |
Wait_en::bits(0) |
Doz_en::bits(0) |
Stop_en::bits(0) |
Om::bits(Om::DISCONNECTED) |
Clk_src::bits(Clk_src::IPG_CLK_32K);
}
};
/**
* Status register
*/
struct Sr : Register<0x4, 32>
{
struct Ocif : Bitfield<0, 1> { }; /* IRQ status, write 1 clears */
};
struct Lr : Register<0x8, 32> { }; /* load value register */
struct Cmpr : Register<0xc, 32> { }; /* compare value register */
struct Cnt : Register<0x10, 32> { }; /* counter register */
/**
* Disable timer and clear its interrupt output
*/
void _reset()
{
/* wait until ongoing reset operations are finished */
while (read<Cr::Swr>()) ;
/* disable timer */
write<Cr::En>(0);
clear_interrupt();
}
public:
enum { IRQ = Board::EPIT_1_IRQ };
/**
* Constructor
*/
Timer() : Mmio(Board::EPIT_1_MMIO_BASE) { _reset(); }
/**
* Start a one-shot run
*
* \param tics native timer value used to assess the delay
* of the timer interrupt as of the call
*/
void start_one_shot(unsigned const tics)
{
/* stop timer */
_reset();
/* configure timer for a one-shot */
write<Cr>(Cr::prepare_one_shot());
write<Lr>(tics);
write<Cmpr>(0);
/* start timer */
write<Cr::En>(1);
}
/**
* Stop the timer from a one-shot run
*
* \return last native timer value of the one-shot run
*/
unsigned long stop_one_shot()
{
/* disable timer */
write<Cr::En>(0);
/* if the timer has hit zero already return 0 */
return read<Sr::Ocif>() ? 0 : read<Cnt>();
}
/**
* Clear interrupt output line
*/
void clear_interrupt() { write<Sr::Ocif>(1); }
/**
* Translate milliseconds to a native timer value
*/
static unsigned ms_to_tics(unsigned const ms) {
return TICS_PER_MS * ms; }
};
}
#endif /* _TIMER__IMX31_H_ */

8
base-hw/src/core/include/arm/section_table.h → base-hw/src/core/tlb/arm.h
View File

@ -1,5 +1,5 @@
/*
* \brief Driver for ARM section tables
* \brief TLB driver for core
* \author Martin Stein
* \date 2012-02-22
*/
@ -11,8 +11,8 @@
* under the terms of the GNU General Public License version 2.
*/
#ifndef _INCLUDE__ARM__SECTION_TABLE_H_
#define _INCLUDE__ARM__SECTION_TABLE_H_
#ifndef _TLB__ARM_H_
#define _TLB__ARM_H_
/* Genode includes */
#include <util/register.h>
@ -962,5 +962,5 @@ namespace Arm
} __attribute__((aligned(1<<Section_table::ALIGNM_LOG2)));
}
#endif /* _INCLUDE__ARM__SECTION_TABLE_H_ */
#endif /* _TLB__ARM_H_ */

10
base-hw/src/core/include/arm/v6/section_table.h → base-hw/src/core/tlb/arm_v6.h
View File

@ -1,5 +1,5 @@
/*
* \brief Driver for ARMv6 section tables
* \brief TLB driver for core
* \author Martin Stein
* \date 2012-02-22
*/
@ -11,11 +11,11 @@
* under the terms of the GNU General Public License version 2.
*/
#ifndef _INCLUDE__ARM_V6__SECTION_TABLE_H_
#define _INCLUDE__ARM_V6__SECTION_TABLE_H_
#ifndef _TLB__ARM_V6_H_
#define _TLB__ARM_V6_H_
/* core includes */
#include <arm/section_table.h>
#include <tlb/arm.h>
namespace Arm_v6
{
@ -92,5 +92,5 @@ namespace Arm_v6
bool Arm::cache_support() { return 0; }
#endif /* _INCLUDE__ARM_V6__SECTION_TABLE_H_ */
#endif /* _TLB__ARM_V6_H_ */

12
base-hw/src/core/include/arm/v7/section_table.h → base-hw/src/core/tlb/arm_v7.h
View File

@ -1,5 +1,5 @@
/*
* \brief Driver for ARMv7 section tables
* \brief TLB driver for core
* \author Martin Stein
* \date 2012-02-22
*/
@ -11,12 +11,12 @@
* under the terms of the GNU General Public License version 2.
*/
#ifndef _INCLUDE__ARM_V7__SECTION_TABLE_H_
#define _INCLUDE__ARM_V7__SECTION_TABLE_H_
#ifndef _TLB__ARM_V7_H_
#define _TLB__ARM_V7_H_
/* core includes */
#include <arm/section_table.h>
#include <arm/v7/cpu.h>
#include <tlb/arm.h>
#include <cpu/arm_v7.h>
namespace Arm_v7
{
@ -115,5 +115,5 @@ namespace Arm_v7
bool Arm::cache_support() { return 1; }
#endif /* _INCLUDE__ARM_V7__SECTION_TABLE_H_ */
#endif /* _TLB__ARM_V7_H_ */

4
base-hw/src/core/vea9x4/platform_support.cc
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@ -16,8 +16,8 @@
/* Core includes */
#include <platform.h>
#include <cortex_a9/cpu.h>
#include <cortex_a9/no_trustzone/pic.h>
#include <cpu/cortex_a9.h>
#include <pic/cortex_a9_no_trustzone.h>
using namespace Genode;

2
base-hw/src/core/vea9x4/tlb.h
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@ -18,7 +18,7 @@
#include <drivers/board_base.h>
/* core includes */
#include <arm/v7/section_table.h>
#include <tlb/arm_v7.h>
/**
* Software TLB-controls

6
base-hw/src/core/vea9x4/trustzone/kernel_support.h
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@ -15,9 +15,9 @@
#define _SRC__CORE__VEA9X4__TRUSTZONE__KERNEL_SUPPORT_H_
/* Core includes */
#include <cortex_a9/cpu.h>
#include <cortex_a9/timer.h>
#include <vea9x4_trustzone/pic.h>
#include <timer/cortex_a9.h>
#include <cpu/cortex_a9.h>
#include <pic/vea9x4_trustzone.h>
/**
* CPU driver

4
base-hw/src/core/vea9x4/trustzone/platform_support.cc
View File

@ -16,8 +16,8 @@
/* Core includes */
#include <platform.h>
#include <vea9x4_trustzone/pic.h>
#include <cortex_a9/cpu.h>
#include <pic/vea9x4_trustzone.h>
#include <cpu/cortex_a9.h>
using namespace Genode;