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https://github.com/genodelabs/genode.git
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base-hw: move imx53-specifics to imx repository
Ref genodelabs/genode#5252
This commit is contained in:
Stefan Kalkowski
Norman Feske
parent
0c8abf9b50
commit
e93f5fe8e0
@ -1 +0,0 @@
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arm_v7a
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@ -1 +0,0 @@
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0x70010000
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@ -1 +0,0 @@
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arm_v7a
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@ -1 +0,0 @@
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0x70010000
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@ -1 +0,0 @@
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arm_v7a
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@ -1 +0,0 @@
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0x72000000
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@ -1,36 +0,0 @@
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/*
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* \brief TrustZone specific definitions for the i.MX53 board
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* \author Stefan Kalkowski
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* \date 2013-11-15
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*/
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/*
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* Copyright (C) 2013-2017 Genode Labs GmbH
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*
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* This file is part of the Genode OS framework, which is distributed
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* under the terms of the GNU Affero General Public License version 3.
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*/
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#ifndef _INCLUDE__SPEC__IMX53__DRIVERS__TRUSTZONE_H_
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#define _INCLUDE__SPEC__IMX53__DRIVERS__TRUSTZONE_H_
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/* Genode includes */
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#include <drivers/defs/imx53.h>
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namespace Trustzone {
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enum {
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/**
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* Currently, we limit secure RAM to 256 MB only,
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* because the memory protection feature of the M4IF
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* on this platform allows to protect a max. region of
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* 256MB per RAM bank only.
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*/
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SECURE_RAM_BASE = Imx53::RAM_BANK_0_BASE,
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SECURE_RAM_SIZE = 256 * 1024 * 1024,
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NONSECURE_RAM_BASE = Imx53::RAM_BANK_0_BASE + SECURE_RAM_SIZE,
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NONSECURE_RAM_SIZE = 256 * 1024 * 1024,
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};
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}
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#endif /* _INCLUDE__SPEC__IMX53__DRIVERS__TRUSTZONE_H_ */
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@ -1,7 +0,0 @@
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REP_INC_DIR += src/bootstrap/board/imx53_qsb
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SRC_CC += bootstrap/spec/arm/cortex_a8_mmu.cc
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SRC_CC += bootstrap/spec/arm/cpu.cc
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SRC_CC += bootstrap/spec/arm/imx_tzic.cc
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include $(call select_from_repositories,lib/mk/spec/arm_v7/bootstrap-hw.inc)
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@ -1,3 +0,0 @@
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SRC_CC += bootstrap/board/imx53_qsb/platform.cc
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include $(call select_from_repositories,lib/mk/spec/arm_v7/bootstrap-hw-imx53_qsb.inc)
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@ -1,3 +0,0 @@
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SRC_CC += bootstrap/board/imx53_qsb/platform_trustzone.cc
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include $(call select_from_repositories,lib/mk/spec/arm_v7/bootstrap-hw-imx53_qsb.inc)
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@ -1,8 +0,0 @@
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REP_INC_DIR += src/bootstrap/board/usb_armory
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SRC_CC += bootstrap/board/usb_armory/platform.cc
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SRC_CC += bootstrap/spec/arm/cortex_a8_mmu.cc
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SRC_CC += bootstrap/spec/arm/cpu.cc
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SRC_CC += bootstrap/spec/arm/imx_tzic.cc
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include $(call select_from_repositories,lib/mk/spec/arm_v7/bootstrap-hw.inc)
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@ -1,6 +0,0 @@
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REP_INC_DIR += src/core/board/imx53_qsb
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SRC_CC += spec/arm/imx_epit.cc
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SRC_CC += spec/arm/imx_tzic.cc
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include $(call select_from_repositories,lib/mk/spec/cortex_a8/core-hw.inc)
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@ -1,5 +0,0 @@
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SRC_CC += kernel/vm_thread_off.cc
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SRC_CC += platform_services.cc
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# include less specific configuration
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include $(call select_from_repositories,lib/mk/spec/arm_v7/core-hw-imx53_qsb.inc)
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@ -1,13 +0,0 @@
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REP_INC_DIR += src/core/spec/arm_v7/trustzone
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SRC_CC += kernel/vm_thread_on.cc
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SRC_CC += spec/arm_v7/trustzone/kernel/vm.cc
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SRC_CC += spec/arm_v7/trustzone/platform_services.cc
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SRC_CC += spec/arm_v7/trustzone/vm_session_component.cc
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SRC_CC += vm_session_common.cc
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SRC_CC += vm_session_component.cc
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SRC_S += spec/arm_v7/trustzone/exception_vector.s
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# include less specific configuration
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include $(call select_from_repositories,lib/mk/spec/arm_v7/core-hw-imx53_qsb.inc)
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@ -1,25 +0,0 @@
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#
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# \brief Build config for parts of core that depend on Trustzone status
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# \author Martin Stein
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# \date 2015-10-30
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#
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# add include paths
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REP_INC_DIR += src/core/board/usb_armory
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REP_INC_DIR += src/core/spec/arm_v7/trustzone
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# add C++ sources
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SRC_CC += kernel/vm_thread_on.cc
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SRC_CC += spec/arm/imx_epit.cc
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SRC_CC += spec/arm/imx_tzic.cc
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SRC_CC += spec/arm_v7/trustzone/kernel/vm.cc
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SRC_CC += spec/arm_v7/trustzone/platform_services.cc
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SRC_CC += spec/arm_v7/trustzone/vm_session_component.cc
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SRC_CC += vm_session_common.cc
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SRC_CC += vm_session_component.cc
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# add assembly sources
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SRC_S += spec/arm_v7/trustzone/exception_vector.s
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# include less specific configuration
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include $(call select_from_repositories,lib/mk/spec/cortex_a8/core-hw.inc)
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@ -1,12 +0,0 @@
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#
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# \brief Build config for Genodes core process
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# \author Stefan Kalkowski
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# \date 2014-09-02
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#
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# add C++ sources
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SRC_CC += kernel/cpu_up.cc
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SRC_CC += kernel/lock.cc
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# include less specific configuration
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include $(call select_from_repositories,lib/mk/spec/arm_v7/core-hw.inc)
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@ -1 +0,0 @@
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include $(GENODE_DIR)/repos/base-hw/recipes/src/base-hw_content.inc
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@ -1 +0,0 @@
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2024-06-19 b82fe2048a2a47c4d78e2c8f8155737aa6dbb038
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@ -1,2 +0,0 @@
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base-hw
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base
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@ -1,6 +0,0 @@
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CONTENT += src/core/board/imx53_qsb \
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src/bootstrap/board/imx53_qsb \
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lib/mk/spec/arm_v7/core-hw-imx53_qsb.inc \
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lib/mk/spec/arm_v7/bootstrap-hw-imx53_qsb.inc
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include $(GENODE_DIR)/repos/base-hw/recipes/src/base-hw_content.inc
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@ -1 +0,0 @@
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2024-06-19 4ab83110a020ad753e3faf76d556d39b73b3afe0
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@ -1,2 +0,0 @@
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base-hw
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base
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@ -24,7 +24,7 @@ BOARD := $(patsubst base-hw-%,%,$(_BOARD))
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#
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LIB_MK_SPECS(arm_v6) := arm arm_v6
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LIB_MK_SPECS(arm_v7a) := arm arm_v7 cortex_a8 cortex_a9 cortex_a15
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LIB_MK_SPECS(arm_v7a) := arm arm_v7 cortex_a9 cortex_a15
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LIB_MK_SPECS(arm_v8a) := arm_64 arm_v8
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LIB_MK_SPECS(x86_64) := x86_64
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LIB_MK_SPECS(riscv) := riscv
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@ -1,32 +0,0 @@
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/*
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* \brief i.MX53 Quickstart board definitions
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* \author Stefan Kalkowski
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* \date 2017-03-22
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*/
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/*
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* Copyright (C) 2017 Genode Labs GmbH
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*
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* This file is part of the Genode OS framework, which is distributed
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* under the terms of the GNU Affero General Public License version 3.
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*/
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#ifndef _SRC__BOOTSTRAP__SPEC__IMX53_QSB__BOARD_H_
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#define _SRC__BOOTSTRAP__SPEC__IMX53_QSB__BOARD_H_
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#include <hw/spec/arm/imx53_qsb_board.h>
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#include <hw/spec/arm/imx_tzic.h>
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#include <spec/arm/cortex_a8_page_table.h>
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#include <spec/arm/cpu.h>
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namespace Board {
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using namespace Hw::Imx53_qsb_board;
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using Hw::Pic;
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bool secure_irq(unsigned irq);
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}
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#endif /* _SRC__BOOTSTRAP__SPEC__IMX53_QSB__BOARD_H_ */
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@ -1,32 +0,0 @@
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/*
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* \brief Specific i.MX53 bootstrap implementations
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* \author Stefan Kalkowski
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* \date 2012-10-24
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*/
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/*
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* Copyright (C) 2012-2017 Genode Labs GmbH
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*
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* This file is part of the Genode OS framework, which is distributed
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* under the terms of the GNU Affero General Public License version 3.
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*/
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#include <platform.h>
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#include <spec/arm/imx_aipstz.h>
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using namespace Board;
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bool Board::secure_irq(unsigned) { return true; }
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Bootstrap::Platform::Board::Board()
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:
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early_ram_regions(Memory_region { RAM0_BASE, RAM0_SIZE },
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Memory_region { RAM1_BASE, RAM1_SIZE }),
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core_mmio(Memory_region { UART_1_MMIO_BASE, UART_1_MMIO_SIZE },
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Memory_region { EPIT_1_MMIO_BASE, EPIT_1_MMIO_SIZE },
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Memory_region { IRQ_CONTROLLER_BASE, IRQ_CONTROLLER_SIZE })
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{
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Aipstz aipstz_1(AIPS_1_MMIO_BASE);
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Aipstz aipstz_2(AIPS_2_MMIO_BASE);
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}
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@ -1,59 +0,0 @@
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/*
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* \brief Specific i.MX53 bootstrap implementations
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* \author Stefan Kalkowski
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* \date 2012-10-24
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*/
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/*
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* Copyright (C) 2012-2017 Genode Labs GmbH
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*
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* This file is part of the Genode OS framework, which is distributed
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* under the terms of the GNU Affero General Public License version 3.
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*/
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#include <platform.h>
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#include <drivers/defs/imx53_trustzone.h>
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#include <spec/arm/imx_aipstz.h>
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#include <spec/arm/imx_csu.h>
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using namespace Board;
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bool Board::secure_irq(unsigned i)
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{
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if (i == EPIT_1_IRQ) return true;
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if (i == EPIT_2_IRQ) return true;
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if (i == I2C_2_IRQ) return true;
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if (i == I2C_3_IRQ) return true;
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if (i == SDHC_IRQ) return true;
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if (i >= GPIO1_IRQL && i <= GPIO4_IRQH) return true;
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if (i >= GPIO5_IRQL && i <= GPIO7_IRQH) return true;
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return false;
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}
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Bootstrap::Platform::Board::Board()
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:
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early_ram_regions(Memory_region { Trustzone::SECURE_RAM_BASE,
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Trustzone::SECURE_RAM_SIZE }),
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core_mmio(Memory_region { UART_1_MMIO_BASE, UART_1_MMIO_SIZE },
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Memory_region { EPIT_1_MMIO_BASE, EPIT_1_MMIO_SIZE },
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Memory_region { IRQ_CONTROLLER_BASE, IRQ_CONTROLLER_SIZE },
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Memory_region { CSU_BASE, CSU_SIZE })
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{
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Aipstz aipstz_1(AIPS_1_MMIO_BASE);
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Aipstz aipstz_2(AIPS_2_MMIO_BASE);
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/* set exception vector entry */
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Cpu::Mvbar::write(Hw::Mm::system_exception_vector().base);
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/* enable coprocessor 10 + 11 access for TZ VMs */
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Cpu::Nsacr::access_t v = 0;
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Cpu::Nsacr::Cpnsae10::set(v, 1);
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Cpu::Nsacr::Cpnsae11::set(v, 1);
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Cpu::Nsacr::write(v);
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/* configure central security unit */
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Csu csu(CSU_BASE, false, true, false, true);
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}
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@ -1,32 +0,0 @@
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/*
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* \brief i.MX53 Quickstart board definitions
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* \author Stefan Kalkowski
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* \date 2017-03-22
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*/
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/*
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* Copyright (C) 2017 Genode Labs GmbH
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*
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* This file is part of the Genode OS framework, which is distributed
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* under the terms of the GNU Affero General Public License version 3.
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*/
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#ifndef _SRC__BOOTSTRAP__SPEC__USB_ARMORY__BOARD_H_
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#define _SRC__BOOTSTRAP__SPEC__USB_ARMORY__BOARD_H_
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#include <hw/spec/arm/usb_armory_board.h>
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#include <hw/spec/arm/imx_tzic.h>
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#include <spec/arm/cortex_a8_page_table.h>
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#include <spec/arm/cpu.h>
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namespace Board {
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using namespace Hw::Usb_armory_board;
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using Hw::Pic;
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bool secure_irq(unsigned irq);
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}
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#endif /* _SRC__BOOTSTRAP__SPEC__USB_ARMORY__BOARD_H_ */
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@ -1,56 +0,0 @@
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/*
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* \brief Specific i.MX53 bootstrap implementations
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* \author Stefan Kalkowski
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* \date 2012-10-24
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*/
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/*
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* Copyright (C) 2012-2017 Genode Labs GmbH
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*
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* This file is part of the Genode OS framework, which is distributed
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* under the terms of the GNU Affero General Public License version 3.
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*/
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#include <platform.h>
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#include <drivers/defs/imx53_trustzone.h>
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#include <spec/arm/imx_aipstz.h>
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#include <spec/arm/imx_csu.h>
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using namespace Board;
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bool Board::secure_irq(unsigned i)
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{
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if (i == EPIT_1_IRQ) return true;
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if (i == EPIT_2_IRQ) return true;
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if (i == SDHC_IRQ) return true;
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return false;
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}
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Bootstrap::Platform::Board::Board()
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:
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early_ram_regions(Memory_region { Trustzone::SECURE_RAM_BASE,
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Trustzone::SECURE_RAM_SIZE }),
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core_mmio(Memory_region { UART_1_MMIO_BASE, UART_1_MMIO_SIZE },
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Memory_region { EPIT_1_MMIO_BASE, EPIT_1_MMIO_SIZE },
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Memory_region { IRQ_CONTROLLER_BASE, IRQ_CONTROLLER_SIZE },
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Memory_region { CSU_BASE, CSU_SIZE })
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{
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Aipstz aipstz_1(AIPS_1_MMIO_BASE);
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Aipstz aipstz_2(AIPS_2_MMIO_BASE);
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Pic pic {};
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/* set monitor mode exception vector entry */
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Cpu::Mvbar::write(Hw::Mm::system_exception_vector().base);
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/* enable coprocessor 10 + 11 access for TZ VMs */
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Cpu::Nsacr::access_t v = 0;
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Cpu::Nsacr::Cpnsae10::set(v, 1);
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Cpu::Nsacr::Cpnsae11::set(v, 1);
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Cpu::Nsacr::write(v);
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/* configure central security unit */
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Csu csu(CSU_BASE, true, false, true, false);
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}
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@ -1,86 +0,0 @@
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/*
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* \brief Driver for Freescale's AIPSTZ bridge
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* \author Stefan Kalkowski
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* \author Martin Stein
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* \date 2012-10-24
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*/
|
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|
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/*
|
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* Copyright (C) 2012-2017 Genode Labs GmbH
|
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*
|
||||
* This file is part of the Genode OS framework, which is distributed
|
||||
* under the terms of the GNU Affero General Public License version 3.
|
||||
*/
|
||||
|
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#ifndef _SRC__BOOTSTRAP__SPEC__ARM__IMX_AIPSTZ_H_
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#define _SRC__BOOTSTRAP__SPEC__ARM__IMX_AIPSTZ_H_
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#include <util/mmio.h>
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namespace Bootstrap {
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/**
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* AHB to IP Bridge
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*
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* Interface between the system bus and lower bandwidth IP Slave (IPS)
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* bus peripherals.
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*/
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class Aipstz;
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}
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class Bootstrap::Aipstz : public Genode::Mmio<0x54>
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{
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private:
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/*
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* Configuration of the masters
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*/
|
||||
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struct Mpr { enum { ALL_UNBUFFERED_AND_FULLY_TRUSTED = 0x77777777 }; };
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struct Mpr1 : Register<0x0, 32>, Mpr { };
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struct Mpr2 : Register<0x4, 32>, Mpr { };
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/*
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* Configuration of the platform peripherals
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*/
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struct Pacr { enum { ALL_UNBUFFERED_AND_FULLY_UNPROTECTED = 0 }; };
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struct Pacr1 : Register<0x20, 32>, Pacr { };
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struct Pacr2 : Register<0x24, 32>, Pacr { };
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struct Pacr3 : Register<0x28, 32>, Pacr { };
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struct Pacr4 : Register<0x2c, 32>, Pacr { };
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/*
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* Configuration of the off-platform peripherals
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||||
*/
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||||
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||||
struct Opacr1 : Register<0x40, 32>, Pacr { };
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||||
struct Opacr2 : Register<0x44, 32>, Pacr { };
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struct Opacr3 : Register<0x48, 32>, Pacr { };
|
||||
struct Opacr4 : Register<0x4c, 32>, Pacr { };
|
||||
struct Opacr5 : Register<0x50, 32>, Pacr { };
|
||||
|
||||
public:
|
||||
|
||||
/**
|
||||
* Configure this module appropriately for the first kernel run
|
||||
*/
|
||||
Aipstz(Genode::addr_t const base) : Mmio({(char *)base, Mmio::SIZE})
|
||||
{
|
||||
/* avoid AIPS intervention at any memory access */
|
||||
write<Mpr1>(Mpr::ALL_UNBUFFERED_AND_FULLY_TRUSTED);
|
||||
write<Mpr2>(Mpr::ALL_UNBUFFERED_AND_FULLY_TRUSTED);
|
||||
write<Pacr1>(Pacr::ALL_UNBUFFERED_AND_FULLY_UNPROTECTED);
|
||||
write<Pacr2>(Pacr::ALL_UNBUFFERED_AND_FULLY_UNPROTECTED);
|
||||
write<Pacr3>(Pacr::ALL_UNBUFFERED_AND_FULLY_UNPROTECTED);
|
||||
write<Pacr4>(Pacr::ALL_UNBUFFERED_AND_FULLY_UNPROTECTED);
|
||||
write<Opacr1>(Pacr::ALL_UNBUFFERED_AND_FULLY_UNPROTECTED);
|
||||
write<Opacr2>(Pacr::ALL_UNBUFFERED_AND_FULLY_UNPROTECTED);
|
||||
write<Opacr3>(Pacr::ALL_UNBUFFERED_AND_FULLY_UNPROTECTED);
|
||||
write<Opacr4>(Pacr::ALL_UNBUFFERED_AND_FULLY_UNPROTECTED);
|
||||
write<Opacr5>(Pacr::ALL_UNBUFFERED_AND_FULLY_UNPROTECTED);
|
||||
}
|
||||
};
|
||||
|
||||
#endif /* _SRC__BOOTSTRAP__SPEC__ARM__IMX_AIPSTZ_H_ */
|
||||
@ -1,235 +0,0 @@
|
||||
/*
|
||||
* \brief Driver for the Central Security Unit
|
||||
* \author Stefan Kalkowski
|
||||
* \date 2012-11-06
|
||||
*/
|
||||
|
||||
/*
|
||||
* Copyright (C) 2012-2017 Genode Labs GmbH
|
||||
*
|
||||
* This file is part of the Genode OS framework, which is distributed
|
||||
* under the terms of the GNU Affero General Public License version 3.
|
||||
*/
|
||||
|
||||
#ifndef _SRC__BOOTSTRAP__SPEC__ARM__IMX_CSU_H_
|
||||
#define _SRC__BOOTSTRAP__SPEC__ARM__IMX_CSU_H_
|
||||
|
||||
#include <util/mmio.h>
|
||||
#include <util/register.h>
|
||||
|
||||
namespace Bootstrap { struct Csu; }
|
||||
|
||||
|
||||
struct Bootstrap::Csu : Genode::Mmio<0x36c>
|
||||
{
|
||||
template <Genode::off_t OFF>
|
||||
struct Csl : public Register<OFF, 32>
|
||||
{
|
||||
enum {
|
||||
SECURE = 0x33,
|
||||
UNSECURE = 0xff,
|
||||
};
|
||||
|
||||
struct Slave_a : Register<OFF, 32>::template Bitfield<0, 9> { };
|
||||
struct Slave_b : Register<OFF, 32>::template Bitfield<16, 9> { };
|
||||
};
|
||||
|
||||
|
||||
struct Master : public Register<0x218, 32>
|
||||
{
|
||||
enum {
|
||||
SECURE_UNLOCKED,
|
||||
UNSECURE_UNLOCKED,
|
||||
SECURE_LOCKED,
|
||||
UNSECURE_LOCKED
|
||||
};
|
||||
|
||||
struct Esdhc3 : Bitfield<0,2> { };
|
||||
struct Cortex : Bitfield<2,2> { };
|
||||
struct Sdma : Bitfield<4,2> { };
|
||||
struct Gpu : Bitfield<6,2> { };
|
||||
struct Usb : Bitfield<8,2> { };
|
||||
struct Pata : Bitfield<10,2> { };
|
||||
struct Mlb : Bitfield<14,2> { };
|
||||
struct Rtic : Bitfield<18,2> { };
|
||||
struct Esdhc4 : Bitfield<20,2> { };
|
||||
struct Fec : Bitfield<22,2> { };
|
||||
struct Dap : Bitfield<24,2> { };
|
||||
struct Esdhc1 : Bitfield<26,2> { };
|
||||
struct Esdhc2 : Bitfield<28,2> { };
|
||||
};
|
||||
|
||||
struct Alarm_mask : public Register<0x230, 32> { };
|
||||
struct Irq_ctrl : public Register<0x368, 32> { };
|
||||
|
||||
typedef Csl<0x00> Csl00;
|
||||
typedef Csl<0x04> Csl01;
|
||||
typedef Csl<0x08> Csl02;
|
||||
typedef Csl<0x0c> Csl03;
|
||||
typedef Csl<0x10> Csl04;
|
||||
typedef Csl<0x14> Csl05;
|
||||
typedef Csl<0x18> Csl06;
|
||||
typedef Csl<0x1c> Csl07;
|
||||
typedef Csl<0x20> Csl08;
|
||||
typedef Csl<0x24> Csl09;
|
||||
typedef Csl<0x28> Csl10;
|
||||
typedef Csl<0x2c> Csl11;
|
||||
typedef Csl<0x30> Csl12;
|
||||
typedef Csl<0x34> Csl13;
|
||||
typedef Csl<0x38> Csl14;
|
||||
typedef Csl<0x3c> Csl15;
|
||||
typedef Csl<0x40> Csl16;
|
||||
typedef Csl<0x44> Csl17;
|
||||
typedef Csl<0x48> Csl18;
|
||||
typedef Csl<0x4c> Csl19;
|
||||
typedef Csl<0x50> Csl20;
|
||||
typedef Csl<0x54> Csl21;
|
||||
typedef Csl<0x58> Csl22;
|
||||
typedef Csl<0x5c> Csl23;
|
||||
typedef Csl<0x60> Csl24;
|
||||
typedef Csl<0x64> Csl25;
|
||||
typedef Csl<0x68> Csl26;
|
||||
typedef Csl<0x6c> Csl27;
|
||||
typedef Csl<0x70> Csl28;
|
||||
typedef Csl<0x74> Csl29;
|
||||
typedef Csl<0x78> Csl30;
|
||||
typedef Csl<0x7c> Csl31;
|
||||
|
||||
Csu(Genode::addr_t base,
|
||||
bool secure_uart,
|
||||
bool secure_gpio,
|
||||
bool secure_esdhc,
|
||||
bool secure_i2c) : Mmio({(char *)base, Mmio::SIZE})
|
||||
{
|
||||
/* Power (CCM, SRC, DPLLIP1-4, GPC and OWIRE) */
|
||||
write<Csl09::Slave_a>(Csl00::UNSECURE);
|
||||
|
||||
/* AHBMAX S0-S2 */
|
||||
write<Csl09::Slave_b>(Csl00::UNSECURE);
|
||||
write<Csl20::Slave_a>(Csl00::UNSECURE);
|
||||
write<Csl06::Slave_b>(Csl00::UNSECURE);
|
||||
|
||||
/* AHBMAX M6 */
|
||||
write<Csl10::Slave_a>(Csl00::UNSECURE);
|
||||
|
||||
/* Timer (EPIT, GPT) TODO */
|
||||
write<Csl04::Slave_a>(Csl00::UNSECURE);
|
||||
|
||||
/* UART 1-5 */
|
||||
Csl00::access_t uart_csl =
|
||||
secure_uart ? Csl00::SECURE : Csl00::UNSECURE;
|
||||
write<Csl07::Slave_b>(uart_csl);
|
||||
write<Csl08::Slave_a>(uart_csl);
|
||||
write<Csl26::Slave_a>(uart_csl);
|
||||
write<Csl30::Slave_b>(uart_csl);
|
||||
write<Csl19::Slave_a>(uart_csl);
|
||||
|
||||
/* GPIO */
|
||||
Csl00::access_t gpio_csl =
|
||||
secure_gpio ? Csl00::SECURE : Csl00::UNSECURE;
|
||||
write<Csl00::Slave_b>(gpio_csl);
|
||||
write<Csl01::Slave_a>(gpio_csl);
|
||||
write<Csl01::Slave_b>(gpio_csl);
|
||||
write<Csl02::Slave_a>(gpio_csl);
|
||||
|
||||
/* IOMUXC TODO */
|
||||
write<Csl05::Slave_a>(Csl00::UNSECURE);
|
||||
|
||||
/* SDMA TODO */
|
||||
write<Csl15::Slave_a>(Csl00::UNSECURE);
|
||||
|
||||
/* USB */
|
||||
write<Csl00::Slave_a>(Csl00::UNSECURE);
|
||||
|
||||
/* TVE */
|
||||
write<Csl22::Slave_b>(Csl00::SECURE);
|
||||
|
||||
/* I2C */
|
||||
Csl00::access_t i2c_csl =
|
||||
secure_i2c ? Csl00::SECURE : Csl00::UNSECURE;
|
||||
write<Csl18::Slave_a>(i2c_csl);
|
||||
write<Csl17::Slave_b>(i2c_csl);
|
||||
write<Csl31::Slave_a>(i2c_csl);
|
||||
|
||||
/* IPU */
|
||||
write<Csl24::Slave_a>(Csl00::SECURE);
|
||||
|
||||
/* Audio */
|
||||
write<Csl18::Slave_b>(Csl00::UNSECURE);
|
||||
|
||||
/* SATA */
|
||||
write<Csl07::Slave_a>(Csl00::UNSECURE);
|
||||
|
||||
/* FEC */
|
||||
write<Csl22::Slave_a>(Csl00::UNSECURE);
|
||||
|
||||
/* SDHCI 1-4 */
|
||||
Csl00::access_t esdhc_csl =
|
||||
secure_esdhc ? Csl00::SECURE : Csl00::UNSECURE;
|
||||
write<Csl25::Slave_a>(esdhc_csl);
|
||||
write<Csl25::Slave_b>(esdhc_csl);
|
||||
write<Csl28::Slave_a>(esdhc_csl);
|
||||
write<Csl28::Slave_b>(esdhc_csl);
|
||||
|
||||
/* SPDIF */
|
||||
write<Csl29::Slave_a>(Csl00::UNSECURE);
|
||||
|
||||
/* GPU 2D */
|
||||
write<Csl24::Slave_b>(Csl00::SECURE);
|
||||
|
||||
/* GPU 3D */
|
||||
write<Csl27::Slave_b>(Csl00::SECURE);
|
||||
|
||||
write<Csl02::Slave_b>(Csl00::UNSECURE);
|
||||
write<Csl03::Slave_a>(Csl00::UNSECURE);
|
||||
write<Csl03::Slave_b>(Csl00::UNSECURE);
|
||||
write<Csl04::Slave_b>(Csl00::UNSECURE); // SRTC
|
||||
write<Csl05::Slave_b>(Csl00::UNSECURE);
|
||||
write<Csl06::Slave_a>(Csl00::UNSECURE);
|
||||
write<Csl08::Slave_b>(Csl00::UNSECURE);
|
||||
write<Csl10::Slave_b>(Csl00::UNSECURE);
|
||||
write<Csl11::Slave_a>(Csl00::UNSECURE);
|
||||
write<Csl11::Slave_b>(Csl00::UNSECURE);
|
||||
write<Csl12::Slave_a>(Csl00::UNSECURE);
|
||||
write<Csl12::Slave_b>(Csl00::UNSECURE);
|
||||
write<Csl13::Slave_a>(Csl00::UNSECURE);
|
||||
write<Csl13::Slave_b>(Csl00::UNSECURE);
|
||||
write<Csl14::Slave_a>(Csl00::UNSECURE);
|
||||
write<Csl14::Slave_b>(Csl00::UNSECURE);
|
||||
write<Csl15::Slave_b>(Csl00::UNSECURE); // SCC
|
||||
write<Csl16::Slave_a>(Csl00::UNSECURE);
|
||||
write<Csl16::Slave_b>(Csl00::UNSECURE); // RTIC
|
||||
write<Csl17::Slave_a>(Csl00::UNSECURE);
|
||||
write<Csl19::Slave_b>(Csl00::UNSECURE);
|
||||
write<Csl20::Slave_b>(Csl00::UNSECURE);
|
||||
write<Csl21::Slave_a>(Csl00::UNSECURE);
|
||||
write<Csl21::Slave_b>(Csl00::UNSECURE);
|
||||
write<Csl23::Slave_a>(Csl00::SECURE); //VPU
|
||||
write<Csl23::Slave_b>(Csl00::UNSECURE);
|
||||
write<Csl26::Slave_b>(Csl00::UNSECURE);
|
||||
write<Csl27::Slave_a>(Csl00::UNSECURE);
|
||||
write<Csl29::Slave_b>(Csl00::UNSECURE);
|
||||
write<Csl30::Slave_a>(Csl00::UNSECURE);
|
||||
write<Csl31::Slave_b>(Csl00::UNSECURE);
|
||||
|
||||
/* DMA from graphical subsystem is considered to be secure */
|
||||
write<Master::Gpu>(Master::SECURE_UNLOCKED);
|
||||
|
||||
/* all other DMA operations are insecure */
|
||||
write<Master::Sdma>(Master::UNSECURE_UNLOCKED);
|
||||
write<Master::Usb>(Master::UNSECURE_UNLOCKED);
|
||||
write<Master::Pata>(Master::UNSECURE_UNLOCKED);
|
||||
write<Master::Fec>(Master::UNSECURE_UNLOCKED);
|
||||
write<Master::Dap>(Master::UNSECURE_UNLOCKED);
|
||||
|
||||
Master::access_t esdhc_master =
|
||||
secure_esdhc ? Master::SECURE_UNLOCKED
|
||||
: Master::UNSECURE_UNLOCKED;
|
||||
write<Master::Esdhc1>(esdhc_master);
|
||||
write<Master::Esdhc2>(esdhc_master);
|
||||
write<Master::Esdhc3>(esdhc_master);
|
||||
write<Master::Esdhc4>(esdhc_master);
|
||||
}
|
||||
};
|
||||
|
||||
#endif /* _SRC__BOOTSTRAP__SPEC__ARM__IMX_CSU_H_ */
|
||||
@ -1,31 +0,0 @@
|
||||
/*
|
||||
* \brief Freescale's TrustZone aware interrupt controller
|
||||
* \author Stefan Kalkowski
|
||||
* \date 2012-10-24
|
||||
*/
|
||||
|
||||
/*
|
||||
* Copyright (C) 2012-2013 Genode Labs GmbH
|
||||
*
|
||||
* This file is part of the Genode OS framework, which is distributed
|
||||
* under the terms of the GNU Affero General Public License version 3.
|
||||
*/
|
||||
|
||||
#include <board.h>
|
||||
|
||||
Hw::Pic::Pic()
|
||||
:
|
||||
Mmio({(char *)Board::IRQ_CONTROLLER_BASE, Board::IRQ_CONTROLLER_SIZE})
|
||||
{
|
||||
for (unsigned i = 0; i < NR_OF_IRQ; i++) {
|
||||
write<Intsec::Nonsecure>(!Board::secure_irq(i), i);
|
||||
if (!Board::secure_irq(i)) write<Priority>(0x80, i);
|
||||
write<Enclear::Clear_enable>(1, i);
|
||||
}
|
||||
write<Priomask::Mask>(0xff);
|
||||
Intctrl::access_t v = 0;
|
||||
Intctrl::Enable::set(v, 1);
|
||||
Intctrl::Nsen::set(v, 1);
|
||||
Intctrl::Nsen_mask::set(v, 1);
|
||||
write<Intctrl>(v);
|
||||
}
|
||||
@ -1,29 +0,0 @@
|
||||
/*
|
||||
* \brief Board driver
|
||||
* \author Stefan Kalkowski
|
||||
* \author Martin Stein
|
||||
* \date 2012-10-24
|
||||
*/
|
||||
|
||||
/*
|
||||
* Copyright (C) 2012-2017 Genode Labs GmbH
|
||||
*
|
||||
* This file is part of the Genode OS framework, which is distributed
|
||||
* under the terms of the GNU Affero General Public License version 3.
|
||||
*/
|
||||
|
||||
#ifndef _CORE__SPEC__IMX53_QSB__BOARD_H_
|
||||
#define _CORE__SPEC__IMX53_QSB__BOARD_H_
|
||||
|
||||
/* base-hw internal includes */
|
||||
#include <hw/spec/arm/imx_tzic.h>
|
||||
#include <hw/spec/arm/imx53_qsb_board.h>
|
||||
|
||||
/* base-hw core includes */
|
||||
#include <spec/arm/imx_epit.h>
|
||||
#include <spec/arm/trustzone_board.h>
|
||||
#include <spec/cortex_a8/cpu.h>
|
||||
|
||||
namespace Board { using namespace Hw::Imx53_qsb_board; }
|
||||
|
||||
#endif /* _CORE__SPEC__IMX53_QSB__BOARD_H_ */
|
||||
@ -1,29 +0,0 @@
|
||||
/*
|
||||
* \brief Board driver
|
||||
* \author Stefan Kalkowski
|
||||
* \author Martin Stein
|
||||
* \date 2012-10-24
|
||||
*/
|
||||
|
||||
/*
|
||||
* Copyright (C) 2012-2017 Genode Labs GmbH
|
||||
*
|
||||
* This file is part of the Genode OS framework, which is distributed
|
||||
* under the terms of the GNU Affero General Public License version 3.
|
||||
*/
|
||||
|
||||
#ifndef _CORE__SPEC__USB_ARMORY__BOARD_H_
|
||||
#define _CORE__SPEC__USB_ARMORY__BOARD_H_
|
||||
|
||||
/* base-hw internal includes */
|
||||
#include <hw/spec/arm/imx_tzic.h>
|
||||
#include <hw/spec/arm/usb_armory_board.h>
|
||||
|
||||
/* base-hw core includes */
|
||||
#include <spec/arm/imx_epit.h>
|
||||
#include <spec/arm/trustzone_board.h>
|
||||
#include <spec/cortex_a8/cpu.h>
|
||||
|
||||
namespace Board { using namespace Hw::Usb_armory_board; }
|
||||
|
||||
#endif /* _CORE__SPEC__USB_ARMORY__BOARD_H_ */
|
||||
@ -1,106 +0,0 @@
|
||||
/*
|
||||
* \brief Timer driver for core
|
||||
* \author Stefan Kalkowski
|
||||
* \author Martin Stein
|
||||
* \date 2012-04-23
|
||||
*/
|
||||
|
||||
/*
|
||||
* Copyright (C) 2012-2017 Genode Labs GmbH
|
||||
*
|
||||
* This file is part of the Genode OS framework, which is distributed
|
||||
* under the terms of the GNU Affero General Public License version 3.
|
||||
*/
|
||||
|
||||
/* core includes */
|
||||
#include <kernel/timer.h>
|
||||
#include <board.h>
|
||||
#include <platform.h>
|
||||
|
||||
#include <drivers/timer/util.h>
|
||||
|
||||
using namespace Core;
|
||||
using namespace Kernel;
|
||||
|
||||
|
||||
unsigned Timer::interrupt_id() const { return Board::EPIT_1_IRQ; }
|
||||
|
||||
|
||||
Board::Timer::Timer(unsigned)
|
||||
:
|
||||
Mmio({(char *)Platform::mmio_to_virt(Board::EPIT_1_MMIO_BASE), Mmio::SIZE})
|
||||
{
|
||||
init();
|
||||
}
|
||||
|
||||
|
||||
void Board::Timer::init()
|
||||
{
|
||||
/*
|
||||
* Used timer mode:
|
||||
*
|
||||
* - Set CNT to 0xffffffff whenever CR.EN goes from 0 to 1 (CR.EN_MOD = 1).
|
||||
* This happens only once: at construction time.
|
||||
* - CNT is counting downwards with timer frequency.
|
||||
* - When CNT reaches 0 it rolls over to 0xffffffff (CR.RLD = 0).
|
||||
* - When writing LR, also set CNT to new LR value (CR.IOVW = 1). This
|
||||
* happens whenever a timeout is programmed.
|
||||
* - Trigger IRQ when CNT == CMPR (CR.OCI_EN = 1). CMPR is always set to
|
||||
* 0xffffffff.
|
||||
*/
|
||||
|
||||
reset();
|
||||
|
||||
Cr::access_t cr = read<Cr>();
|
||||
Cr::En_mod::set(cr, Cr::En_mod::RELOAD);
|
||||
Cr::Oci_en::set(cr, 1);
|
||||
Cr::Rld::set(cr, 0);
|
||||
Cr::Prescaler::set(cr, Cr::Prescaler::DIVIDE_BY_1);
|
||||
Cr::Clk_src::set(cr, Cr::Clk_src::HIGH_FREQ_REF_CLK);
|
||||
Cr::Iovw::set(cr, 1);
|
||||
write<Cr>(cr);
|
||||
|
||||
write<Cmpr>(0xffffffff);
|
||||
write<Cr::En>(1);
|
||||
|
||||
write<Lr>(0xffffffff);
|
||||
}
|
||||
|
||||
|
||||
void Timer::_start_one_shot(time_t const ticks)
|
||||
{
|
||||
/*
|
||||
* First unset the interrupt flag,
|
||||
* otherwise if the tick is small enough, we loose an interrupt
|
||||
*/
|
||||
_device.write<Board::Timer::Sr::Ocif>(1);
|
||||
|
||||
/* maximal ticks are guaranteed via _max_value */
|
||||
_device.write<Board::Timer::Lr>((uint32_t)(ticks - 1));
|
||||
}
|
||||
|
||||
|
||||
time_t Timer::ticks_to_us(time_t const ticks) const {
|
||||
return timer_ticks_to_us(ticks, Board::Timer::TICS_PER_MS); }
|
||||
|
||||
|
||||
time_t Timer::us_to_ticks(time_t const us) const {
|
||||
return (us * Board::Timer::TICS_PER_MS) / 1000; }
|
||||
|
||||
|
||||
time_t Timer::_max_value() const {
|
||||
return 0xffffffff; }
|
||||
|
||||
|
||||
time_t Timer::_duration() const
|
||||
{
|
||||
using Device = Board::Timer;
|
||||
Device::Cnt::access_t const initial_cnt {
|
||||
(Device::Cnt::access_t)_last_timeout_duration };
|
||||
|
||||
Device::Cnt::access_t const curr_cnt { _device.read<Device::Cnt>() };
|
||||
if (curr_cnt > initial_cnt)
|
||||
return _max_value() - _device.read<Device::Cnt>() + initial_cnt;
|
||||
else
|
||||
return initial_cnt - curr_cnt;
|
||||
}
|
||||
@ -1,91 +0,0 @@
|
||||
/*
|
||||
* \brief Timer driver for core
|
||||
* \author Martin Stein
|
||||
* \date 2012-04-23
|
||||
*/
|
||||
|
||||
/*
|
||||
* Copyright (C) 2012-2017 Kernel Labs GmbH
|
||||
*
|
||||
* This file is part of the Kernel OS framework, which is distributed
|
||||
* under the terms of the GNU Affero General Public License version 3.
|
||||
*/
|
||||
|
||||
#ifndef _SRC__CORE__SPEC__ARM__IMX_EPIT_H_
|
||||
#define _SRC__CORE__SPEC__ARM__IMX_EPIT_H_
|
||||
|
||||
/* Kernel includes */
|
||||
#include <util/mmio.h>
|
||||
|
||||
namespace Board { class Timer; }
|
||||
|
||||
|
||||
/**
|
||||
* Timer driver for core
|
||||
*/
|
||||
struct Board::Timer : Genode::Mmio<0x14>
|
||||
{
|
||||
enum { TICS_PER_MS = 33333 };
|
||||
|
||||
/**
|
||||
* Control register
|
||||
*/
|
||||
struct Cr : Register<0x0, 32>
|
||||
{
|
||||
struct En : Bitfield<0, 1> { }; /* enable timer */
|
||||
|
||||
struct En_mod : Bitfield<1, 1> /* reload on enable */
|
||||
{
|
||||
enum { RELOAD = 1 };
|
||||
};
|
||||
|
||||
struct Oci_en : Bitfield<2, 1> { }; /* interrupt on compare */
|
||||
struct Rld : Bitfield<3, 1> { }; /* counter reload mode */
|
||||
|
||||
struct Prescaler : Bitfield<4, 12> /* clock input divisor */
|
||||
{
|
||||
enum { DIVIDE_BY_1 = 0 };
|
||||
};
|
||||
|
||||
struct Swr : Bitfield<16, 1> { }; /* software reset bit */
|
||||
struct Iovw : Bitfield<17, 1> { }; /* enable overwrite */
|
||||
|
||||
struct Clk_src : Bitfield<24, 2> /* select clock input */
|
||||
{
|
||||
enum { HIGH_FREQ_REF_CLK = 2 };
|
||||
};
|
||||
};
|
||||
|
||||
/**
|
||||
* Status register
|
||||
*/
|
||||
struct Sr : Register<0x4, 32>
|
||||
{
|
||||
struct Ocif : Bitfield<0, 1> { }; /* IRQ status, write 1 clears */
|
||||
};
|
||||
|
||||
struct Lr : Register<0x8, 32> { }; /* load value register */
|
||||
struct Cmpr : Register<0xc, 32> { }; /* compare value register */
|
||||
struct Cnt : Register<0x10, 32> { }; /* counter register */
|
||||
|
||||
/**
|
||||
* Disable timer and clear its interrupt output
|
||||
*/
|
||||
void reset()
|
||||
{
|
||||
/* wait until ongoing reset operations are finished */
|
||||
while (read<Cr::Swr>()) ;
|
||||
|
||||
/* disable timer */
|
||||
write<Cr::En>(0);
|
||||
|
||||
/* clear interrupt */
|
||||
write<Sr::Ocif>(1);
|
||||
}
|
||||
|
||||
Timer(unsigned);
|
||||
|
||||
void init();
|
||||
};
|
||||
|
||||
#endif /* _SRC__CORE__SPEC__ARM__IMX_EPIT_H_ */
|
||||
@ -1,21 +0,0 @@
|
||||
/*
|
||||
* \brief Freescale TrustZone aware interrupt controller for core
|
||||
* \author Stefan Kalkowski
|
||||
* \date 2012-10-24
|
||||
*/
|
||||
|
||||
/*
|
||||
* Copyright (C) 2012-2017 Genode Labs GmbH
|
||||
*
|
||||
* This file is part of the Genode OS framework, which is distributed
|
||||
* under the terms of the GNU Affero General Public License version 3.
|
||||
*/
|
||||
|
||||
/* core includes */
|
||||
#include <board.h>
|
||||
#include <platform.h>
|
||||
|
||||
using namespace Core;
|
||||
|
||||
|
||||
Hw::Pic::Pic() : Mmio({(char *)Platform::mmio_to_virt(Board::IRQ_CONTROLLER_BASE), Mmio::SIZE}) { }
|
||||
@ -13,7 +13,6 @@
|
||||
|
||||
/* Genode includes */
|
||||
#include <base/service.h>
|
||||
#include <drivers/defs/imx53_trustzone.h>
|
||||
|
||||
/* core includes */
|
||||
#include <platform.h>
|
||||
|
||||
@ -1,34 +0,0 @@
|
||||
/*
|
||||
* \brief i.MX53 Quickstart board definitions
|
||||
* \author Stefan Kalkowski
|
||||
* \date 2019-05-15
|
||||
*/
|
||||
|
||||
/*
|
||||
* Copyright (C) 2019 Genode Labs GmbH
|
||||
*
|
||||
* This file is part of the Genode OS framework, which is distributed
|
||||
* under the terms of the GNU Affero General Public License version 3.
|
||||
*/
|
||||
|
||||
#ifndef _SRC__INCLUDE__HW__SPEC__IMX53_QSB_BOARD_H_
|
||||
#define _SRC__INCLUDE__HW__SPEC__IMX53_QSB_BOARD_H_
|
||||
|
||||
#include <drivers/defs/imx53_qsb.h>
|
||||
#include <drivers/uart/imx.h>
|
||||
#include <hw/spec/arm/boot_info.h>
|
||||
|
||||
namespace Hw::Imx53_qsb_board {
|
||||
|
||||
using namespace Imx53_qsb;
|
||||
using Serial = Genode::Imx_uart;
|
||||
|
||||
enum {
|
||||
UART_BASE = UART_1_MMIO_BASE,
|
||||
UART_CLOCK = 0, /* ignored value */
|
||||
};
|
||||
|
||||
static constexpr Genode::size_t NR_OF_CPUS = 1;
|
||||
}
|
||||
|
||||
#endif /* _SRC__INCLUDE__HW__SPEC__IMX53_QSB_BOARD_H_ */
|
||||
@ -1,133 +0,0 @@
|
||||
/*
|
||||
* \brief Freescale's TrustZone aware interrupt controller
|
||||
* \author Stefan Kalkowski
|
||||
* \date 2012-10-24
|
||||
*/
|
||||
|
||||
/*
|
||||
* Copyright (C) 2012-2017 Genode Labs GmbH
|
||||
*
|
||||
* This file is part of the Genode OS framework, which is distributed
|
||||
* under the terms of the GNU Affero General Public License version 3.
|
||||
*/
|
||||
|
||||
#ifndef _SRC__LIB__HW__SPEC__ARM__IMX_TZIC_H_
|
||||
#define _SRC__LIB__HW__SPEC__ARM__IMX_TZIC_H_
|
||||
|
||||
#include <util/mmio.h>
|
||||
|
||||
namespace Hw { class Pic; }
|
||||
|
||||
|
||||
class Hw::Pic : public Genode::Mmio<0xf04>
|
||||
{
|
||||
public:
|
||||
|
||||
enum { NR_OF_IRQ = 109, };
|
||||
|
||||
protected:
|
||||
|
||||
/**
|
||||
* Software Interrupt Trigger Register
|
||||
*/
|
||||
struct Swint : Register<0xf00, 32> {
|
||||
struct Intid : Bitfield<0,10> { }; };
|
||||
|
||||
/**
|
||||
* Interrupt control register
|
||||
*/
|
||||
struct Intctrl : Register<0, 32>
|
||||
{
|
||||
struct Enable : Bitfield<0,1> { };
|
||||
struct Nsen : Bitfield<16,1> { };
|
||||
struct Nsen_mask : Bitfield<31,1> { };
|
||||
};
|
||||
|
||||
/**
|
||||
* Priority mask register
|
||||
*/
|
||||
struct Priomask : Register<0xc, 32> {
|
||||
struct Mask : Bitfield<0,8> { }; };
|
||||
|
||||
/**
|
||||
* Interrupt security registers
|
||||
*/
|
||||
struct Intsec : Register_array<0x80, 32, NR_OF_IRQ, 1> {
|
||||
struct Nonsecure : Bitfield<0, 1> { }; };
|
||||
|
||||
/**
|
||||
* Interrupt set enable registers
|
||||
*/
|
||||
struct Enset : Register_array<0x100, 32, NR_OF_IRQ, 1, true> {
|
||||
struct Set_enable : Bitfield<0, 1> { }; };
|
||||
|
||||
/**
|
||||
* Interrupt clear enable registers
|
||||
*/
|
||||
struct Enclear : Register_array<0x180, 32, NR_OF_IRQ, 1, true> {
|
||||
struct Clear_enable : Bitfield<0, 1> { }; };
|
||||
|
||||
/**
|
||||
* Interrupt priority level registers
|
||||
*/
|
||||
struct Priority : Register_array<0x400, 32, NR_OF_IRQ, 8> { };
|
||||
|
||||
/**
|
||||
* Highest interrupt pending registers
|
||||
*/
|
||||
struct Hipndr : Register_array<0xd80, 32, NR_OF_IRQ, 1, true> {
|
||||
struct Pending : Bitfield<0, 1> { }; };
|
||||
|
||||
/**
|
||||
* Validate request number 'i'
|
||||
*/
|
||||
bool _valid(unsigned const i) const { return i < NR_OF_IRQ; }
|
||||
|
||||
public:
|
||||
|
||||
enum { IPI = 0xffff };
|
||||
|
||||
Pic();
|
||||
|
||||
/**
|
||||
* Receive a pending request number 'i'
|
||||
*/
|
||||
bool take_request(unsigned & i)
|
||||
{
|
||||
for (unsigned j = 0; j < NR_OF_IRQ; j++) {
|
||||
if (!read<Hipndr::Pending>(j)) { continue; }
|
||||
i = j;
|
||||
return true;
|
||||
}
|
||||
return false;
|
||||
}
|
||||
|
||||
void finish_request() { }
|
||||
|
||||
void irq_mode(unsigned, unsigned, unsigned) { }
|
||||
|
||||
/**
|
||||
* Unmask interrupt 'i'
|
||||
*/
|
||||
void unmask(unsigned const i, unsigned) {
|
||||
if (_valid(i)) { write<Enset::Set_enable>(1, i); } }
|
||||
|
||||
/**
|
||||
* Mask interrupt 'i'
|
||||
*/
|
||||
void mask(unsigned const i) {
|
||||
if (_valid(i)) { write<Enclear::Clear_enable>(1, i); } }
|
||||
|
||||
/*
|
||||
* Trigger interrupt 'i' from software if possible
|
||||
*/
|
||||
void trigger(unsigned const i) {
|
||||
write<Swint>(Swint::Intid::bits(i)); }
|
||||
|
||||
bool secure(unsigned i) {
|
||||
return !read<Intsec::Nonsecure>(i); }
|
||||
|
||||
static constexpr bool fast_interrupts() { return true; }
|
||||
};
|
||||
|
||||
#endif /* _SRC__LIB__HW__SPEC__ARM__IMX_TZIC_H_ */
|
||||
@ -1,35 +0,0 @@
|
||||
/*
|
||||
* \brief USB armory board definitions
|
||||
* \author Stefan Kalkowski
|
||||
* \date 2019-05-15
|
||||
*/
|
||||
|
||||
/*
|
||||
* Copyright (C) 2019 Genode Labs GmbH
|
||||
*
|
||||
* This file is part of the Genode OS framework, which is distributed
|
||||
* under the terms of the GNU Affero General Public License version 3.
|
||||
*/
|
||||
|
||||
#ifndef _SRC__INCLUDE__HW__SPEC__ARM__USB_ARMORY_BOARD_H_
|
||||
#define _SRC__INCLUDE__HW__SPEC__ARM__USB_ARMORY_BOARD_H_
|
||||
|
||||
#include <drivers/defs/usb_armory.h>
|
||||
#include <drivers/uart/imx.h>
|
||||
#include <hw/spec/arm/boot_info.h>
|
||||
|
||||
namespace Hw::Usb_armory_board {
|
||||
|
||||
using namespace Usb_armory;
|
||||
|
||||
using Serial = Genode::Imx_uart;
|
||||
|
||||
enum {
|
||||
UART_BASE = UART_1_MMIO_BASE,
|
||||
UART_CLOCK = 0, /* ignored value */
|
||||
};
|
||||
|
||||
static constexpr Genode::size_t NR_OF_CPUS = 1;
|
||||
}
|
||||
|
||||
#endif /* _SRC__INCLUDE__HW__SPEC__ARM__USB_ARMORY_BOARD_H_ */
|
||||
@ -1,112 +0,0 @@
|
||||
/*
|
||||
* \brief MMIO and IRQ definitions common to i.MX53 SoC
|
||||
* \author Stefan Kalkowski
|
||||
* \date 2012-10-24
|
||||
*/
|
||||
|
||||
/*
|
||||
* Copyright (C) 2012-2017 Genode Labs GmbH
|
||||
*
|
||||
* This file is part of the Genode OS framework, which is distributed
|
||||
* under the terms of the GNU Affero General Public License version 3.
|
||||
*/
|
||||
|
||||
#ifndef _INCLUDE__DRIVERS__DEFS__IMX53_H_
|
||||
#define _INCLUDE__DRIVERS__DEFS__IMX53_H_
|
||||
|
||||
namespace Imx53 {
|
||||
enum {
|
||||
MMIO_BASE = 0x0,
|
||||
MMIO_SIZE = 0x70000000,
|
||||
|
||||
RAM_BANK_0_BASE = 0x70000000,
|
||||
RAM_BANK_0_SIZE = 0x40000000,
|
||||
RAM_BANK_1_BASE = 0xb0000000,
|
||||
RAM_BANK_1_SIZE = 0x40000000,
|
||||
|
||||
SDHC_IRQ = 1,
|
||||
SDHC_MMIO_BASE = 0x50004000,
|
||||
SDHC_MMIO_SIZE = 0x00004000,
|
||||
|
||||
UART_1_IRQ = 31,
|
||||
UART_1_MMIO_BASE = 0x53fbc000,
|
||||
UART_1_MMIO_SIZE = 0x00004000,
|
||||
|
||||
EPIT_1_IRQ = 40,
|
||||
EPIT_1_MMIO_BASE = 0x53fac000,
|
||||
EPIT_1_MMIO_SIZE = 0x00004000,
|
||||
|
||||
EPIT_2_IRQ = 41,
|
||||
EPIT_2_MMIO_BASE = 0x53fb0000,
|
||||
EPIT_2_MMIO_SIZE = 0x00004000,
|
||||
|
||||
GPIO1_MMIO_BASE = 0x53f84000,
|
||||
GPIO1_MMIO_SIZE = 0x4000,
|
||||
GPIO2_MMIO_BASE = 0x53f88000,
|
||||
GPIO2_MMIO_SIZE = 0x4000,
|
||||
GPIO3_MMIO_BASE = 0x53f8c000,
|
||||
GPIO3_MMIO_SIZE = 0x4000,
|
||||
GPIO4_MMIO_BASE = 0x53f90000,
|
||||
GPIO4_MMIO_SIZE = 0x4000,
|
||||
GPIO5_MMIO_BASE = 0x53fdc000,
|
||||
GPIO5_MMIO_SIZE = 0x4000,
|
||||
GPIO6_MMIO_BASE = 0x53fe0000,
|
||||
GPIO6_MMIO_SIZE = 0x4000,
|
||||
GPIO7_MMIO_BASE = 0x53fe4000,
|
||||
GPIO7_MMIO_SIZE = 0x4000,
|
||||
GPIO1_IRQL = 50,
|
||||
GPIO1_IRQH = 51,
|
||||
GPIO2_IRQL = 52,
|
||||
GPIO2_IRQH = 53,
|
||||
GPIO3_IRQL = 54,
|
||||
GPIO3_IRQH = 55,
|
||||
GPIO4_IRQL = 56,
|
||||
GPIO4_IRQH = 57,
|
||||
GPIO5_IRQL = 103,
|
||||
GPIO5_IRQH = 104,
|
||||
GPIO6_IRQL = 105,
|
||||
GPIO6_IRQH = 106,
|
||||
GPIO7_IRQL = 107,
|
||||
GPIO7_IRQH = 108,
|
||||
|
||||
IRQ_CONTROLLER_BASE = 0x0fffc000,
|
||||
IRQ_CONTROLLER_SIZE = 0x00004000,
|
||||
|
||||
AIPS_1_MMIO_BASE = 0x53f00000,
|
||||
AIPS_2_MMIO_BASE = 0x63f00000,
|
||||
|
||||
IOMUXC_BASE = 0x53fa8000,
|
||||
IOMUXC_SIZE = 0x00004000,
|
||||
|
||||
PWM2_BASE = 0x53fb8000,
|
||||
PWM2_SIZE = 0x00004000,
|
||||
|
||||
IPU_BASE = 0x18000000,
|
||||
IPU_SIZE = 0x08000000,
|
||||
|
||||
SRC_BASE = 0x53fd0000,
|
||||
SRC_SIZE = 0x00004000,
|
||||
|
||||
CCM_BASE = 0x53FD4000,
|
||||
CCM_SIZE = 0x00004000,
|
||||
|
||||
I2C_2_IRQ = 63,
|
||||
I2C_2_BASE = 0x63fc4000,
|
||||
I2C_2_SIZE = 0x00004000,
|
||||
|
||||
I2C_3_IRQ = 64,
|
||||
I2C_3_BASE = 0x53fec000,
|
||||
I2C_3_SIZE = 0x00004000,
|
||||
|
||||
IIM_BASE = 0x63f98000,
|
||||
IIM_SIZE = 0x00004000,
|
||||
|
||||
CSU_BASE = 0x63f9c000,
|
||||
CSU_SIZE = 0x00001000,
|
||||
|
||||
M4IF_BASE = 0x63fd8000,
|
||||
M4IF_SIZE = 0x00001000,
|
||||
};
|
||||
};
|
||||
|
||||
#endif /* _INCLUDE__DRIVERS__DEFS__IMX53_H_ */
|
||||
@ -1,32 +0,0 @@
|
||||
/*
|
||||
* \brief MMIO and IRQ definitions of the i.MX53 Quickstart board
|
||||
* \author Stefan Kalkowski
|
||||
* \date 2012-10-24
|
||||
*/
|
||||
|
||||
/*
|
||||
* Copyright (C) 2012-2017 Genode Labs GmbH
|
||||
*
|
||||
* This file is part of the Genode OS framework, which is distributed
|
||||
* under the terms of the GNU Affero General Public License version 3.
|
||||
*/
|
||||
|
||||
#ifndef _INCLUDE__DRIVERS__DEFS__IMX53_QSB_H_
|
||||
#define _INCLUDE__DRIVERS__DEFS__IMX53_QSB_H_
|
||||
|
||||
/* Genode includes */
|
||||
#include <drivers/defs/imx53.h>
|
||||
|
||||
namespace Imx53_qsb {
|
||||
|
||||
using namespace Imx53;
|
||||
|
||||
enum {
|
||||
RAM0_BASE = RAM_BANK_0_BASE,
|
||||
RAM0_SIZE = 0x20000000,
|
||||
RAM1_BASE = RAM_BANK_1_BASE,
|
||||
RAM1_SIZE = 0x20000000,
|
||||
};
|
||||
};
|
||||
|
||||
#endif /* _INCLUDE__DRIVERS__DEFS__IMX53_QSB_H_ */
|
||||
@ -1,30 +0,0 @@
|
||||
/*
|
||||
* \brief MMIO and IRQ definitions for the USB Armory
|
||||
* \author Stefan Kalkowski
|
||||
* \date 2012-10-24
|
||||
*/
|
||||
|
||||
/*
|
||||
* Copyright (C) 2012-2017 Genode Labs GmbH
|
||||
*
|
||||
* This file is part of the Genode OS framework, which is distributed
|
||||
* under the terms of the GNU Affero General Public License version 3.
|
||||
*/
|
||||
|
||||
#ifndef _INCLUDE__DRIVERS__DEFS__USB_ARMORY_H_
|
||||
#define _INCLUDE__DRIVERS__DEFS__USB_ARMORY_H_
|
||||
|
||||
/* Genode includes */
|
||||
#include <drivers/defs/imx53.h>
|
||||
|
||||
namespace Usb_armory {
|
||||
|
||||
using namespace Imx53;
|
||||
|
||||
enum {
|
||||
RAM_BASE = RAM_BANK_0_BASE,
|
||||
RAM_SIZE = 0x20000000,
|
||||
};
|
||||
};
|
||||
|
||||
#endif /* _INCLUDE__DRIVERS__DEFS__USB_ARMORY_H_ */
|
||||
@ -1,272 +0,0 @@
|
||||
/*
|
||||
* \brief Driver for Freescale's i.MX UART
|
||||
* \author Norman Feske
|
||||
* \author Martin Stein
|
||||
* \date 2012-08-30
|
||||
*/
|
||||
|
||||
/*
|
||||
* Copyright (C) 2012-2017 Genode Labs GmbH
|
||||
*
|
||||
* This file is part of the Genode OS framework, which is distributed
|
||||
* under the terms of the GNU Affero General Public License version 3.
|
||||
*/
|
||||
|
||||
#ifndef _INCLUDE__DRIVERS__UART__IMX_H_
|
||||
#define _INCLUDE__DRIVERS__UART__IMX_H_
|
||||
|
||||
/* Genode includes */
|
||||
#include <util/mmio.h>
|
||||
|
||||
namespace Genode { class Imx_uart; }
|
||||
|
||||
|
||||
/**
|
||||
* Driver base for i.MX UART-module
|
||||
*/
|
||||
class Genode::Imx_uart: Mmio<0xa2>
|
||||
{
|
||||
/**
|
||||
* Control register 1
|
||||
*/
|
||||
struct Cr1 : Register<0x80, 32>
|
||||
{
|
||||
struct Uart_en : Bitfield<0, 1> { }; /* enable UART */
|
||||
struct Doze : Bitfield<1, 1> { }; /* disable on doze */
|
||||
struct At_dma_en : Bitfield<2, 1> { }; /* aging DMA
|
||||
* timer on */
|
||||
struct Tx_dma_en : Bitfield<3, 1> { }; /* TX ready DMA on */
|
||||
struct Snd_brk : Bitfield<4, 1> { }; /* send breaks */
|
||||
struct Rtsd_en : Bitfield<5, 1> { }; /* RTS delta IRQ on */
|
||||
struct Tx_mpty_en : Bitfield<6, 1> { }; /* TX empty IRQ on */
|
||||
struct Ir_en : Bitfield<7, 1> { }; /* enable infrared */
|
||||
struct Rx_dma_en : Bitfield<8, 1> { }; /* RX ready DMA on */
|
||||
struct R_rdy_en : Bitfield<9, 1> { }; /* RX ready IRQ on */
|
||||
|
||||
struct Icd : Bitfield<10, 2> /* idle IRQ condition */
|
||||
{
|
||||
enum { IDLE_4_FRAMES = 0 };
|
||||
};
|
||||
|
||||
struct Id_en : Bitfield<12, 1> { }; /* enable idle IRQ */
|
||||
struct T_rdy_en : Bitfield<13, 1> { }; /* TX ready IRQ on */
|
||||
struct Adbr : Bitfield<14, 1> { }; /* enable baud-rate
|
||||
* auto detect */
|
||||
struct Ad_en : Bitfield<15, 1> { }; /* enable ADBR IRQ */
|
||||
|
||||
/**
|
||||
* Initialization value
|
||||
*/
|
||||
static access_t init_value()
|
||||
{
|
||||
return Uart_en::bits(1) |
|
||||
Doze::bits(0) |
|
||||
At_dma_en::bits(0) |
|
||||
Tx_dma_en::bits(0) |
|
||||
Snd_brk::bits(0) |
|
||||
Rtsd_en::bits(0) |
|
||||
Tx_mpty_en::bits(0) |
|
||||
Ir_en::bits(0) |
|
||||
Rx_dma_en::bits(0) |
|
||||
R_rdy_en::bits(0) |
|
||||
Id_en::bits(0) |
|
||||
T_rdy_en::bits(0) |
|
||||
Adbr::bits(0) |
|
||||
Ad_en::bits(0);
|
||||
}
|
||||
|
||||
};
|
||||
|
||||
/**
|
||||
* Control register 2
|
||||
*/
|
||||
struct Cr2 : Register<0x84, 32>
|
||||
{
|
||||
struct S_rst : Bitfield<0, 1> /* SW reset bit */
|
||||
{
|
||||
enum { NO_RESET = 1 };
|
||||
};
|
||||
|
||||
struct Rx_en : Bitfield<1, 1> { }; /* enable receiver */
|
||||
struct Tx_en : Bitfield<2, 1> { }; /* enable transmitter */
|
||||
struct At_en : Bitfield<3, 1> { }; /* enable aging timer */
|
||||
struct Rts_en : Bitfield<4, 1> { }; /* send request IRQ on */
|
||||
|
||||
struct Ws : Bitfield<5, 1> /* select word size */
|
||||
{
|
||||
enum { _8_BITS = 1 };
|
||||
};
|
||||
|
||||
struct Stpb : Bitfield<6, 1> /* number of stop bits */
|
||||
{
|
||||
enum { _1_BIT = 0 };
|
||||
};
|
||||
|
||||
struct Pr_en : Bitfield<8, 1> { }; /* enable parity */
|
||||
struct Esc_en : Bitfield<11, 1> { }; /* escape detection on */
|
||||
|
||||
struct Ctsc : Bitfield<13, 1> /* select CTS control */
|
||||
{
|
||||
enum { BY_RECEIVER = 1 };
|
||||
};
|
||||
|
||||
struct Irts : Bitfield<14, 1> { }; /* ignore RTS pin */
|
||||
struct Esci : Bitfield<15, 1> { }; /* enable escape IRQ */
|
||||
|
||||
/**
|
||||
* Initialization value
|
||||
*/
|
||||
static access_t init_value()
|
||||
{
|
||||
return S_rst::bits(S_rst::NO_RESET) |
|
||||
Rx_en::bits(0) |
|
||||
Tx_en::bits(1) |
|
||||
At_en::bits(0) |
|
||||
Rts_en::bits(0) |
|
||||
Ws::bits(Ws::_8_BITS) |
|
||||
Stpb::bits(Stpb::_1_BIT) |
|
||||
Pr_en::bits(0) |
|
||||
Esc_en::bits(0) |
|
||||
Ctsc::bits(Ctsc::BY_RECEIVER) |
|
||||
Irts::bits(1) |
|
||||
Esci::bits(0);
|
||||
}
|
||||
};
|
||||
|
||||
/**
|
||||
* Control register 3
|
||||
*/
|
||||
struct Cr3 : Register<0x88, 32>
|
||||
{
|
||||
struct Rxdmux_sel : Bitfield<2, 1> { }; /* use muxed RXD */
|
||||
struct Aci_en : Bitfield<0, 1> { }; /* autobaud count IRQ on */
|
||||
struct Dtrd_en : Bitfield<3, 1> { }; /* data terminal ready
|
||||
* delta IRQ on */
|
||||
struct Awak_en : Bitfield<4, 1> { }; /* wake IRQ on */
|
||||
struct Air_int_en : Bitfield<5, 1> { }; /* IR wake IRQ on */
|
||||
struct Rx_ds_en : Bitfield<6, 1> { }; /* RX status IRQ on */
|
||||
struct Ad_nimp : Bitfield<7, 1> { }; /* autobaud detect off */
|
||||
struct Ri_en : Bitfield<8, 1> { }; /* ring indicator IRQ on */
|
||||
struct Dcd_en : Bitfield<9, 1> { }; /* data carrier detect
|
||||
* IRQ on */
|
||||
struct Dsr : Bitfield<10,1> { }; /* DSR/DTR output */
|
||||
struct Frame_en : Bitfield<11,1> { }; /* frame error IRQ on */
|
||||
struct Parity_en : Bitfield<12,1> { }; /* parity error IRQ on */
|
||||
struct Dtr_en : Bitfield<13,1> { }; /* data terminal ready
|
||||
* IRQ on */
|
||||
struct Dpec_ctrl : Bitfield<14,2> { }; /* DTR/DSR IRQ edge
|
||||
* control */
|
||||
|
||||
/**
|
||||
* Initialization value
|
||||
*/
|
||||
static access_t init_value()
|
||||
{
|
||||
return Aci_en::bits(0) |
|
||||
Rxdmux_sel::bits(0) |
|
||||
Dtrd_en::bits(0) |
|
||||
Awak_en::bits(0) |
|
||||
Air_int_en::bits(0) |
|
||||
Rx_ds_en::bits(0) |
|
||||
Ad_nimp::bits(1) |
|
||||
Ri_en::bits(0) |
|
||||
Dcd_en::bits(0) |
|
||||
Dsr::bits(0) |
|
||||
Frame_en::bits(0) |
|
||||
Parity_en::bits(0) |
|
||||
Dtr_en::bits(0) |
|
||||
Dpec_ctrl::bits(0);
|
||||
}
|
||||
};
|
||||
|
||||
/**
|
||||
* Control register 4
|
||||
*/
|
||||
struct Cr4 : Register<0x8c, 32>
|
||||
{
|
||||
struct Dr_en : Bitfield<0, 1> { }; /* RX data ready IRQ on */
|
||||
struct Or_en : Bitfield<1, 1> { }; /* RX overrun IRQ on */
|
||||
struct Bk_en : Bitfield<2, 1> { }; /* BREAK IRQ on */
|
||||
struct Tc_en : Bitfield<3, 1> { }; /* TX complete IRQ on */
|
||||
struct Lp_dis : Bitfield<4, 1> { }; /* low power off */
|
||||
struct IR_sc : Bitfield<5, 1> { }; /* use UART ref clock
|
||||
* for vote logic */
|
||||
struct Id_dma_en : Bitfield<6, 1> { }; /* idle DMA IRQ on */
|
||||
struct Wake_en : Bitfield<7, 1> { }; /* WAKE IRQ on */
|
||||
struct IR_en : Bitfield<8, 1> { }; /* serial IR IRQ on */
|
||||
struct Cts_level : Bitfield<10,6> { }; /* CTS trigger level*/
|
||||
|
||||
/**
|
||||
* Initialization value
|
||||
*/
|
||||
static access_t init_value()
|
||||
{
|
||||
return Dr_en::bits(0) |
|
||||
Or_en::bits(0) |
|
||||
Bk_en::bits(0) |
|
||||
Tc_en::bits(0) |
|
||||
Lp_dis::bits(0) |
|
||||
IR_sc::bits(0) |
|
||||
Id_dma_en::bits(0) |
|
||||
Wake_en::bits(0) |
|
||||
IR_en::bits(0) |
|
||||
Cts_level::bits(0);
|
||||
}
|
||||
};
|
||||
|
||||
/**
|
||||
* Status register 2
|
||||
*/
|
||||
struct Sr2 : Register<0x98, 32>
|
||||
{
|
||||
struct Txdc : Bitfield<3, 1> { }; /* transmission complete */
|
||||
};
|
||||
|
||||
/**
|
||||
* Transmitter register
|
||||
*/
|
||||
struct Txd : Register<0x40, 32>
|
||||
{
|
||||
struct Tx_data : Bitfield<0, 8> { }; /* transmit data */
|
||||
};
|
||||
|
||||
/**
|
||||
* Transmit character 'c' without care about its type
|
||||
*/
|
||||
void _put_char(char c)
|
||||
{
|
||||
while (!read<Sr2::Txdc>()) ;
|
||||
write<Txd::Tx_data>(c);
|
||||
}
|
||||
|
||||
public:
|
||||
|
||||
/**
|
||||
* Constructor
|
||||
*
|
||||
* \param base device MMIO base
|
||||
*/
|
||||
Imx_uart(addr_t base, uint32_t, uint32_t) : Mmio({(char*)base, Mmio::SIZE})
|
||||
{
|
||||
init();
|
||||
}
|
||||
|
||||
void init()
|
||||
{
|
||||
write<Cr1>(Cr1::init_value());
|
||||
write<Cr2>(Cr2::init_value());
|
||||
write<Cr3>(Cr3::init_value());
|
||||
write<Cr4>(Cr4::init_value());
|
||||
}
|
||||
|
||||
/**
|
||||
* Print character 'c' through the UART
|
||||
*/
|
||||
void put_char(char c)
|
||||
{
|
||||
/* transmit character */
|
||||
_put_char(c);
|
||||
}
|
||||
};
|
||||
|
||||
#endif /* _INCLUDE__DRIVERS__UART__IMX_H_ */
|
||||
Loading…
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Reference in New Issue
Block a user