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base,os: Coding-style unification

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Fixes #1432
This commit is contained in:
Norman Feske
2015-03-04 21:12:14 +01:00
committed by Christian Helmuth
parent 56ed7addbc
commit e8336acafc
227 changed files with 19073 additions and 18833 deletions
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80
repos/base/include/platform/rpi/drivers/board_base.h
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@ -17,58 +17,58 @@
/* Genode includes */
#include <util/mmio.h>
namespace Genode
namespace Genode { struct Board_base; }
struct Genode::Board_base
{
struct Board_base
{
enum {
RAM_0_BASE = 0x00000000,
RAM_0_SIZE = 0x10000000, /* XXX ? */
enum {
RAM_0_BASE = 0x00000000,
RAM_0_SIZE = 0x10000000, /* XXX ? */
MMIO_0_BASE = 0x20000000,
MMIO_0_SIZE = 0x02000000,
MMIO_0_BASE = 0x20000000,
MMIO_0_SIZE = 0x02000000,
/*
* IRQ numbers 0..7 refer to the basic IRQs.
* IRQ numbers 8..39 refer to GPU IRQs 0..31.
* IRQ numbers 40..71 refer to GPU IRQs 32..63.
*/
GPU_IRQ_BASE = 8,
/*
* IRQ numbers 0..7 refer to the basic IRQs.
* IRQ numbers 8..39 refer to GPU IRQs 0..31.
* IRQ numbers 40..71 refer to GPU IRQs 32..63.
*/
GPU_IRQ_BASE = 8,
SYSTEM_TIMER_IRQ = GPU_IRQ_BASE + 1,
SYSTEM_TIMER_MMIO_BASE = 0x20003000,
SYSTEM_TIMER_MMIO_SIZE = 0x1000,
SYSTEM_TIMER_CLOCK = 1000000,
SYSTEM_TIMER_IRQ = GPU_IRQ_BASE + 1,
SYSTEM_TIMER_MMIO_BASE = 0x20003000,
SYSTEM_TIMER_MMIO_SIZE = 0x1000,
SYSTEM_TIMER_CLOCK = 1000000,
PL011_0_IRQ = 57,
PL011_0_MMIO_BASE = 0x20201000,
PL011_0_MMIO_SIZE = 0x1000,
PL011_0_CLOCK = 3000000,
PL011_0_IRQ = 57,
PL011_0_MMIO_BASE = 0x20201000,
PL011_0_MMIO_SIZE = 0x1000,
PL011_0_CLOCK = 3000000,
IRQ_CONTROLLER_BASE = 0x2000b200,
IRQ_CONTROLLER_SIZE = 0x100,
IRQ_CONTROLLER_BASE = 0x2000b200,
IRQ_CONTROLLER_SIZE = 0x100,
USB_DWC_OTG_BASE = 0x20980000,
USB_DWC_OTG_SIZE = 0x20000,
USB_DWC_OTG_BASE = 0x20980000,
USB_DWC_OTG_SIZE = 0x20000,
/* timer */
TIMER_IRQ = 0,
/* timer */
TIMER_IRQ = 0,
/* USB host controller */
DWC_IRQ = 17,
/* USB host controller */
DWC_IRQ = 17,
SECURITY_EXTENSION = 0,
SECURITY_EXTENSION = 0,
/* CPU cache */
CACHE_LINE_SIZE_LOG2 = 5,
};
enum Videocore_cache_policy { NON_COHERENT = 0,
COHERENT = 1,
L2_ONLY = 2,
UNCACHED = 3 };
/* CPU cache */
CACHE_LINE_SIZE_LOG2 = 5,
};
}
enum Videocore_cache_policy { NON_COHERENT = 0,
COHERENT = 1,
L2_ONLY = 2,
UNCACHED = 3 };
};
#endif /* _INCLUDE__PLATFORM__BOARD_BASE_H_ */