diff --git a/repos/base-hw/src/bootstrap/spec/arm_64/crt0.s b/repos/base-hw/src/bootstrap/spec/arm_64/crt0.s
index 882916783d..046fc94b03 100644
--- a/repos/base-hw/src/bootstrap/spec/arm_64/crt0.s
+++ b/repos/base-hw/src/bootstrap/spec/arm_64/crt0.s
@@ -28,6 +28,8 @@
 	.global _start
 	_start:
 
+	bl _mmu_disable
+
 	/**
 	 * Hack for Qemu, which starts all cpus at once
 	 * only first CPU runs through, all others wait for wakeup
@@ -45,6 +47,36 @@
 	.long 0
 
 
+	/*************************************
+	 ** Disable MMU of current EL (1-3) **
+	 *************************************/
+
+	_mmu_disable:
+	mrs  x8, CurrentEL
+	lsr  x8, x8, #2
+	cmp  x8, #0x2
+	b.eq _el2
+	b.hi _el3
+	_el1:
+	mrs x8, sctlr_el1
+	bic x8, x8, #(1 << 0)
+	msr sctlr_el1, x8
+	isb
+	ret
+	_el2:
+	mrs x8, sctlr_el2
+	bic x8, x8, #(1 << 0)
+	msr sctlr_el2, x8
+	isb
+	ret
+	_el3:
+	mrs x8, sctlr_el3
+	bic x8, x8, #(1 << 0)
+	msr sctlr_el3, x8
+	isb
+	ret
+
+
 	/***************************
 	 ** Zero-fill BSS segment **
 	 ***************************/
@@ -58,7 +90,6 @@
 	str xzr, [x1], #8
 	b 1b
 
-
 	/************************************
 	 ** Common Entrypoint for all CPUs **
 	 ************************************/
@@ -66,6 +97,8 @@
 	.global _crt0_start_secondary
 	_crt0_start_secondary:
 
+	bl _mmu_disable
+
 
 	/****************
 	 ** Enable FPU **