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hw: GICv3 implementation
* modern GICv3 implementation * distributor * redistributor * MMIO cpu interface Ref #3426
This commit is contained in:
Sebastian Sumpf
Christian Helmuth
parent
fa1aa33f83
commit
dd505edd19
62
repos/base-hw/src/bootstrap/spec/arm/gicv3.cc
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62
repos/base-hw/src/bootstrap/spec/arm/gicv3.cc
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/*
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* \brief GICv3 interrupt controller for core
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* \author Sebastian Sumpf
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* \date 2019-07-08
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*/
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/*
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* Copyright (C) 2019 Genode Labs GmbH
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*
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* This file is part of the Genode OS framework, which is distributed
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* under the terms of the GNU Affero General Public License version 3.
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*/
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#include <platform.h>
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Hw::Pic::Pic()
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: _distr(Board::Cpu_mmio::IRQ_CONTROLLER_DISTR_BASE),
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_redistr(Board::Cpu_mmio::IRQ_CONTROLLER_REDIST_BASE),
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_redistr_sgi(Board::Cpu_mmio::IRQ_CONTROLLER_REDIST_BASE +
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Board::Cpu_mmio::IRQ_CONTROLLER_REDIST_SIZE / 2),
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_max_irq(_distr.max_irq())
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{
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/* disable device */
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_distr.write<Distributor::Ctlr>(0);
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_distr.wait_for_rwp();
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/* XXX: remove */
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struct Affinity : Genode::Register<64>
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{
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struct Aff0 : Bitfield<0, 8> { };
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struct Aff1 : Bitfield<8, 8> { };
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struct Aff2 : Bitfield<16, 8> { };
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struct Aff3 : Bitfield<32, 8> { };
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};
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Genode::uint64_t mpidr = 0;
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asm volatile ("mrs %0, mpidr_el1" : "=r"(mpidr) : : "memory");
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Affinity::access_t affinity = 0;
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Affinity::Aff0::set(affinity, mpidr);
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Affinity::Aff1::set(affinity, (mpidr >> 8) & 0xff);
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Affinity::Aff2::set(affinity, (mpidr >> 16) & 0xff);
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Affinity::Aff3::set(affinity, (mpidr >> 32) & 0xff);
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/* configure every shared peripheral interrupt */
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for (unsigned i = min_spi; i <= _max_irq; i++) {
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_distr.write<Distributor::Icfgr::Edge_triggered>(0, i);
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_distr.write<Distributor::Ipriorityr::Priority>(0xa0, i);
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_distr.write<Distributor::Icenabler::Clear_enable>(1, i);
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_distr.write<Distributor::Icpendr::Clear_pending>(1, i);
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_distr.write<Distributor::Igroup0r::Group1>(1, i);
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/* XXX remove: route all SPIs to this PE */
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_distr.write<Distributor::Irouter>(affinity, i);
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}
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/* enable device GRP1_NS with affinity */
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Distributor::Ctlr::access_t ctlr = 0;
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Distributor::Ctlr::Enable_grp1_a::set(ctlr, 1);
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Distributor::Ctlr::Are_ns::set(ctlr, 1);
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_distr.write<Distributor::Ctlr>(ctlr);
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_distr.wait_for_rwp();
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}
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29
repos/base-hw/src/core/spec/arm/gicv3.cc
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29
repos/base-hw/src/core/spec/arm/gicv3.cc
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/*
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* \brief Generic Interrupt Controller version 3
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* \author Sebastian Sumpf
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* \date 2019-06-27
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*/
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/*
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* Copyright (C) 2019 Genode Labs GmbH
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*
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* This file is part of the Genode OS framework, which is distributed
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* under the terms of the GNU Affero General Public License version 3.
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*/
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/* core includes */
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#include <board.h>
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#include <platform.h>
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using namespace Genode;
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Hw::Pic::Pic()
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: _distr(Platform::mmio_to_virt(Board::Cpu_mmio::IRQ_CONTROLLER_DISTR_BASE)),
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_redistr(Platform::mmio_to_virt(Board::Cpu_mmio::IRQ_CONTROLLER_REDIST_BASE)),
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_redistr_sgi(Platform::mmio_to_virt(Board::Cpu_mmio::IRQ_CONTROLLER_REDIST_BASE)
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+ Board::Cpu_mmio::IRQ_CONTROLLER_REDIST_SIZE / 2),
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_max_irq(_distr.max_irq())
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{
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_redistributor_init();
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_cpui.init();
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}
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262
repos/base-hw/src/include/hw/spec/arm/gicv3.h
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262
repos/base-hw/src/include/hw/spec/arm/gicv3.h
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/*
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* \brief GICv3 interrupt controller for core
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* \author Sebastian Sumpf
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* \date 2019-07-08
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*/
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/*
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* Copyright (C) 2019 Genode Labs GmbH
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*
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* This file is part of the Genode OS framework, which is distributed
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* under the terms of the GNU Affero General Public License version 3.
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*/
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#ifndef _SRC__INCLUDE__HW__SPEC__ARM__GIC_V3_H_
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#define _SRC__INCLUDE__HW__SPEC__ARM__GIC_V3_H_
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#include <util/mmio.h>
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namespace Hw { class Pic; }
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#define SYSTEM_REGISTER(sz, name, reg, ...) \
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struct name : Genode::Register<sz> \
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{ \
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static access_t read() \
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{ \
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access_t v; \
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asm volatile ("mrs %0, " reg : "=r" (v)); \
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return v; \
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} \
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\
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static void write(access_t const v) { \
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asm volatile ("msr " reg ", %0" :: "r" (v)); } \
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\
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__VA_ARGS__; \
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};
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class Hw::Pic
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{
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protected:
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static constexpr unsigned min_spi = 32;
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static constexpr unsigned spurious_id = 1023;
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struct Distributor : Genode::Mmio
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{
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static constexpr unsigned nr_of_irq = 1024;
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/**
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* Control register (secure access)
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*/
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/* XXX: CAUTION this is different in EL3/EL2/EL1! */
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struct Ctlr : Register<0x0, 32>
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{
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struct Enable_grp0 : Bitfield<0, 1> { };
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struct Enable_grp1_a : Bitfield<1, 1> { };
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struct Are_ns : Bitfield<5, 1> { };
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struct Rwp : Bitfield<31, 1> { };
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};
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struct Typer : Register<0x004, 32> {
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struct It_lines_number : Bitfield<0,5> { }; };
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struct Igroup0r : Register_array<0x80, 32, 32*32, 1> {
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struct Group1 : Bitfield<0, 1> { }; };
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/**
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* Interrupt Set-Enable register
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*/
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struct Isenabler : Register_array<0x100, 32, 32*32, 1, true> {
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struct Set_enable : Bitfield<0, 1> { }; };
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/**
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* Interrupt clear enable registers
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*/
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struct Icenabler : Register_array<0x180, 32, 32*32, 1, true> {
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struct Clear_enable : Bitfield<0, 1> { }; };
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/**
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* Interrupt clear pending registers
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*/
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struct Icpendr : Register_array<0x280, 32, 32*32, 1, true> {
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struct Clear_pending : Bitfield<0, 1> { }; };
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/**
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* Interrupt priority level registers
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*/
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struct Ipriorityr : Register_array<0x400, 32, 255*4, 8> {
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struct Priority : Bitfield<0, 8> { }; };
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struct Icfgr : Register_array<0xc00, 32, 64*16, 2> {
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struct Edge_triggered : Bitfield<1, 1> { }; };
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struct Irouter : Register_array<0x6000, 64, 1020, 64, true> { };
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void wait_for_rwp()
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{
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for (unsigned i = 0; i < 1000; i++)
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if (read<Ctlr::Rwp>() == 0)
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return;
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}
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unsigned max_irq() { return 32 * (read<Typer::It_lines_number>() + 1) - 1; }
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Distributor(Genode::addr_t const base) : Genode::Mmio(base)
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{ }
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};
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struct Redistributor : Genode::Mmio
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{
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struct Ctlr : Register<0x0, 32>
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{
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struct Uwp : Bitfield<31, 1> { };
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};
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Redistributor(Genode::addr_t const base) : Genode::Mmio(base)
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{ }
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/* wait for upstream writes */
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void wait_for_uwp()
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{
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for (unsigned i = 0; i < 1000; i++)
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if (read<Ctlr::Uwp>() == 0)
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return;
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}
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};
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struct Redistributor_sgi_ppi : Genode::Mmio
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{
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struct Igroupr0 : Register<0x80, 32> { };
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struct Isenabler0 : Register_array<0x100, 32, 32, 1>
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{ };
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struct Icenabler0 : Register_array<0x180, 32, 32, 1>
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{ };
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struct Icactiver0 : Register<0x380, 32> { };
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struct Ipriorityr : Register_array<0x400, 32, min_spi, 8> {
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struct Priority : Bitfield<0, 8> { }; };
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struct Icfgr1 : Register<0xc04, 32> { };
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Redistributor_sgi_ppi(Genode::addr_t const base) : Genode::Mmio(base)
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{
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}
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};
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struct Cpu_interface
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{
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SYSTEM_REGISTER(32, Icc_sre_el1, "S3_0_C12_C12_5",
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struct Sre : Bitfield<0, 1> { };
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);
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SYSTEM_REGISTER(32, Icc_iar1_el1, "S3_0_C12_C12_0");
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SYSTEM_REGISTER(32, Icc_br1_el1, "S3_0_C12_C12_3");
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SYSTEM_REGISTER(32, Icc_pmr_el1, "S3_0_C4_C6_0");
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SYSTEM_REGISTER(32, Icc_igrpen1_el1, "S3_0_C12_C12_7");
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SYSTEM_REGISTER(32, Icc_eoir1_el1, "S3_0_C12_C12_1");
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void init()
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{
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/* enable register access */
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Icc_sre_el1::access_t sre = Icc_sre_el1::read();
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Icc_sre_el1::Sre::set(sre, 1);
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Icc_sre_el1::write(sre);
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/* XXX: check if needed or move somewhere else */
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asm volatile("isb sy" ::: "memory");
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/* no priority grouping */
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Icc_br1_el1::write(0);
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/* allow all priorities */
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Icc_pmr_el1::write(0xff);
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/* enable GRP1 interrupts */
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Icc_igrpen1_el1::write(1);
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/* XXX: check if needed or move somewhere else */
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asm volatile("isb sy" ::: "memory");
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}
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};
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void _redistributor_init()
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{
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/* diactivate SGI/PPI */
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_redistr_sgi.write<Redistributor_sgi_ppi::Icactiver0>(~0u);
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for (unsigned i = 0; i < min_spi; i++) {
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_redistr_sgi.write<Redistributor_sgi_ppi::Ipriorityr::Priority>(0xa0, i); }
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/* set group 1 for all PPI/SGIs */
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_redistr_sgi.write<Redistributor_sgi_ppi::Igroupr0>(~0);
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/* disable SGI/PPI */
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_redistr_sgi.write<Redistributor_sgi_ppi::Icenabler0>(~0);
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/* set PPIs to level triggered */
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_redistr_sgi.write<Redistributor_sgi_ppi::Icfgr1>(0);
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_redistr.wait_for_uwp();
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}
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Distributor _distr;
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Redistributor _redistr;
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Redistributor_sgi_ppi _redistr_sgi;
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Cpu_interface _cpui { };
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unsigned const _max_irq;
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Cpu_interface::Icc_iar1_el1::access_t _last_iar { spurious_id };
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bool _valid(unsigned const irq_id) const { return irq_id <= _max_irq; }
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public:
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Pic();
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enum { IPI = 0 };
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enum { NR_OF_IRQ = Distributor::nr_of_irq };
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bool take_request(unsigned &irq)
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{
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_last_iar = Cpu_interface::Icc_iar1_el1::read();
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irq = _last_iar;
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return _valid(irq);
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}
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void finish_request()
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{
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Cpu_interface::Icc_eoir1_el1::write(_last_iar);
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_last_iar = spurious_id;
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}
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void unmask(unsigned const irq_id, unsigned const /* cpu_id */)
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{
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if (irq_id < min_spi) {
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_redistr_sgi.write<Redistributor_sgi_ppi::Isenabler0>(1, irq_id);
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} else {
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_distr.write<Distributor::Isenabler::Set_enable>(1, irq_id);
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}
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}
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void mask(unsigned const irq_id)
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{
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if (irq_id < min_spi) {
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_redistr_sgi.write<Redistributor_sgi_ppi::Icenabler0>(1, irq_id);
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} else {
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_distr.write<Distributor::Icenabler::Clear_enable>(1, irq_id);
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}
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}
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};
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#undef SYSTEM_REGISTER
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#endif /* _SRC__INCLUDE__HW__SPEC__ARM__GIC_V3_H_ */
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