mirror of
https://github.com/genodelabs/genode.git
synced 2024-12-22 06:57:51 +00:00
Alexander Boettcher
Christian Helmuth
parent
f0f473392d
commit
cf3ff17c50
@ -6,4 +6,6 @@ SRC_S += bootstrap/spec/x86_64/crt0_translation_table.s
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SRC_CC += hw/spec/64bit/memory_map.cc
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NR_OF_CPUS = 32
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include $(BASE_DIR)/../base-hw/lib/mk/bootstrap-hw.inc
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@ -20,7 +20,6 @@ SRC_CC += spec/x86_64/kernel/thread_exception.cc
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SRC_CC += spec/x86_64/platform_support.cc
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SRC_CC += spec/x86/platform_services.cc
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SRC_CC += kernel/kernel.cc
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SRC_CC += spec/x86/io_port_session_component.cc
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SRC_CC += spec/x86/io_port_session_support.cc
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SRC_CC += spec/x86_64/bios_data_area.cc
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@ -30,10 +29,14 @@ SRC_CC += spec/x86_64/kernel/cpu.cc
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SRC_CC += spec/x86_64/kernel/thread.cc
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SRC_CC += spec/x86_64/kernel/thread.cc
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SRC_CC += spec/x86_64/platform_support_common.cc
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SRC_CC += spec/x86_64/smp/cpu.cc
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SRC_CC += spec/64bit/memory_map.cc
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vpath spec/64bit/memory_map.cc $(BASE_DIR)/../base-hw/src/lib/hw
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NR_OF_CPUS = 32
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# include less specific configuration
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include $(BASE_DIR)/../base-hw/lib/mk/core-hw.inc
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include $(BASE_DIR)/../base-hw/lib/mk/spec/smp/core-hw.inc
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@ -1 +1 @@
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a4ce6a1f3bc1209e4c9f8ecf163d7af354c188af
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e51f0c9bfe99c284b3cf3bcf5fb81f7e9052f8a6
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10
repos/base-hw/ports/muen.patch
Normal file
10
repos/base-hw/ports/muen.patch
Normal file
@ -0,0 +1,10 @@
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+++ src/kernel/muen/policy/xml/vcpu_subject_base_hw.xml
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@@ -9,7 +9,7 @@
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</vmx>
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<registers>
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<gpr>
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- <rip>16#0020_0028#</rip>
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+ <rip>16#0020_0078#</rip>
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<rsp>16#0000#</rsp>
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</gpr>
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</registers>
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@ -6,6 +6,8 @@ URL(muen) := https://git.codelabs.ch/git/muen.git
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REV(muen) := 807cb0381e12329d84cb7e6b2f778b1e1559a2e8
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DIR(muen) := src/kernel/muen
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PATCHES := ports/muen.patch
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$(call check_tool,git)
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$(call check_tool,iasl)
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$(call check_tool,tidy)
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@ -4,16 +4,19 @@
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* \author Martin Stein
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* \author Reto Buerki
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* \author Stefan Kalkowski
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* \author Alexander Boettcher
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* \date 2015-02-06
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*/
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/*
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* Copyright (C) 2011-2017 Genode Labs GmbH
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* Copyright (C) 2011-2018 Genode Labs GmbH
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*
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* This file is part of the Genode OS framework, which is distributed
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* under the terms of the GNU Affero General Public License version 3.
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*/
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.set STACK_SIZE, 4096
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.section ".text.crt0"
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/* magic multi-boot 1 header */
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@ -34,9 +37,55 @@
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.long 0x8
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__mbi2_end:
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/**********************************
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** Startup code for primary CPU **
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**********************************/
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.macro SETUP_PAGING
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/* Enable PAE (prerequisite for IA-32e mode) */
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movl $0x20, %eax
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movl %eax, %cr4
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/* Enable IA-32e mode and execute-disable */
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movl $0xc0000080, %ecx
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rdmsr
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btsl $8, %eax
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btsl $11, %eax
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wrmsr
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/* Enable paging, write protection and caching */
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xorl %eax, %eax
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btsl $0, %eax /* protected mode */
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btsl $16, %eax /* write protect */
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btsl $31, %eax /* paging */
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movl %eax, %cr0
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.endm
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/*******************************************************************
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** Startup code for non-primary CPU (AP - application processor) **
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*******************************************************************/
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.code16
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.global _ap
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_ap:
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/* Load initial pagetables */
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mov $_kernel_pml4, %eax
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mov %eax, %cr3
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/* setup paging */
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SETUP_PAGING
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/* setup GDT */
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lgdtl %cs:__gdt - _ap
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ljmpl $8, $_start64
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__gdt:
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.word 55
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.long __gdt_start
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/**************************************************************
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** Startup code for primary CPU (bootstrap processor - BSP) **
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**************************************************************/
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.code32
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.global _start
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@ -55,40 +104,30 @@
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xor %eax, %eax
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rep stosl
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/* Enable PAE (prerequisite for IA-32e mode) */
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movl %cr4, %eax
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btsl $5, %eax
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movl %eax, %cr4
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/* Load initial pagetables */
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leal _kernel_pml4, %eax
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mov %eax, %cr3
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/* Enable IA-32e mode and execute-disable */
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movl $0xc0000080, %ecx
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rdmsr
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btsl $8, %eax
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btsl $11, %eax
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wrmsr
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/* setup paging */
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SETUP_PAGING
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/* Enable paging, write protection and caching */
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movl %cr0, %eax
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btsl $16, %eax
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btrl $29, %eax
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btrl $30, %eax
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btsl $31, %eax
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movl %eax, %cr0
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/* Set up GDT */
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movl $__gdt_ptr+2, %eax
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movl $__gdt_start, (%eax)
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/* setup GDT */
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lgdt __gdt_ptr
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/* Indirect long jump to 64-bit code */
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ljmp $8, $_start64
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ljmp $8, $_start64_bsp
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.code64
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_start64_bsp:
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/* save rax & rbx, used to lookup multiboot structures */
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movq __initial_ax@GOTPCREL(%rip),%rax
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movq %rsi, (%rax)
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movq __initial_bx@GOTPCREL(%rip),%rax
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movq %rbx, (%rax)
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_start64:
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/*
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@ -99,26 +138,38 @@
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mov %eax, %fs
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mov %eax, %gs
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/*
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* Install initial temporary environment that is replaced later by the
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* environment that init_main_thread creates.
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*/
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leaq _stack_high@GOTPCREL(%rip),%rax
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/* increment CPU counter atomically */
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movq __cpus_booted@GOTPCREL(%rip),%rax
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movq $1, %rcx
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lock xaddq %rcx, (%rax)
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/* if more CPUs started than supported, then stop them */
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cmp $NR_OF_CPUS, %rcx
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jge 1f
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/* calculate stack depending on CPU counter */
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movq $STACK_SIZE, %rax
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inc %rcx
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mulq %rcx
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movq %rax, %rcx
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subq $8, %rcx
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leaq __bootstrap_stack@GOTPCREL(%rip),%rax
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movq (%rax), %rsp
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movq __initial_ax@GOTPCREL(%rip),%rax
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movq %rsi, (%rax)
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movq __initial_bx@GOTPCREL(%rip),%rax
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movq %rbx, (%rax)
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addq %rcx, %rsp
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/* kernel-initialization */
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call init
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/* catch erroneous return of the kernel initialization */
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1: jmp 1b
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1:
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hlt
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jmp 1b
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.global bootstrap_stack_size
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bootstrap_stack_size:
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.quad STACK_SIZE
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/******************************************
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** Global Descriptor Table (GDT) **
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** See Intel SDM Vol. 3A, section 3.5.1 **
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@ -128,7 +179,7 @@
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.space 2
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__gdt_ptr:
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.word 55 /* limit */
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.long 0 /* base address */
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.long __gdt_start /* base address */
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.set TSS_LIMIT, 0x68
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.set TSS_TYPE, 0x8900
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@ -171,12 +222,19 @@
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.bss
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/* stack of the temporary initial environment */
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.p2align 8
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.space 32 * 1024
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_stack_high:
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.p2align 12
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.globl __bootstrap_stack
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__bootstrap_stack:
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.rept NR_OF_CPUS
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.space STACK_SIZE
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.endr
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.globl __initial_ax
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__initial_ax:
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.space 8
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.globl __initial_bx
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__initial_bx:
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.space 8
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.globl __cpus_booted
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__cpus_booted:
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.quad 0
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@ -34,14 +34,15 @@
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/* PDP */
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.p2align MIN_PAGE_SIZE_LOG2
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_kernel_pdp:
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.quad _kernel_pd + 0xf
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.fill 2, 8, 0x0
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.quad _kernel_pd_503 + 0xf
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.quad _kernel_pd_0 + 0xf
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.fill 1, 8, 0x0
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.quad _kernel_pd_2 + 0xf
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.quad _kernel_pd_3 + 0xf
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.fill 508, 8, 0x0
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/* PD */
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/* PD [0G-1G) */
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.p2align MIN_PAGE_SIZE_LOG2
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_kernel_pd:
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_kernel_pd_0:
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.quad _kernel_pt_bda + 0xf
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.set entry, 0x20018f
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.rept 511
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@ -49,9 +50,23 @@
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.set entry, entry + 0x200000
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.endr
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/* PD [2G-3G) */
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.p2align MIN_PAGE_SIZE_LOG2
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_kernel_pd_503:
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.fill 502, 8, 0x0
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_kernel_pd_2:
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.set entry, 0x8000018f
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.rept 512
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.quad entry
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.set entry, entry + 0x200000
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.endr
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/* PD [3G-4G) */
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.p2align MIN_PAGE_SIZE_LOG2
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_kernel_pd_3:
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.set entry, 0xc000018f
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.rept 502
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.quad entry
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.set entry, entry + 0x200000
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.endr
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.quad 0xfec0019f
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.quad 0xfee0019f
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.fill 8, 8, 0x0
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@ -2,11 +2,12 @@
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* \brief Platform implementations specific for x86_64
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* \author Reto Buerki
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* \author Stefan Kalkowski
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* \author Alexander Boettcher
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* \date 2015-05-04
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*/
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/*
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* Copyright (C) 2015-2017 Genode Labs GmbH
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* Copyright (C) 2015-2018 Genode Labs GmbH
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*
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* This file is part of the Genode OS framework, which is distributed
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* under the terms of the GNU Affero General Public License version 3.
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@ -27,6 +28,39 @@ extern "C" Genode::addr_t __initial_ax;
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/* contains physical pointer to multiboot */
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extern "C" Genode::addr_t __initial_bx;
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/* pointer to stack base */
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extern "C" Genode::addr_t __bootstrap_stack;
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/* number of booted CPUs */
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extern "C" Genode::addr_t __cpus_booted;
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/* stack size per CPU */
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extern "C" Genode::addr_t const bootstrap_stack_size;
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/* hardcoded physical page or AP CPUs boot code */
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enum { AP_BOOT_CODE_PAGE = 0x1000 };
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extern "C" void * _start;
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extern "C" void * _ap;
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static Hw::Acpi_rsdp search_rsdp(addr_t area, addr_t area_size)
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{
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if (area && area_size && area < area + area_size) {
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for (addr_t addr = 0; addr + sizeof(Hw::Acpi_rsdp) <= area_size;
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addr += sizeof(Hw::Acpi_rsdp::signature))
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{
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Hw::Acpi_rsdp * rsdp = reinterpret_cast<Hw::Acpi_rsdp *>(area + addr);
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if (rsdp->valid())
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return *rsdp;
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}
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}
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Hw::Acpi_rsdp invalid;
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return invalid;
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}
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Bootstrap::Platform::Board::Board()
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: core_mmio(Memory_region { 0, 0x1000 },
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Memory_region { Hw::Cpu_memory_map::lapic_phys_base(), 0x1000 },
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@ -97,22 +131,37 @@ Bootstrap::Platform::Board::Board()
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lambda(base, size);
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}
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/* search ACPI RSDP pointer at known places */
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/* BIOS range to scan for */
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enum { BIOS_BASE = 0xe0000, BIOS_SIZE = 0x20000 };
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acpi_rsdp = search_rsdp(BIOS_BASE, BIOS_SIZE);
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if (!acpi_rsdp.valid()) {
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/* page 0 is remapped to 2M - 4k - see crt_translation table */
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addr_t const bios_addr = 2 * 1024 * 1024 - 4096;
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/* search EBDA (BIOS addr + 0x40e) */
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addr_t ebda_phys = (*reinterpret_cast<uint16_t *>(bios_addr + 0x40e)) << 4;
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if (ebda_phys < 0x1000)
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ebda_phys = bios_addr;
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acpi_rsdp = search_rsdp(ebda_phys, 0x1000 /* EBDA size */);
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}
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} else {
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error("invalid multiboot magic value: ", Hex(__initial_ax));
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}
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if (!acpi_rsdp.valid())
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return;
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uint64_t const table_addr = acpi_rsdp.xsdt ? acpi_rsdp.xsdt : acpi_rsdp.rsdt;
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if (!table_addr)
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return;
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/* find out the number of available CPUs */
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/* remember max supported CPUs and use ACPI to get the actual number */
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unsigned const max_cpus = cpus;
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cpus = 0;
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/* scan ACPI tables to find out number of CPUs in this machine */
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if (acpi_rsdp.valid()) {
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uint64_t const table_addr = acpi_rsdp.xsdt ? acpi_rsdp.xsdt : acpi_rsdp.rsdt;
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if (table_addr) {
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Hw::Acpi_generic * table = reinterpret_cast<Hw::Acpi_generic *>(table_addr);
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if (!memcmp(table->signature, "RSDT", 4)) {
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Hw::for_each_rsdt_entry(*table, [&](uint32_t paddr_table) {
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@ -144,20 +193,116 @@ Bootstrap::Platform::Board::Board()
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}
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});
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});
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} else
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Genode::error("unknown table signature");
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}
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}
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}
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if (!cpus || cpus > max_cpus) {
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Genode::warning("CPU count is unsupported ", cpus, "/", max_cpus);
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cpus = max_cpus;
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}
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Genode::warning("CPU count is unsupported ", cpus, "/", max_cpus,
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acpi_rsdp.valid() ? " - invalid or missing RSDT/XSDT"
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: " - invalid RSDP");
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cpus = !cpus ? 1 : max_cpus;
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}
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if (cpus > 1) {
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/* copy 16 bit boot code for AP CPUs */
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addr_t ap_code_size = (addr_t)&_start - (addr_t)&_ap;
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memcpy((void *)AP_BOOT_CODE_PAGE, &_ap, ap_code_size);
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}
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}
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struct Lapic : Mmio
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{
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struct Svr : Register<0x0f0, 32>
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{
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struct APIC_enable : Bitfield<8, 1> { };
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};
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struct Icr_low : Register<0x300, 32> {
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struct Vector : Bitfield< 0, 8> { };
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struct Delivery_mode : Bitfield< 8, 3> {
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enum Mode { INIT = 5, SIPI = 6 };
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};
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struct Delivery_status : Bitfield<12, 1> { };
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struct Level_assert : Bitfield<14, 1> { };
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struct Dest_shorthand : Bitfield<18, 2> {
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enum { ALL_OTHERS = 3 };
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};
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};
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struct Icr_high : Register<0x310, 32> {
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struct Destination : Bitfield<24, 8> { };
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};
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Lapic(addr_t const addr) : Mmio(addr) { }
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};
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static inline Genode::uint64_t rdtsc()
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{
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Genode::uint32_t lo, hi;
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asm volatile("rdtsc" : "=a" (lo), "=d" (hi));
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return (Genode::uint64_t)hi << 32 | lo;
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}
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static inline void ipi_to_all(Lapic &lapic, unsigned const boot_frame,
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Lapic::Icr_low::Delivery_mode::Mode const mode)
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{
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/* wait until ready */
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while (lapic.read<Lapic::Icr_low::Delivery_status>())
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asm volatile ("pause":::"memory");
|
||||
|
||||
unsigned const apic_cpu_id = 0; /* unused for IPI to all */
|
||||
|
||||
Lapic::Icr_low::access_t icr_low = 0;
|
||||
|
||||
Lapic::Icr_low::Vector::set(icr_low, boot_frame);
|
||||
Lapic::Icr_low::Delivery_mode::set(icr_low, mode);
|
||||
Lapic::Icr_low::Level_assert::set(icr_low);
|
||||
Lapic::Icr_low::Level_assert::set(icr_low);
|
||||
Lapic::Icr_low::Dest_shorthand::set(icr_low, Lapic::Icr_low::Dest_shorthand::ALL_OTHERS);
|
||||
|
||||
/* program */
|
||||
lapic.write<Lapic::Icr_high::Destination>(apic_cpu_id);
|
||||
lapic.write<Lapic::Icr_low>(icr_low);
|
||||
}
|
||||
|
||||
unsigned Bootstrap::Platform::enable_mmu()
|
||||
{
|
||||
Cpu::Cr3::write(Cpu::Cr3::Pdb::masked((addr_t)core_pd->table_base));
|
||||
return 0;
|
||||
|
||||
addr_t const stack_base = reinterpret_cast<addr_t>(&__bootstrap_stack);
|
||||
addr_t const this_stack = reinterpret_cast<addr_t>(&stack_base);
|
||||
addr_t const cpu_id = (this_stack - stack_base) / bootstrap_stack_size;
|
||||
|
||||
/* we like to use local APIC */
|
||||
Cpu::IA32_apic_base::access_t lapic_msr = Cpu::IA32_apic_base::read();
|
||||
Cpu::IA32_apic_base::Lapic::set(lapic_msr);
|
||||
Cpu::IA32_apic_base::write(lapic_msr);
|
||||
|
||||
/* skip the SMP when ACPI parsing did not reveal the number of CPUs */
|
||||
if (board.cpus <= 1)
|
||||
return cpu_id;
|
||||
|
||||
Lapic lapic(board.core_mmio.virt_addr(Hw::Cpu_memory_map::lapic_phys_base()));
|
||||
|
||||
/* enable local APIC if required */
|
||||
if (!lapic.read<Lapic::Svr::APIC_enable>())
|
||||
lapic.write<Lapic::Svr::APIC_enable>(true);
|
||||
|
||||
if (!Cpu::IA32_apic_base::Bsp::get(lapic_msr))
|
||||
/* AP - done */
|
||||
return cpu_id;
|
||||
|
||||
/* BSP - we're primary CPU - wake now all other CPUs */
|
||||
|
||||
/* see Intel Multiprocessor documentation - we need to do INIT-SIPI-SIPI */
|
||||
ipi_to_all(lapic, 0 /* unused */, Lapic::Icr_low::Delivery_mode::INIT);
|
||||
/* wait 10 ms - debates ongoing whether this is still required */
|
||||
ipi_to_all(lapic, AP_BOOT_CODE_PAGE >> 12, Lapic::Icr_low::Delivery_mode::SIPI);
|
||||
/* wait 200 us - debates ongoing whether this is still required */
|
||||
/* debates ongoing whether the second SIPI is still required */
|
||||
ipi_to_all(lapic, AP_BOOT_CODE_PAGE >> 12, Lapic::Icr_low::Delivery_mode::SIPI);
|
||||
|
||||
return cpu_id;
|
||||
}
|
||||
|
||||
|
||||
|
||||
@ -105,6 +105,10 @@ void Genode::Cpu::mmu_fault(Context & regs, Kernel::Thread_fault & fault)
|
||||
}
|
||||
|
||||
|
||||
extern void const * const kernel_stack;
|
||||
extern Genode::size_t const kernel_stack_size;
|
||||
|
||||
|
||||
void Genode::Cpu::switch_to(Context & context, Mmu_context &mmu_context)
|
||||
{
|
||||
_fpu.switch_to(context);
|
||||
@ -113,4 +117,19 @@ void Genode::Cpu::switch_to(Context & context, Mmu_context &mmu_context)
|
||||
Cr3::write(mmu_context.cr3);
|
||||
|
||||
tss.ist[0] = (addr_t)&context + sizeof(Genode::Cpu_state);
|
||||
|
||||
addr_t const stack_base = reinterpret_cast<addr_t>(&kernel_stack);
|
||||
context.kernel_stack = stack_base +
|
||||
(Cpu::executing_id() + 1) * kernel_stack_size -
|
||||
sizeof(addr_t);
|
||||
}
|
||||
|
||||
|
||||
unsigned Genode::Cpu::executing_id()
|
||||
{
|
||||
void * const stack_ptr = nullptr;
|
||||
addr_t const stack_addr = reinterpret_cast<addr_t>(&stack_ptr);
|
||||
addr_t const stack_base = reinterpret_cast<addr_t>(&kernel_stack);
|
||||
unsigned const cpu_id = (stack_addr - stack_base) / kernel_stack_size;
|
||||
return cpu_id;
|
||||
}
|
||||
|
||||
@ -92,7 +92,10 @@ class Genode::Cpu : public Hw::X86_64_cpu
|
||||
/**
|
||||
* Extend basic CPU state by members relevant for 'base-hw' only
|
||||
*/
|
||||
struct alignas(16) Context : Cpu_state, Fpu::Context
|
||||
struct Kernel_stack { unsigned long kernel_stack { }; };
|
||||
|
||||
/* exception_vector.s depends on the position of the Kernel_stack */
|
||||
struct alignas(16) Context : Cpu_state, Kernel_stack, Fpu::Context
|
||||
{
|
||||
enum Eflags {
|
||||
EFLAGS_IF_SET = 1 << 9,
|
||||
@ -100,7 +103,7 @@ class Genode::Cpu : public Hw::X86_64_cpu
|
||||
};
|
||||
|
||||
Context(bool privileged);
|
||||
};
|
||||
} __attribute__((packed));
|
||||
|
||||
|
||||
struct Mmu_context
|
||||
@ -121,7 +124,7 @@ class Genode::Cpu : public Hw::X86_64_cpu
|
||||
/**
|
||||
* Return kernel name of the executing CPU
|
||||
*/
|
||||
static unsigned executing_id() { return 0; }
|
||||
static unsigned executing_id();
|
||||
|
||||
/**
|
||||
* Return kernel name of the primary CPU
|
||||
|
||||
@ -2,11 +2,12 @@
|
||||
* \brief Startup code for Genode 64Bit applications
|
||||
* \author Sebastian Sumpf
|
||||
* \author Martin Stein
|
||||
* \author Alexander Boettcher
|
||||
* \date 2011-05-11
|
||||
*/
|
||||
|
||||
/*
|
||||
* Copyright (C) 2011-2017 Genode Labs GmbH
|
||||
* Copyright (C) 2011-2018 Genode Labs GmbH
|
||||
*
|
||||
* This file is part of the Genode OS framework, which is distributed
|
||||
* under the terms of the GNU Affero General Public License version 3.
|
||||
@ -21,11 +22,20 @@
|
||||
.global _start
|
||||
_start:
|
||||
|
||||
/* load kernel stack size */
|
||||
movq kernel_stack_size@GOTPCREL(%rip), %rbx
|
||||
movq (%rbx), %rax
|
||||
|
||||
/* calculate stack top (rdi contains cpu_id), stack top is stored in rax */
|
||||
movq %rdi, %rbx
|
||||
inc %rbx
|
||||
mulq %rbx
|
||||
|
||||
/* switch to kernel stack */
|
||||
mov kernel_stack@GOTPCREL(%rip), %rax
|
||||
mov kernel_stack_size@GOTPCREL(%rip), %rbx
|
||||
add (%rbx), %rax
|
||||
mov %rax, %rsp
|
||||
movq kernel_stack@GOTPCREL(%rip), %rbx
|
||||
addq %rbx, %rax
|
||||
subq $8, %rax
|
||||
movq %rax, %rsp
|
||||
|
||||
/* jump to C entry code */
|
||||
jmp kernel_init
|
||||
|
||||
@ -111,12 +111,22 @@
|
||||
pushq %r9
|
||||
pushq %r8
|
||||
|
||||
/**
|
||||
* Calculate offset into Kernel_stack member of Cpu::Context as defined
|
||||
* in cpu.h - struct Context : Cpu_state, Kernel_stack, Fpu_context
|
||||
*/
|
||||
.set REGISTER_COUNT, 22
|
||||
.set REGISTER_SIZE, 8
|
||||
.set SIZEOF_CPU_STATE, REGISTER_COUNT * REGISTER_SIZE /* sizeof (Cpu_state) */
|
||||
.set KERNEL_STACK_OFFSET, SIZEOF_CPU_STATE
|
||||
/* rsp contains pointer to Cpu::Context */
|
||||
|
||||
/* Restore kernel stack and continue kernel execution */
|
||||
_load_address kernel_stack rax
|
||||
_load_address kernel_stack_size rbx
|
||||
movq %rsp, %rax
|
||||
addq $KERNEL_STACK_OFFSET, %rax
|
||||
movq (%rax), %rsp
|
||||
|
||||
_load_address kernel rcx
|
||||
add (%rbx), %rax
|
||||
mov %rax, %rsp
|
||||
jmp *%rcx
|
||||
|
||||
|
||||
@ -159,5 +169,7 @@
|
||||
|
||||
.global idle_thread_main
|
||||
idle_thread_main:
|
||||
pause
|
||||
sti
|
||||
hlt
|
||||
cli
|
||||
jmp idle_thread_main
|
||||
|
||||
@ -30,6 +30,7 @@ void Kernel::Cpu::init(Pic &pic)
|
||||
|
||||
/* enable timer interrupt */
|
||||
unsigned const cpu = Cpu::executing_id();
|
||||
pic.store_apic_id(cpu);
|
||||
pic.unmask(_timer.interrupt_id(), cpu);
|
||||
}
|
||||
|
||||
|
||||
@ -62,6 +62,7 @@ class Genode::Pic
|
||||
void mask(unsigned const) { }
|
||||
bool is_ip_interrupt(unsigned, unsigned) { return false; }
|
||||
void trigger_ip_interrupt(unsigned) { }
|
||||
void store_apic_id(unsigned const) { }
|
||||
|
||||
private:
|
||||
|
||||
|
||||
@ -2,11 +2,12 @@
|
||||
* \brief Programmable interrupt controller for core
|
||||
* \author Adrian-Ken Rueegsegger
|
||||
* \author Reto Buerki
|
||||
* \author Alexander Boettcher
|
||||
* \date 2015-02-17
|
||||
*/
|
||||
|
||||
/*
|
||||
* Copyright (C) 2015-2017 Genode Labs GmbH
|
||||
* Copyright (C) 2015-2018 Genode Labs GmbH
|
||||
*
|
||||
* This file is part of the Genode OS framework, which is distributed
|
||||
* under the terms of the GNU Affero General Public License version 3.
|
||||
@ -23,6 +24,8 @@
|
||||
|
||||
using namespace Genode;
|
||||
|
||||
uint8_t Pic::lapic_ids[NR_OF_CPUS];
|
||||
|
||||
enum {
|
||||
PIC_CMD_MASTER = 0x20,
|
||||
PIC_CMD_SLAVE = 0xa0,
|
||||
@ -99,6 +102,25 @@ inline unsigned Pic::get_lowest_bit(void)
|
||||
return 0;
|
||||
}
|
||||
|
||||
void Pic::send_ipi(unsigned const cpu_id) {
|
||||
|
||||
while (read<Icr_low::Delivery_status>())
|
||||
asm volatile("pause" : : : "memory");
|
||||
|
||||
Icr_high::access_t icr_high = 0;
|
||||
Icr_low::access_t icr_low = 0;
|
||||
|
||||
Icr_high::Destination::set(icr_high, lapic_ids[cpu_id]);
|
||||
|
||||
Icr_low::Vector::set(icr_low, Pic::IPI);
|
||||
Icr_low::Level_assert::set(icr_low);
|
||||
|
||||
/* program */
|
||||
write<Icr_high>(icr_high);
|
||||
write<Icr_low>(icr_low);
|
||||
|
||||
}
|
||||
|
||||
Ioapic::Irq_mode Ioapic::_irq_mode[IRQ_COUNT];
|
||||
|
||||
void Ioapic::setup_irq_mode(unsigned irq_number, unsigned trigger,
|
||||
|
||||
@ -1,11 +1,12 @@
|
||||
/*
|
||||
* \brief Programmable interrupt controller for core
|
||||
* \author Reto Buerki
|
||||
* \author Alexander Boettcher
|
||||
* \date 2015-02-17
|
||||
*/
|
||||
|
||||
/*
|
||||
* Copyright (C) 2015-2017 Genode Labs GmbH
|
||||
* Copyright (C) 2015-2018 Genode Labs GmbH
|
||||
*
|
||||
* This file is part of the Genode OS framework, which is distributed
|
||||
* under the terms of the GNU Affero General Public License version 3.
|
||||
@ -142,6 +143,7 @@ class Genode::Pic : public Mmio
|
||||
* Registers
|
||||
*/
|
||||
|
||||
struct Id : Register<0x020, 32> { };
|
||||
struct EOI : Register<0x0b0, 32, true> { };
|
||||
struct Svr : Register<0x0f0, 32>
|
||||
{
|
||||
@ -155,6 +157,18 @@ class Genode::Pic : public Mmio
|
||||
*/
|
||||
struct Isr : Register_array<0x100, 32, 8 * 4, 32> { };
|
||||
|
||||
/*
|
||||
* Interrupt control register
|
||||
*/
|
||||
struct Icr_low : Register<0x300, 32, true> {
|
||||
struct Vector : Bitfield< 0, 8> { };
|
||||
struct Delivery_status : Bitfield<12, 1> { };
|
||||
struct Level_assert : Bitfield<14, 1> { };
|
||||
};
|
||||
struct Icr_high : Register<0x310, 32, true> {
|
||||
struct Destination : Bitfield<24, 8> { };
|
||||
};
|
||||
|
||||
/**
|
||||
* Determine lowest pending interrupt in ISR register
|
||||
*
|
||||
@ -163,6 +177,11 @@ class Genode::Pic : public Mmio
|
||||
*/
|
||||
inline unsigned get_lowest_bit(void);
|
||||
|
||||
/**
|
||||
* Mapping of our logical boot CPUs to the local APIC IDs
|
||||
*/
|
||||
static uint8_t lapic_ids[NR_OF_CPUS];
|
||||
|
||||
public:
|
||||
|
||||
enum {
|
||||
@ -190,12 +209,12 @@ class Genode::Pic : public Mmio
|
||||
|
||||
void mask(unsigned const i);
|
||||
|
||||
/*
|
||||
* Dummies
|
||||
*/
|
||||
void store_apic_id(unsigned const cpu_id) {
|
||||
Id::access_t const lapic_id = read<Id>();
|
||||
lapic_ids[cpu_id] = (lapic_id >> 24) & 0xff;
|
||||
}
|
||||
|
||||
bool is_ip_interrupt(unsigned, unsigned) { return false; }
|
||||
void trigger_ip_interrupt(unsigned) { }
|
||||
void send_ipi(unsigned const);
|
||||
};
|
||||
|
||||
namespace Kernel { using Genode::Pic; }
|
||||
|
||||
25
repos/base-hw/src/core/spec/x86_64/smp/cpu.cc
Normal file
25
repos/base-hw/src/core/spec/x86_64/smp/cpu.cc
Normal file
@ -0,0 +1,25 @@
|
||||
/*
|
||||
* \brief Cpu class implementation specific to SMP
|
||||
* \author Stefan Kalkowski
|
||||
* \date 2015-12-09
|
||||
*/
|
||||
|
||||
/*
|
||||
* Copyright (C) 2015-2017 Genode Labs GmbH
|
||||
*
|
||||
* This file is part of the Genode OS framework, which is distributed
|
||||
* under the terms of the GNU Affero General Public License version 3.
|
||||
*/
|
||||
|
||||
/* core includes */
|
||||
#include <kernel/lock.h>
|
||||
#include <kernel/kernel.h>
|
||||
#include <kernel/cpu.h>
|
||||
|
||||
/* base-internal includes */
|
||||
#include <base/internal/unmanaged_singleton.h>
|
||||
|
||||
|
||||
/* spin-lock used to synchronize kernel access of different cpus */
|
||||
Kernel::Lock & Kernel::data_lock() {
|
||||
return *unmanaged_singleton<Kernel::Lock>(); }
|
||||
@ -11,6 +11,7 @@ if {
|
||||
![expr [have_spec zynq] && ![have_spec zynq_qemu] ] &&
|
||||
![expr [have_spec x86_32] && [have_spec foc] ] &&
|
||||
![expr [have_spec x86_64] && [have_spec foc] ] &&
|
||||
![expr [have_spec x86_64] && [have_spec hw] ] &&
|
||||
![have_spec nova] &&
|
||||
![have_spec sel4]
|
||||
} {
|
||||
|
||||
@ -40,7 +40,6 @@ if {[have_include "power_on/qemu"]} {
|
||||
if {[have_spec okl4]} { set want_cpus 1 }
|
||||
if {[have_spec pistachio]} { set want_cpus 1 }
|
||||
if {[have_spec fiasco]} { set want_cpus 1 }
|
||||
if {([have_spec x86_64] && [have_spec hw])} { set want_cpus 1 }
|
||||
if {[have_spec zynq]} { set want_cpus 1 }
|
||||
|
||||
append qemu_args " -nographic -smp $want_cpus,cores=$want_cpus "
|
||||
|
||||
Loading…
Reference in New Issue
Block a user