mirror of
https://github.com/genodelabs/genode.git
synced 2024-12-19 05:37:54 +00:00
Stefan Kalkowski
Norman Feske
parent
fe009fd66d
commit
cf0d007fd4
@ -1,7 +1,5 @@
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proc have_platform_drv {} {
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return [expr [have_board imx53_qsb] \
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|| [have_board imx53_qsb_tz] \
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|| [have_board pc]]
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return [expr [have_board pc]]
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}
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@ -63,9 +61,7 @@ proc append_platform_drv_build_components {} {
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}
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proc platform_drv_binary {} {
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if {[have_board imx53_qsb]} { return legacy_imx53_platform_drv }
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if {[have_board imx53_qsb_tz]} { return legacy_imx53_platform_drv }
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if {[have_board pc]} { return legacy_pc_platform_drv }
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if {[have_board pc]} { return legacy_pc_platform_drv }
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return no_platform_drv_available
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}
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@ -1,36 +0,0 @@
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/*
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* \brief i.MX53 specific platform session client side
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* \author Stefan Kalkowski <stefan.kalkowski@genode-labs.com
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* \date 2013-04-29
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*/
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/*
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* Copyright (C) 2013-2017 Genode Labs GmbH
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*
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* This file is part of the Genode OS framework, which is distributed
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* under the terms of the GNU Affero General Public License version 3.
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*/
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#ifndef _INCLUDE__LEGACY__IMX53__PLATFORM_SESSION__CLIENT_H_
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#define _INCLUDE__LEGACY__IMX53__PLATFORM_SESSION__CLIENT_H_
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#include <base/capability.h>
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#include <base/rpc_client.h>
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#include <legacy/imx53/platform_session/platform_session.h>
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namespace Platform { struct Client; }
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struct Platform::Client : Genode::Rpc_client<Session>
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{
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explicit Client(Genode::Capability<Session> session)
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: Genode::Rpc_client<Session>(session) { }
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void enable(Device dev) override { call<Rpc_enable>(dev); }
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void disable(Device dev) override { call<Rpc_disable>(dev); }
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void clock_rate(Device dev, unsigned long rate) override {
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call<Rpc_clock_rate>(dev, rate); }
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Board_revision revision() override { return call<Rpc_revision>(); }
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};
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#endif /* _INCLUDE__LEGACY__IMX53__PLATFORM_SESSION__CLIENT_H_ */
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@ -1,35 +0,0 @@
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/*
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* \brief Connection to platform service
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* \author Stefan Kalkowski
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* \date 2013-04-29
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*/
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/*
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* Copyright (C) 2013-2017 Genode Labs GmbH
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*
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* This file is part of the Genode OS framework, which is distributed
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* under the terms of the GNU Affero General Public License version 3.
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*/
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#ifndef _INCLUDE__LEGACY__IMX53__PLATFORM_SESSION__CONNECTION_H_
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#define _INCLUDE__LEGACY__IMX53__PLATFORM_SESSION__CONNECTION_H_
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#include <legacy/imx53/platform_session/client.h>
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#include <util/arg_string.h>
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#include <base/connection.h>
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namespace Platform { struct Connection; }
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struct Platform::Connection : Genode::Connection<Session>, Client
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{
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/**
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* Constructor
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*/
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Connection(Genode::Env &env)
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: Genode::Connection<Session>(env, session(env.parent(),
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"ram_quota=6K, cap_quota=%u", CAP_QUOTA)),
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Client(cap()) { }
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};
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#endif /* _INCLUDE__LEGACY__IMX53__PLATFORM_SESSION__CONNECTION_H_ */
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@ -1,67 +0,0 @@
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/*
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* \brief i.MX53 specific platform session
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* \author Stefan Kalkowski <stefan.kalkowski@genode-labs.com
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* \date 2013-04-29
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*/
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/*
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* Copyright (C) 2013-2017 Genode Labs GmbH
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*
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* This file is part of the Genode OS framework, which is distributed
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* under the terms of the GNU Affero General Public License version 3.
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*/
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#ifndef _INCLUDE__LEGACY__IMX53__PLATFORM_SESSION__PLATFORM_SESSION_H_
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#define _INCLUDE__LEGACY__IMX53__PLATFORM_SESSION__PLATFORM_SESSION_H_
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#include <base/capability.h>
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#include <base/rpc.h>
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namespace Platform { struct Session; }
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struct Platform::Session : Genode::Session
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{
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enum Device {
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IPU,
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I2C_2,
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I2C_3,
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BUTTONS,
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PWM,
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};
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enum Board_revision {
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SMD = 2, /* Freescale i.MX53 SMD Tablet */
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QSB = 3, /* Freescale i.MX53 low-cost Quickstart board */
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UNKNOWN,
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};
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/**
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* \noapi
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*/
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static const char *service_name() { return "Platform"; }
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enum { CAP_QUOTA = 2 };
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virtual ~Session() { }
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virtual void enable(Device dev) = 0;
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virtual void disable(Device dev) = 0;
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virtual void clock_rate(Device dev, unsigned long rate) = 0;
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virtual Board_revision revision() = 0;
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/*********************
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** RPC declaration **
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*********************/
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GENODE_RPC(Rpc_enable, void, enable, Device);
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GENODE_RPC(Rpc_disable, void, disable, Device);
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GENODE_RPC(Rpc_clock_rate, void, clock_rate, Device, unsigned long);
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GENODE_RPC(Rpc_revision, Board_revision, revision);
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GENODE_RPC_INTERFACE(Rpc_enable, Rpc_disable, Rpc_clock_rate,
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Rpc_revision);
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};
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#endif /* _INCLUDE__LEGACY__IMX53__PLATFORM_SESSION__PLATFORM_SESSION_H_ */
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@ -1,5 +1,4 @@
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INCLUDE_SUB_DIRS := platform_session \
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legacy/imx53/platform_session \
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legacy/x86/platform_session \
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legacy/x86/platform_device
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@ -1,3 +0,0 @@
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Device drivers needed to run interactive
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scenarios on i.MX53 Quickstart Board
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@ -1,3 +0,0 @@
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_/src/platform_drv
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_/src/imx53_qsb_drivers
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_/raw/drivers_interactive-imx53_qsb
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@ -1 +0,0 @@
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2022-01-18 adfec25dff593f5fdb159fb542b6475ab9e9f4ba
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@ -1,4 +0,0 @@
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content: drivers.config fb_drv.config
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drivers.config fb_drv.config:
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cp $(REP_DIR)/recipes/raw/drivers_interactive-imx53_qsb/$@ $@
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@ -1,55 +0,0 @@
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<config>
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<parent-provides>
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<service name="IRQ"/>
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<service name="IO_MEM"/>
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<service name="IO_PORT"/>
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<service name="ROM"/>
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<service name="PD"/>
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<service name="RM"/>
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<service name="CPU"/>
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<service name="LOG"/>
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<service name="Timer"/>
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<service name="Capture"/>
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</parent-provides>
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<default caps="60"/>
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<service name="Input">
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<default-policy> <child name="dummy_input_drv"/> </default-policy> </service>
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<start name="platform_drv" caps="200" managing_system="yes">
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<binary name="legacy_imx53_platform_drv"/>
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<resource name="RAM" quantum="3M"/>
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<provides>
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<service name="Platform"/>
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</provides>
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<route>
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<service name="IRQ"> <parent/> </service>
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<service name="IO_MEM"> <parent/> </service>
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<service name="ROM"> <parent/> </service>
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<service name="PD"> <parent/> </service>
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<service name="CPU"> <parent/> </service>
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<service name="LOG"> <parent/> </service>
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<service name="Timer"> <parent/> </service>
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</route>
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</start>
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<start name="fb_drv" caps="120">
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<binary name="imx53_fb_drv"/>
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<resource name="RAM" quantum="4M"/>
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<config width="800" height="480" display="0" buffered="true"/>
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<route>
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<service name="ROM" label="config"> <parent label="fb_drv.config"/> </service>
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<service name="Platform"> <child name="platform_drv"/> </service>
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<service name="IO_MEM"> <parent/> </service>
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<service name="ROM"> <parent/> </service>
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<service name="PD"> <parent/> </service>
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<service name="CPU"> <parent/> </service>
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<service name="LOG"> <parent/> </service>
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<service name="Timer"> <parent/> </service>
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<service name="Capture"> <parent/> </service>
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</route>
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</start>
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</config>
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@ -1 +0,0 @@
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<config buffered="yes"/>
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@ -1 +0,0 @@
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2022-01-18 9bd966603f5216a24dc0680a3d42e1b9bc85722d
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@ -1,13 +0,0 @@
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include $(GENODE_DIR)/repos/base/recipes/src/content.inc
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content: src/drivers include/gpio
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include/gpio:
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mkdir -p include
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cp -r $(REP_DIR)/include/gpio $@
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src/drivers:
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mkdir -p $@/framebuffer $@/gpio
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cp -r $(REP_DIR)/src/drivers/gpio/imx $@/gpio/
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cp -r $(REP_DIR)/src/drivers/framebuffer/imx53 $@/framebuffer/
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cp -r $(REP_DIR)/include/spec/imx53/imx_framebuffer_session $@/framebuffer/imx53/
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@ -1 +0,0 @@
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2022-01-18 49f81fada899e3f40abeed62b0db6ec4128b210a
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@ -1,8 +0,0 @@
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base
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os
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blit
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platform_session
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gpio_session
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capture_session
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input_session
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timer_session
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@ -1,76 +0,0 @@
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/*
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* \brief Frame-buffer driver for Freescale's i.MX53
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* \author Nikolay Golikov <nik@ksyslabs.org>
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* \author Stefan Kalkowski
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* \date 2012-06-21
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*/
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/*
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* Copyright (C) 2009-2017 Genode Labs GmbH
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*
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* This file is part of the Genode OS framework, which is distributed
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* under the terms of the GNU Affero General Public License version 3.
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*/
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#ifndef _DRIVERS__FRAMEBUFFER__SPEC__IMX53__DRIVER_H_
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#define _DRIVERS__FRAMEBUFFER__SPEC__IMX53__DRIVER_H_
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/* Genode includes */
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#include <drivers/defs/imx53.h>
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#include <base/attached_io_mem_dataspace.h>
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#include <io_mem_session/connection.h>
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#include <legacy/imx53/platform_session/connection.h>
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#include <util/mmio.h>
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#include <capture_session/connection.h>
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/* local includes */
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#include <ipu.h>
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namespace Framebuffer {
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using namespace Genode;
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using Area = Capture::Area;
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class Driver;
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};
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class Framebuffer::Driver
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{
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private:
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Genode::Env &_env;
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Platform::Connection _platform;
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Attached_io_mem_dataspace _ipu_mmio;
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Ipu _ipu;
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bool _disp0;
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size_t _width;
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size_t _height;
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public:
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enum Resolutions { BYTES_PER_PIXEL = 4 };
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Driver(Genode::Env &env, Genode::Xml_node config)
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: _env(env),
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_platform(_env),
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_ipu_mmio(_env, Imx53::IPU_BASE, Imx53::IPU_SIZE),
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_ipu((addr_t)_ipu_mmio.local_addr<void>()),
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_disp0(config.attribute_value<unsigned>("display", 0) == 0),
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_width(config.attribute_value<unsigned>("width", 800)),
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_height(config.attribute_value<unsigned>("height", 480)) { }
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bool init(addr_t phys_base)
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{
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/* enable IPU via platform driver */
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_platform.enable(Platform::Session::IPU);
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_ipu.init(_width, _height, _width * BYTES_PER_PIXEL,
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phys_base, _disp0);
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return true;
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}
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Area screen_size() const { return Area { _width, _height }; }
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Ipu &ipu() { return _ipu; }
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};
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#endif /* _DRIVERS__FRAMEBUFFER__SPEC__IMX53__DRIVER_H_ */
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@ -1,555 +0,0 @@
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/*
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* \brief Image Processing Unit registers
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* \author Nikolay Golikov <nik@ksyslabs.org>
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* \author Stefan Kalkowski <stefan.kalkowski@genode-labs.com>
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* \date 2012-11-10
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*/
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/*
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* Copyright (C) 2009-2017 Genode Labs GmbH
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*
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* This file is part of the Genode OS framework, which is distributed
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* under the terms of the GNU Affero General Public License version 3.
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*/
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#ifndef _DRIVERS__FRAMEBUFFER__SPEC__IMX53__IPU_H_
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#define _DRIVERS__FRAMEBUFFER__SPEC__IMX53__IPU_H_
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/* Genode includes */
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#include <util/mmio.h>
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#include <util/string.h>
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#include <base/attached_io_mem_dataspace.h>
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class Ipu : Genode::Mmio
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{
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private:
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enum { REGS_OFF = 0x6000000 };
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struct Conf : Register<0x0, 32> { };
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template<unsigned NR>
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struct Int_ctrl : Register<0x3c+(NR*4), 32> { };
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struct Srm_pri2 : Register<0xa4, 32>
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{
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struct Dp_m_srm : Bitfield<3,2> { enum { UPDATE_NOW = 1 }; };
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};
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struct Disp_gen : Register<0xc4, 32> { };
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struct Mem_rst : Register<0xdc, 32> { };
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struct Pm : Register<0xe0, 32> { };
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struct Gpr : Register<0xe4, 32> { };
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struct Ch_db_mode_sel0 : Register<0x150, 32> { };
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struct Alt_ch_trb_mode_sel0 : Register<0x178, 32> { };
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struct Cur_buf_0 : Register<0x23c, 32> { };
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struct Triple_cur_buf_1 : Register<0x25c, 32> { };
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struct Ch_buf0_rdy0 : Register<0x268, 32> { };
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struct Ch_buf1_rdy0 : Register<0x270, 32> { };
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/**************************************
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** Image DMA controller registers **
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**************************************/
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enum Idmac_channels {
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CHAN_DP_PRIMARY_MAIN = 23,
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CHAN_DP_PRIMARY_AUXI = 27,
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CHAN_DC_SYNC_FLOW = 28
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};
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struct Idmac_ch_en : Register_array<0x8004, 32, 32, 1>
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{
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struct Ch : Bitfield<0, 1> { };
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};
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struct Idmac_ch_pri_1 : Register<0x8014, 32> { };
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struct Idmac_wm_en : Register_array<0x801c, 32, 32, 1>
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{
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struct Ch : Bitfield<0, 1> { };
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};
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struct Idmac_ch_lock_en_1 : Register<0x8024, 32> { };
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/***********************************
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** Display processor registers **
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||||
***********************************/
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||||
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||||
struct Dp_com_conf : Register<0x1040000, 32> { };
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struct Dp_fg_pos_sync : Register<0x1040008, 32> { };
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struct Gr_wnd_ctl_sync : Register<0x1040004, 32> { };
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/***********************************
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** Display interface registers **
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***********************************/
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template <Genode::off_t OFF>
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struct Di
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{
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struct General : Register<OFF+0x0, 32> { };
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struct Bs_clkgen0 : Register<OFF+0x4, 32> { };
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struct Bs_clkgen1 : Register<OFF+0x8, 32> { };
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template <unsigned NR>
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struct Sync_wave_gen0 : Register<0xc+OFF+(NR*4), 32> { };
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template <unsigned NR>
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struct Sync_wave_gen1 : Register<0x30+OFF+(NR*4), 32> { };
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struct Sync_as_gen : Register<OFF+0x54, 32> { };
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template <unsigned NR>
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struct Dw_gen : Register<0x58 + OFF + (NR*4), 32> { };
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template <unsigned NR>
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struct Dw_set3 : Register<0x118 + OFF + (NR*4), 32> { };
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template <unsigned NR>
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struct Step_repeat : Register<0x148 + OFF + (NR*4), 32> { };
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struct Polarity : Register<OFF+0x164, 32> { };
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struct Scr_conf : Register<OFF+0x170, 32> { };
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};
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typedef Di<0x40000> Di0;
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typedef Di<0x48000> Di1;
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/************************************
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** Display controller registers **
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************************************/
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struct Dc_wr_ch_conf_5 : Register<0x5805c, 32> { };
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struct Dc_wr_ch_addr_5 : Register<0x58060, 32> { };
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template <unsigned NR>
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struct Dc_rl_ch_5 : Register<0x58064+(NR*4), 32> { };
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struct Dc_gen : Register<0x580d4, 32> { };
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struct Dc_disp_conf2_0 : Register<0x580e8, 32> { };
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||||
struct Dc_disp_conf2_1 : Register<0x580ec, 32> { };
|
||||
template <unsigned NR>
|
||||
struct Dc_map_conf : Register<0x58108+(NR*4), 32> { };
|
||||
template <unsigned NR>
|
||||
struct Dc_template : Register<0x1080000+(NR*4), 32> { };
|
||||
|
||||
|
||||
/***********************************************
|
||||
** Display multi FIFO controller registers **
|
||||
***********************************************/
|
||||
|
||||
struct Dmfc_wr_chan : Register<0x60004, 32> { };
|
||||
struct Dmfc_wr_chan_def : Register<0x60008, 32> { };
|
||||
struct Dmfc_dp_chan : Register<0x6000c, 32> { };
|
||||
struct Dmfc_dp_chan_def : Register<0x60010, 32> { };
|
||||
struct Dmfc_general_1 : Register<0x60014, 32> { };
|
||||
struct Dmfc_ic_ctrl : Register<0x6001c, 32> { };
|
||||
|
||||
|
||||
class Cp_mem
|
||||
{
|
||||
public:
|
||||
|
||||
enum { OFFSET = 0x1000000 };
|
||||
|
||||
struct
|
||||
{
|
||||
unsigned xv : 10; /* XV Virtual Coordinate */
|
||||
unsigned yv : 9; /* YV Virtual Coordinate */
|
||||
unsigned xb : 13; /* XB inner Block Coordinate */
|
||||
unsigned yb : 12; /* YB inner Block Coordinate */
|
||||
unsigned nsb_b : 1; /* New Sub Block */
|
||||
unsigned cf : 1; /* Current Field */
|
||||
unsigned sx : 12; /* Scroll X counter */
|
||||
unsigned sy : 11; /* Scroll Y counter */
|
||||
unsigned ns : 10; /* Number of Scroll */
|
||||
unsigned sdx : 7; /* Scroll Delta X */
|
||||
unsigned sm : 10; /* Scroll Max */
|
||||
unsigned scc : 1; /* Scrolling Configuration */
|
||||
unsigned sce : 1; /* Scrolling Enable */
|
||||
unsigned sdy : 7; /* Scroll Delta Y */
|
||||
unsigned sdrx : 1; /* Scroll Horizontal Direction */
|
||||
unsigned sdry : 1; /* Scroll Vertical Direction */
|
||||
unsigned bpp : 3; /* Bits per Pixel */
|
||||
unsigned dec_sel : 2; /* Decode Address Select */
|
||||
unsigned dim : 1; /* Access Dimension */
|
||||
unsigned so : 1; /* Scan Order */
|
||||
unsigned bndm : 3; /* Band Mode */
|
||||
unsigned bm : 2; /* Block Mode */
|
||||
unsigned rot : 1; /* Rotation */
|
||||
unsigned hf : 1; /* Horizontal Flip */
|
||||
unsigned vf : 1; /* Vertical Flip */
|
||||
unsigned the : 1; /* Threshold Enable */
|
||||
unsigned cap : 1; /* Conditional Access Polarity */
|
||||
unsigned cae : 1; /* Conditional Access Enable */
|
||||
unsigned fw : 13; /* Frame Width */
|
||||
unsigned fh : 12; /* Frame Height */
|
||||
unsigned res0 : 10; /* reserved */
|
||||
Genode::uint32_t res1[3];
|
||||
|
||||
unsigned eba0 : 29; /* Ext Mem Buffer 0 Address */
|
||||
unsigned eba1 : 29; /* Ext Mem Buffer 1 Address */
|
||||
unsigned ilo : 20; /* Interlace Offset */
|
||||
unsigned npb : 7; /* Number of Pixels in Whole Burst Access */
|
||||
unsigned pfs : 4; /* Pixel Format Select */
|
||||
unsigned alu : 1; /* Alpha Used */
|
||||
unsigned albm : 3; /* Alpha Channel Mapping */
|
||||
unsigned id : 2; /* AXI ID */
|
||||
unsigned th : 7; /* Threshold */
|
||||
unsigned sly : 14; /* Stride Line */
|
||||
unsigned wid0 : 3; /* Width0 */
|
||||
unsigned wid1 : 3; /* Width1 */
|
||||
unsigned wid2 : 3; /* Width2 */
|
||||
unsigned wid3 : 3; /* Width3 */
|
||||
unsigned off0 : 5; /* Offset0 */
|
||||
unsigned off1 : 5; /* Offset1 */
|
||||
unsigned off2 : 5; /* Offset2 */
|
||||
unsigned off3 : 5; /* Offset3 */
|
||||
unsigned sxys : 1; /* Select SX SY Set */
|
||||
unsigned cre : 1; /* Conditional Read Enable */
|
||||
unsigned dec_sel2 : 1; /* Decode Address Select bit[2] */
|
||||
unsigned res2 : 9; /* reserved */
|
||||
Genode::uint32_t res3[3];
|
||||
} __attribute__((packed));
|
||||
|
||||
Cp_mem() { Genode::memset(this, 0, sizeof(Cp_mem)); }
|
||||
} __attribute__((packed));
|
||||
|
||||
|
||||
void _init_dma_channel(unsigned channel,
|
||||
Genode::uint16_t width, Genode::uint16_t height,
|
||||
Genode::uint32_t stride, Genode::addr_t phys_base)
|
||||
{
|
||||
void *dst =(void*)(base() + Cp_mem::OFFSET + channel*sizeof(Cp_mem));
|
||||
Cp_mem cpmem;
|
||||
|
||||
cpmem.fw = width - 1;
|
||||
cpmem.fh = height - 1;
|
||||
cpmem.sly = stride - 1;
|
||||
cpmem.eba0 = phys_base >> 3;
|
||||
cpmem.eba1 = phys_base >> 3;
|
||||
cpmem.bpp = 0; /* corresponds to 32BPP */
|
||||
cpmem.pfs = 7; /* corresponds to RGB */
|
||||
cpmem.npb = 15;
|
||||
|
||||
/* red */
|
||||
cpmem.wid0 = 7;
|
||||
cpmem.off0 = 8;
|
||||
|
||||
/* green */
|
||||
cpmem.wid1 = 7;
|
||||
cpmem.off1 = 16;
|
||||
|
||||
/* blue */
|
||||
cpmem.wid2 = 7;
|
||||
cpmem.off2 = 24;
|
||||
|
||||
/* alpha */
|
||||
cpmem.wid3 = 7;
|
||||
cpmem.off3 = 0;
|
||||
|
||||
Genode::memcpy(dst, (void*)&cpmem, sizeof(Cp_mem));
|
||||
}
|
||||
|
||||
|
||||
void _init_di0(Genode::uint16_t width, Genode::uint16_t height,
|
||||
Genode::uint32_t stride, Genode::addr_t phys_base)
|
||||
{
|
||||
/* set MCU_T to divide MCU access window into 2 */
|
||||
write<Disp_gen>(0x1600000); // ?= 0x600000
|
||||
|
||||
/* link display controller events */
|
||||
write<Dc_rl_ch_5<0> >(0x5030000);
|
||||
write<Dc_rl_ch_5<2> >(0x602);
|
||||
write<Dc_rl_ch_5<4> >(0x701);
|
||||
write<Dc_rl_ch_5<0> >(0x5030000);
|
||||
write<Dc_rl_ch_5<1> >(0x0);
|
||||
write<Dc_rl_ch_5<1> >(0x0);
|
||||
write<Dc_rl_ch_5<2> >(0x602);
|
||||
write<Dc_rl_ch_5<3> >(0x0);
|
||||
write<Dc_rl_ch_5<3> >(0x0);
|
||||
|
||||
write<Dc_wr_ch_conf_5>(0x2);
|
||||
write<Dc_wr_ch_addr_5>(0x0);
|
||||
|
||||
write<Dc_gen>(0x84);
|
||||
|
||||
|
||||
/*************************
|
||||
** Display interface **
|
||||
*************************/
|
||||
|
||||
/* clear DI */
|
||||
write<Di0::General>(0x200000);
|
||||
|
||||
/* initialize display interface 0 */
|
||||
write<Di0::Bs_clkgen0>(0x38);
|
||||
write<Di0::Bs_clkgen1>(0x30000);
|
||||
write<Di0::Dw_gen<0> >(0x2020300);
|
||||
write<Di0::Dw_set3<0> >(0x60000);
|
||||
write<Di0::Sync_wave_gen0<0> >(0x21310000);
|
||||
write<Di0::Sync_wave_gen1<0> >(0x10000000);
|
||||
write<Di0::Sync_wave_gen0<1> >(0x21310001);
|
||||
write<Di0::Sync_wave_gen1<1> >(0x30141000);
|
||||
write<Di0::Step_repeat<0> >(0x0);
|
||||
write<Di0::Sync_wave_gen0<2> >(0x10520000);
|
||||
write<Di0::Sync_wave_gen1<2> >(0x30142000);
|
||||
write<Di0::Scr_conf>(0x20a);
|
||||
write<Di0::Sync_wave_gen0<3> >(0x3010b);
|
||||
write<Di0::Sync_wave_gen1<3> >(0x8000000);
|
||||
write<Di0::Step_repeat<1> >(0x1e00000);
|
||||
write<Di0::Sync_wave_gen0<4> >(0x10319);
|
||||
write<Di0::Sync_wave_gen1<4> >(0xa000000);
|
||||
write<Di0::Sync_wave_gen0<5> >(0x0);
|
||||
write<Di0::Sync_wave_gen1<5> >(0x0);
|
||||
write<Di0::Sync_wave_gen0<6> >(0x0);
|
||||
write<Di0::Sync_wave_gen1<6> >(0x0);
|
||||
write<Di0::Sync_wave_gen0<7> >(0x0);
|
||||
write<Di0::Sync_wave_gen1<7> >(0x0);
|
||||
write<Di0::Sync_wave_gen0<8> >(0x0);
|
||||
write<Di0::Sync_wave_gen1<8> >(0x0);
|
||||
write<Di0::Step_repeat<2> >(0x320);
|
||||
write<Di0::Step_repeat<3> >(0x0);
|
||||
write<Di0::Step_repeat<4> >(0x0);
|
||||
|
||||
/* write display connection microcode */
|
||||
write<Dc_template<10> >(0x8885);
|
||||
write<Dc_template<11> >(0x380);
|
||||
write<Dc_template<12> >(0x8845);
|
||||
write<Dc_template<13> >(0x380);
|
||||
write<Dc_template<14> >(0x8805);
|
||||
write<Dc_template<15> >(0x380);
|
||||
|
||||
write<Di0::General>(0x220000);
|
||||
write<Di0::Sync_as_gen>(0x2002);
|
||||
write<Di0::General>(0x200000);
|
||||
write<Di0::Sync_as_gen>(0x4002);
|
||||
|
||||
write<Di0::Polarity>(0x10);
|
||||
write<Dc_disp_conf2_0>(0x320);
|
||||
|
||||
/* init IDMAC channels */
|
||||
_init_dma_channel(CHAN_DP_PRIMARY_MAIN, width, height, stride, phys_base);
|
||||
_init_dma_channel(CHAN_DP_PRIMARY_AUXI, width, height, stride, phys_base);
|
||||
|
||||
/* round robin for simultaneous synchronous flows from DC & DP */
|
||||
write<Dmfc_general_1>(0x3);
|
||||
|
||||
/* enable DP, DI0, DC, DMFC */
|
||||
write<Conf>(0x660);
|
||||
|
||||
/* use double buffer for main DMA channel */
|
||||
write<Ch_db_mode_sel0>(1 << CHAN_DP_PRIMARY_MAIN |
|
||||
1 << CHAN_DP_PRIMARY_AUXI);
|
||||
|
||||
/* buffer used by DMA channel is buffer 1 */
|
||||
write<Cur_buf_0>(1 << CHAN_DP_PRIMARY_MAIN);
|
||||
|
||||
write<Dc_wr_ch_conf_5>(0x82);
|
||||
|
||||
/* Enable IDMAC channels */
|
||||
write<Idmac_ch_en::Ch>(1, CHAN_DP_PRIMARY_MAIN);
|
||||
write<Idmac_ch_en::Ch>(1, CHAN_DP_PRIMARY_AUXI);
|
||||
}
|
||||
|
||||
void _init_di1(Genode::uint16_t width, Genode::uint16_t height,
|
||||
Genode::uint32_t stride, Genode::addr_t phys_base)
|
||||
{
|
||||
write<Disp_gen>(0x600000); //write<Disp_gen>(0x2400000);
|
||||
|
||||
write<Dp_com_conf>(0);
|
||||
write<Srm_pri2::Dp_m_srm>(Srm_pri2::Dp_m_srm::UPDATE_NOW);
|
||||
|
||||
write<Dc_rl_ch_5<0> >(0x2030000);
|
||||
write<Dc_rl_ch_5<1> >(0);
|
||||
write<Dc_rl_ch_5<2> >(0x302);
|
||||
write<Dc_rl_ch_5<3> >(0);
|
||||
write<Dc_rl_ch_5<4> >(0x401);
|
||||
write<Dc_wr_ch_conf_5>(0xe);
|
||||
write<Dc_wr_ch_addr_5>(0x0);
|
||||
write<Dc_gen>(0x84);
|
||||
|
||||
write<Conf>(0);
|
||||
|
||||
write<Di1::General>(0x200000);
|
||||
write<Di1::General>(0x300000);
|
||||
|
||||
write<Di1::Bs_clkgen0>(0x10);
|
||||
write<Di1::Bs_clkgen1>(0x10000);
|
||||
|
||||
write<Pm>(0x10101010);
|
||||
|
||||
write<Di1::Dw_gen<0> >(0x300);
|
||||
write<Di1::Dw_set3<0> >(0x20000);
|
||||
write<Di1::Sync_wave_gen0<0> >(0x29f90000);
|
||||
write<Di1::Sync_wave_gen1<0> >(0x10000000);
|
||||
write<Di1::Step_repeat<0> >(0x0);
|
||||
write<Di1::Sync_wave_gen0<1> >(0x29f90001);
|
||||
write<Di1::Sync_wave_gen1<1> >(0x30781000);
|
||||
write<Di1::Step_repeat<0> >(0x0);
|
||||
write<Di1::Sync_wave_gen0<2> >(0x192a0000);
|
||||
write<Di1::Sync_wave_gen1<2> >(0x30142000);
|
||||
write<Di1::Step_repeat<1> >(0x3000000);
|
||||
write<Di1::Scr_conf>(0x325);
|
||||
write<Di1::Sync_wave_gen0<3> >(0x300fb);
|
||||
write<Di1::Sync_wave_gen1<3> >(0x8000000);
|
||||
write<Di1::Step_repeat<1> >(0x3000000);
|
||||
write<Di1::Sync_wave_gen0<4> >(0x108c1);
|
||||
write<Di1::Sync_wave_gen1<4> >(0xa000000);
|
||||
write<Di1::Step_repeat<2> >(0x400);
|
||||
write<Di1::Sync_wave_gen0<6> >(0x29f90091);
|
||||
write<Di1::Sync_wave_gen1<6> >(0x30781000);
|
||||
write<Di1::Step_repeat<3> >(0x0);
|
||||
write<Di1::Sync_wave_gen0<7> >(0x192a000a);
|
||||
write<Di1::Sync_wave_gen1<7> >(0x30142000);
|
||||
write<Di1::Step_repeat<3> >(0x0);
|
||||
write<Di1::Sync_wave_gen0<5> >(0x0);
|
||||
write<Di1::Sync_wave_gen1<5> >(0x0);
|
||||
write<Di1::Sync_wave_gen0<8> >(0x0);
|
||||
write<Di1::Sync_wave_gen1<8> >(0x0);
|
||||
write<Di1::Step_repeat<4> >(0x0);
|
||||
write<Di1::Step_repeat<2> >(0x400);
|
||||
|
||||
write<Di1::Sync_wave_gen0<5> >(0x90011);
|
||||
write<Di1::Sync_wave_gen1<5> >(0x4000000);
|
||||
write<Di1::Step_repeat<2> >(0x28a0400);
|
||||
|
||||
write<Dc_template<4> >(0x10885);
|
||||
write<Dc_template<5> >(0x380);
|
||||
write<Dc_template<6> >(0x845);
|
||||
write<Dc_template<7> >(0x280);
|
||||
write<Dc_template<8> >(0x10805);
|
||||
write<Dc_template<9> >(0x380);
|
||||
|
||||
write<Di1::General>(0x6300000);
|
||||
write<Di1::Sync_as_gen>(0x4000);
|
||||
|
||||
write<Di1::Polarity>(0x10);
|
||||
write<Dc_disp_conf2_1>(0x400);
|
||||
|
||||
_init_dma_channel(CHAN_DP_PRIMARY_MAIN, width, height, stride, phys_base);
|
||||
_init_dma_channel(CHAN_DP_PRIMARY_AUXI, width, height, stride, phys_base);
|
||||
|
||||
/* use double buffer for main DMA channel */
|
||||
write<Ch_db_mode_sel0>(1 << CHAN_DP_PRIMARY_MAIN |
|
||||
1 << CHAN_DP_PRIMARY_AUXI);
|
||||
|
||||
/* buffer used by DMA channel is buffer 1 */
|
||||
write<Cur_buf_0>(1 << CHAN_DP_PRIMARY_MAIN);
|
||||
|
||||
write<Conf>(0x6a0);
|
||||
|
||||
/* Enable IDMAC channels */
|
||||
write<Idmac_ch_en::Ch>(1, CHAN_DP_PRIMARY_MAIN);
|
||||
write<Idmac_ch_en::Ch>(1, CHAN_DP_PRIMARY_AUXI);
|
||||
|
||||
write<Idmac_wm_en>(1 << CHAN_DP_PRIMARY_MAIN |
|
||||
1 << CHAN_DP_PRIMARY_AUXI);
|
||||
|
||||
write<Dc_wr_ch_conf_5>(0x8e);
|
||||
|
||||
write<Disp_gen>(0x2600000);
|
||||
}
|
||||
|
||||
public:
|
||||
|
||||
/**
|
||||
* IPU initialization
|
||||
*/
|
||||
void init(Genode::uint16_t width, Genode::uint16_t height,
|
||||
Genode::uint32_t stride, Genode::addr_t phys_base,
|
||||
bool di0)
|
||||
{
|
||||
/* stop pixel clocks */
|
||||
write<Di0::General>(0);
|
||||
write<Di1::General>(0);
|
||||
|
||||
/* reset IPU memory buffers */
|
||||
write<Mem_rst>(0x807fffff);
|
||||
while (read<Mem_rst>() & 0x80000000) ;
|
||||
|
||||
/* initialize pixel format mappings for display controller */
|
||||
write<Dc_map_conf< 0> >(0x14830820);
|
||||
write<Dc_map_conf< 1> >(0x2d4920e6);
|
||||
write<Dc_map_conf< 2> >(0x39ac);
|
||||
write<Dc_map_conf<15> >(0xfff07ff);
|
||||
write<Dc_map_conf<16> >(0x5fc17ff);
|
||||
write<Dc_map_conf<17> >(0x11fc0bfc);
|
||||
write<Dc_map_conf<18> >(0x17ff0fff);
|
||||
write<Dc_map_conf<19> >(0x4f807ff);
|
||||
write<Dc_map_conf<20> >(0xff80afc);
|
||||
write<Dc_map_conf<21> >(0xdfc05fc);
|
||||
write<Dc_map_conf<22> >(0x15fc);
|
||||
|
||||
/* clear interrupt control registers */
|
||||
write<Int_ctrl<4> >(0);
|
||||
write<Int_ctrl<5> >(0);
|
||||
write<Int_ctrl<8> >(0);
|
||||
write<Int_ctrl<9> >(0);
|
||||
|
||||
/* disable DMFC channel from image converter */
|
||||
write<Dmfc_ic_ctrl>(0x2);
|
||||
|
||||
/* set DMFC FIFO for idma channels */
|
||||
write<Dmfc_wr_chan>(0x90); /* channel CHAN_DC_SYNC_FLOW */
|
||||
write<Dmfc_wr_chan_def>(0x202020f6);
|
||||
write<Dmfc_dp_chan>(0x968a); /* channels CHAN_DP_PRIMARY_XXX */
|
||||
write<Dmfc_dp_chan_def>(0x2020f6f6);
|
||||
write<Dmfc_general_1>(0x3);
|
||||
|
||||
/* set idma channels 23, 27, 28 as high priority */
|
||||
write<Idmac_ch_pri_1>(1 << CHAN_DP_PRIMARY_MAIN |
|
||||
1 << CHAN_DP_PRIMARY_AUXI |
|
||||
1 << CHAN_DC_SYNC_FLOW);
|
||||
|
||||
/*
|
||||
* generate 8 AXI bursts upon the assertion of DMA request
|
||||
* for our channels
|
||||
*/
|
||||
write<Idmac_ch_lock_en_1>(0x3f0000);
|
||||
|
||||
if (di0)
|
||||
_init_di0(width, height, stride, phys_base);
|
||||
else
|
||||
_init_di1(width, height, stride, phys_base);
|
||||
|
||||
|
||||
/************************
|
||||
** overlay settings **
|
||||
************************/
|
||||
|
||||
write<Dp_com_conf>(1 << 0);
|
||||
write<Srm_pri2::Dp_m_srm>(Srm_pri2::Dp_m_srm::UPDATE_NOW);
|
||||
|
||||
write<Dp_fg_pos_sync>(16);
|
||||
write<Srm_pri2::Dp_m_srm>(Srm_pri2::Dp_m_srm::UPDATE_NOW);
|
||||
|
||||
write<Dp_com_conf>(1 << 0 | 1 << 2);
|
||||
write<Srm_pri2::Dp_m_srm>(Srm_pri2::Dp_m_srm::UPDATE_NOW);
|
||||
|
||||
write<Gr_wnd_ctl_sync>(0xff000000);
|
||||
write<Srm_pri2::Dp_m_srm>(Srm_pri2::Dp_m_srm::UPDATE_NOW);
|
||||
}
|
||||
|
||||
|
||||
void overlay(Genode::addr_t phys_base, int x, int y, int alpha)
|
||||
{
|
||||
volatile Genode::uint32_t *ptr = (volatile Genode::uint32_t*)
|
||||
(base() + Cp_mem::OFFSET + CHAN_DP_PRIMARY_AUXI*sizeof(Cp_mem));
|
||||
ptr[8] = (((phys_base >> 3) & 0b111) << 29) | (phys_base >> 3);
|
||||
ptr[9] = (phys_base >> 6);
|
||||
|
||||
write<Dp_fg_pos_sync>(x << 16 | y);
|
||||
write<Srm_pri2::Dp_m_srm>(Srm_pri2::Dp_m_srm::UPDATE_NOW);
|
||||
|
||||
write<Gr_wnd_ctl_sync>(alpha << 24);
|
||||
write<Srm_pri2::Dp_m_srm>(Srm_pri2::Dp_m_srm::UPDATE_NOW);
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
* Constructor
|
||||
*
|
||||
* \param mmio_base base address of IPU
|
||||
*/
|
||||
Ipu(Genode::addr_t mmio_base) : Genode::Mmio(mmio_base + REGS_OFF) { }
|
||||
};
|
||||
|
||||
#endif /* _DRIVERS__FRAMEBUFFER__SPEC__IMX53__IPU_H_ */
|
||||
@ -1,79 +0,0 @@
|
||||
/*
|
||||
* \brief Frame-buffer driver for the i.MX53
|
||||
* \author Nikolay Golikov <nik@ksyslabs.org>
|
||||
* \author Stefan Kalkowski <stefan.kalkowski@genode-labs.com>
|
||||
* \author Norman Feske
|
||||
* \date 2012-06-21
|
||||
*/
|
||||
|
||||
/*
|
||||
* Copyright (C) 2012-2020 Genode Labs GmbH
|
||||
*
|
||||
* This file is part of the Genode OS framework, which is distributed
|
||||
* under the terms of the GNU Affero General Public License version 3.
|
||||
*/
|
||||
|
||||
/* Genode includes */
|
||||
#include <base/attached_rom_dataspace.h>
|
||||
#include <base/attached_ram_dataspace.h>
|
||||
#include <base/component.h>
|
||||
#include <base/log.h>
|
||||
#include <timer_session/connection.h>
|
||||
#include <dataspace/client.h>
|
||||
|
||||
/* local includes */
|
||||
#include <driver.h>
|
||||
|
||||
namespace Framebuffer {
|
||||
using namespace Genode;
|
||||
struct Main;
|
||||
};
|
||||
|
||||
|
||||
struct Framebuffer::Main
|
||||
{
|
||||
using Pixel = Capture::Pixel;
|
||||
|
||||
Env &_env;
|
||||
|
||||
Attached_rom_dataspace _config { _env, "config" };
|
||||
|
||||
Driver _driver { _env, _config.xml() };
|
||||
|
||||
Area const _size = _driver.screen_size();
|
||||
|
||||
Attached_ram_dataspace _fb_ds { _env.ram(), _env.rm(),
|
||||
_size.count()*sizeof(Pixel), WRITE_COMBINED };
|
||||
|
||||
Capture::Connection _capture { _env };
|
||||
|
||||
Capture::Connection::Screen _captured_screen { _capture, _env.rm(), _size };
|
||||
|
||||
Timer::Connection _timer { _env };
|
||||
|
||||
Signal_handler<Main> _timer_handler { _env.ep(), *this, &Main::_handle_timer };
|
||||
|
||||
void _handle_timer()
|
||||
{
|
||||
Surface<Pixel> surface(_fb_ds.local_addr<Pixel>(), _size);
|
||||
|
||||
_captured_screen.apply_to_surface(surface);
|
||||
}
|
||||
|
||||
Main(Env &env) : _env(env)
|
||||
{
|
||||
log("--- i.MX53 framebuffer driver ---");
|
||||
|
||||
if (!_driver.init(Dataspace_client(_fb_ds.cap()).phys_addr())) {
|
||||
error("could not initialize display");
|
||||
struct Could_not_initialize_display : Exception { };
|
||||
throw Could_not_initialize_display();
|
||||
}
|
||||
|
||||
_timer.sigh(_timer_handler);
|
||||
_timer.trigger_periodic(10*1000);
|
||||
}
|
||||
};
|
||||
|
||||
|
||||
void Component::construct(Genode::Env &env) { static Framebuffer::Main main(env); }
|
||||
@ -1,36 +0,0 @@
|
||||
/*
|
||||
* \brief Pulse width modulation
|
||||
* \author Stefan Kalkowski
|
||||
* \date 2013-03-05
|
||||
*/
|
||||
|
||||
/*
|
||||
* Copyright (C) 2013-2017 Genode Labs GmbH
|
||||
*
|
||||
* This file is part of the Genode OS framework, which is distributed
|
||||
* under the terms of the GNU Affero General Public License version 3.
|
||||
*/
|
||||
|
||||
#ifndef _DRIVERS__FRAMEBUFFER__SPEC__IMX53__PWM_H_
|
||||
#define _DRIVERS__FRAMEBUFFER__SPEC__IMX53__PWM_H_
|
||||
|
||||
/* Genode includes */
|
||||
#include <util/mmio.h>
|
||||
|
||||
struct Pwm : Genode::Mmio
|
||||
{
|
||||
struct Control : Register<0x0, 32> {};
|
||||
struct Sample : Register<0xc, 32> {};
|
||||
struct Period : Register<0x10,32> {};
|
||||
|
||||
Pwm(Genode::addr_t const mmio_base) : Genode::Mmio(mmio_base) { }
|
||||
|
||||
void enable_display()
|
||||
{
|
||||
write<Period>(0x64);
|
||||
write<Sample>(0x64);
|
||||
write<Control>(0x3c20001);
|
||||
}
|
||||
};
|
||||
|
||||
#endif /* _DRIVERS__FRAMEBUFFER__SPEC__IMX53__PWM_H_ */
|
||||
@ -1,8 +0,0 @@
|
||||
TARGET = imx53_fb_drv
|
||||
REQUIRES = arm_v7
|
||||
SRC_CC = main.cc
|
||||
LIBS = base blit
|
||||
INC_DIR += $(PRG_DIR)
|
||||
INC_DIR += $(call select_from_repositories,include/spec/imx53)
|
||||
|
||||
CC_CXX_WARN_STRICT_CONVERSION =
|
||||
@ -1,94 +0,0 @@
|
||||
/*
|
||||
* \brief Clock control module register description
|
||||
* \author Nikolay Golikov <nik@ksyslabs.org>
|
||||
* \author Stefan Kalkowski <stefan.kalkowski@genode-labs.com>
|
||||
* \date 2013-04-29
|
||||
*/
|
||||
|
||||
/*
|
||||
* Copyright (C) 2013-2017 Genode Labs GmbH
|
||||
*
|
||||
* This file is part of the Genode OS framework, which is distributed
|
||||
* under the terms of the GNU Affero General Public License version 3.
|
||||
*/
|
||||
|
||||
#ifndef _DRIVERS__PLATFORM__SPEC__IMX53__CCM_H_
|
||||
#define _DRIVERS__PLATFORM__SPEC__IMX53__CCM_H_
|
||||
|
||||
/* Genode includes */
|
||||
#include <util/mmio.h>
|
||||
#include <drivers/defs/imx53.h>
|
||||
#include <base/attached_io_mem_dataspace.h>
|
||||
|
||||
class Ccm : public Genode::Attached_io_mem_dataspace,
|
||||
Genode::Mmio
|
||||
{
|
||||
private:
|
||||
|
||||
/**
|
||||
* Control divider register
|
||||
*/
|
||||
struct Ccdr : Register<0x4, 32>
|
||||
{
|
||||
struct Ipu_hs_mask : Bitfield <21, 1> { };
|
||||
};
|
||||
|
||||
/**
|
||||
* Serial Clock Multiplexer Register 2
|
||||
*/
|
||||
struct Cscmr2 : Register<0x20, 32> {};
|
||||
|
||||
/**
|
||||
* D1 Clock Divider Register
|
||||
*/
|
||||
struct Cdcdr : Register<0x30, 32> {};
|
||||
|
||||
/**
|
||||
* Low power control register
|
||||
*/
|
||||
struct Clpcr : Register<0x54, 32>
|
||||
{
|
||||
struct Bypass_ipu_hs : Bitfield<18, 1> { };
|
||||
};
|
||||
|
||||
struct Ccgr1 : Register<0x6c, 32>
|
||||
{
|
||||
struct I2c_1 : Bitfield<18, 2> { };
|
||||
struct I2c_2 : Bitfield<20, 2> { };
|
||||
struct I2c_3 : Bitfield<22, 2> { };
|
||||
};
|
||||
|
||||
struct Ccgr5 : Register<0x7c, 32>
|
||||
{
|
||||
struct Ipu : Bitfield<10, 2> { };
|
||||
};
|
||||
|
||||
public:
|
||||
|
||||
Ccm(Genode::Env &env)
|
||||
: Genode::Attached_io_mem_dataspace(env, Imx53::CCM_BASE,
|
||||
Imx53::CCM_SIZE),
|
||||
Genode::Mmio((Genode::addr_t)local_addr<void>()) { }
|
||||
|
||||
void i2c_1_enable(void) { write<Ccgr1::I2c_1>(3); }
|
||||
void i2c_2_enable(void) { write<Ccgr1::I2c_2>(3); }
|
||||
void i2c_3_enable(void) { write<Ccgr1::I2c_3>(3); }
|
||||
|
||||
void ipu_clk_enable(void)
|
||||
{
|
||||
write<Ccgr5::Ipu>(3);
|
||||
write<Ccdr::Ipu_hs_mask>(0);
|
||||
write<Clpcr::Bypass_ipu_hs>(0);
|
||||
write<Cscmr2>(0xa2b32f0b);
|
||||
write<Cdcdr>(0x14370092);
|
||||
}
|
||||
|
||||
void ipu_clk_disable(void)
|
||||
{
|
||||
write<Ccgr5::Ipu>(0);
|
||||
write<Ccdr::Ipu_hs_mask>(1);
|
||||
write<Clpcr::Bypass_ipu_hs>(1);
|
||||
}
|
||||
};
|
||||
|
||||
#endif /* _DRIVERS__PLATFORM__SPEC__IMX53__CCM_H_ */
|
||||
@ -1,39 +0,0 @@
|
||||
/*
|
||||
* \brief IC identification module register description
|
||||
* \author Stefan Kalkowski <stefan.kalkowski@genode-labs.com>
|
||||
* \date 2013-04-29
|
||||
*/
|
||||
|
||||
/*
|
||||
* Copyright (C) 2013-2017 Genode Labs GmbH
|
||||
*
|
||||
* This file is part of the Genode OS framework, which is distributed
|
||||
* under the terms of the GNU Affero General Public License version 3.
|
||||
*/
|
||||
|
||||
#ifndef _DRIVERS__PLATFORM__SPEC__IMX53__IIM_H_
|
||||
#define _DRIVERS__PLATFORM__SPEC__IMX53__IIM_H_
|
||||
|
||||
/* Genode includes */
|
||||
#include <util/mmio.h>
|
||||
#include <drivers/defs/imx53.h>
|
||||
#include <base/attached_io_mem_dataspace.h>
|
||||
|
||||
class Iim : public Genode::Attached_io_mem_dataspace,
|
||||
Genode::Mmio
|
||||
{
|
||||
private:
|
||||
|
||||
struct Fuse_bank0_gp6 : Register<0x878, 32> {};
|
||||
|
||||
public:
|
||||
|
||||
Iim(Genode::Env &env)
|
||||
: Genode::Attached_io_mem_dataspace(env, Imx53::IIM_BASE,
|
||||
Imx53::IIM_SIZE),
|
||||
Genode::Mmio((Genode::addr_t)local_addr<void>()) {}
|
||||
|
||||
unsigned long revision() { return read<Fuse_bank0_gp6>() & 0xf; }
|
||||
};
|
||||
|
||||
#endif /* _DRIVERS__PLATFORM__SPEC__IMX53__IIM_H_ */
|
||||
@ -1,110 +0,0 @@
|
||||
/*
|
||||
* \brief IOMUX controller register description
|
||||
* \author Stefan Kalkowski <stefan.kalkowski@genode-labs.com>
|
||||
* \date 2013-04-29
|
||||
*/
|
||||
|
||||
/*
|
||||
* Copyright (C) 2013-2017 Genode Labs GmbH
|
||||
*
|
||||
* This file is part of the Genode OS framework, which is distributed
|
||||
* under the terms of the GNU Affero General Public License version 3.
|
||||
*/
|
||||
|
||||
#ifndef _DRIVERS__PLATFORM__SPEC__IMX53__IOMUX_H_
|
||||
#define _DRIVERS__PLATFORM__SPEC__IMX53__IOMUX_H_
|
||||
|
||||
/* Genode includes */
|
||||
#include <util/mmio.h>
|
||||
#include <drivers/defs/imx53.h>
|
||||
#include <base/attached_io_mem_dataspace.h>
|
||||
|
||||
class Iomux : public Genode::Attached_io_mem_dataspace,
|
||||
Genode::Mmio
|
||||
{
|
||||
private:
|
||||
|
||||
struct Gpr2 : Register<0x8,32>
|
||||
{
|
||||
struct Ch1_mode : Bitfield<2, 2> {
|
||||
enum { ROUTED_TO_DI1 = 0x3 }; };
|
||||
struct Data_width_ch1 : Bitfield<7, 1> {
|
||||
enum { PX_18_BITS, PX_24_BITS }; };
|
||||
struct Bit_mapping_ch1 : Bitfield<8, 1> {
|
||||
enum { SPWG, JEIDA }; };
|
||||
struct Di1_vs_polarity : Bitfield<10,1> { };
|
||||
};
|
||||
|
||||
struct Key_col3 : Register<0x3c, 32> {};
|
||||
struct Key_row3 : Register<0x40, 32> {};
|
||||
|
||||
struct Eim_a24 : Register<0x15c, 32> { };
|
||||
|
||||
template <unsigned OFF>
|
||||
struct Sw_mux_ctl_pad_gpio : Register<0x314 + OFF*4, 32> { };
|
||||
|
||||
struct Sw_pad_ctl_pad_key_col3 : Register<0x364, 32> { };
|
||||
struct Sw_pad_ctl_pad_key_row3 : Register<0x368, 32> { };
|
||||
|
||||
struct Sw_pad_ctl_pad_eim_a24 : Register<0x4a8, 32> { };
|
||||
|
||||
template <unsigned OFF>
|
||||
struct Sw_pad_ctl_pad_gpio : Register<0x6a4 + OFF*4, 32> { };
|
||||
|
||||
struct I2c2_ipp_scl_in_select_input : Register<0x81c, 32> { };
|
||||
struct I2c2_ipp_sda_in_select_input : Register<0x820, 32> { };
|
||||
struct I2c3_ipp_scl_in_select_input : Register<0x824, 32> { };
|
||||
struct I2c3_ipp_sda_in_select_input : Register<0x828, 32> { };
|
||||
|
||||
public:
|
||||
|
||||
Iomux(Genode::Env &env)
|
||||
: Genode::Attached_io_mem_dataspace(env, Imx53::IOMUXC_BASE,
|
||||
Imx53::IOMUXC_SIZE),
|
||||
Genode::Mmio((Genode::addr_t)local_addr<void>())
|
||||
{ }
|
||||
|
||||
void i2c_2_enable()
|
||||
{
|
||||
write<Key_col3>(0x14);
|
||||
write<I2c2_ipp_scl_in_select_input>(0);
|
||||
write<Sw_pad_ctl_pad_key_col3>(0x12d);
|
||||
write<Key_row3>(0x14);
|
||||
write<I2c2_ipp_sda_in_select_input>(0);
|
||||
write<Sw_pad_ctl_pad_key_row3>(0x12d);
|
||||
}
|
||||
|
||||
void i2c_3_enable()
|
||||
{
|
||||
write<Sw_mux_ctl_pad_gpio<3> >(0x12);
|
||||
write<I2c3_ipp_scl_in_select_input>(0x1);
|
||||
write<Sw_pad_ctl_pad_gpio<3> >(0x12d);
|
||||
write<Sw_mux_ctl_pad_gpio<4> >(0x12);
|
||||
write<I2c3_ipp_sda_in_select_input>(0x1);
|
||||
write<Sw_pad_ctl_pad_gpio<4> >(0x12d);
|
||||
}
|
||||
|
||||
void ipu_enable()
|
||||
{
|
||||
write<Gpr2::Di1_vs_polarity>(1);
|
||||
write<Gpr2::Data_width_ch1>(Gpr2::Data_width_ch1::PX_18_BITS);
|
||||
write<Gpr2::Bit_mapping_ch1>(Gpr2::Bit_mapping_ch1::SPWG);
|
||||
write<Gpr2::Ch1_mode>(Gpr2::Ch1_mode::ROUTED_TO_DI1);
|
||||
}
|
||||
|
||||
void pwm_enable()
|
||||
{
|
||||
write<Eim_a24>(1);
|
||||
write<Sw_pad_ctl_pad_eim_a24>(0);
|
||||
write<Sw_mux_ctl_pad_gpio<1> >(0x4);
|
||||
write<Sw_pad_ctl_pad_gpio<1> >(0x0);
|
||||
}
|
||||
|
||||
void buttons_enable()
|
||||
{
|
||||
write<Eim_a24>(1);
|
||||
write<Sw_pad_ctl_pad_eim_a24>(0);
|
||||
}
|
||||
};
|
||||
|
||||
#endif /* _DRIVERS__PLATFORM__SPEC__IMX53__IOMUX_H_ */
|
||||
@ -1,152 +0,0 @@
|
||||
/*
|
||||
* \brief Driver for i.MX53 specific platform devices (clocks, power, etc.)
|
||||
* \author Stefan Kalkowski <stefan.kalkowski@genode-labs.com>
|
||||
* \date 2013-04-29
|
||||
*/
|
||||
|
||||
/*
|
||||
* Copyright (C) 2013-2017 Genode Labs GmbH
|
||||
*
|
||||
* This file is part of the Genode OS framework, which is distributed
|
||||
* under the terms of the GNU Affero General Public License version 3.
|
||||
*/
|
||||
|
||||
#include <base/log.h>
|
||||
#include <base/heap.h>
|
||||
#include <base/component.h>
|
||||
#include <root/component.h>
|
||||
#include <legacy/imx53/platform_session/platform_session.h>
|
||||
|
||||
#include <ccm.h>
|
||||
#include <iim.h>
|
||||
#include <iomux.h>
|
||||
#include <src.h>
|
||||
|
||||
|
||||
namespace Platform {
|
||||
class Session_component;
|
||||
class Root;
|
||||
}
|
||||
|
||||
|
||||
class Platform::Session_component : public Genode::Rpc_object<Platform::Session>
|
||||
{
|
||||
private:
|
||||
|
||||
Iim &_iim; /* IC identification module */
|
||||
Iomux &_iomux; /* I/O multiplexer device */
|
||||
Ccm &_ccm; /* clock control module */
|
||||
Src &_src; /* system reset controller */
|
||||
|
||||
public:
|
||||
|
||||
/**
|
||||
* Constructor
|
||||
*/
|
||||
Session_component(Iim &iim, Iomux &iomux, Ccm &ccm, Src &src)
|
||||
: _iim(iim), _iomux(iomux), _ccm(ccm), _src(src) {}
|
||||
|
||||
|
||||
/**********************************
|
||||
** Platform session interface **
|
||||
**********************************/
|
||||
|
||||
void enable(Device dev) override
|
||||
{
|
||||
switch (dev) {
|
||||
case Session::IPU:
|
||||
_src.reset_ipu();
|
||||
_ccm.ipu_clk_enable();
|
||||
_iomux.ipu_enable();
|
||||
break;
|
||||
case Session::I2C_2:
|
||||
_ccm.i2c_2_enable();
|
||||
_iomux.i2c_2_enable();
|
||||
break;
|
||||
case Session::I2C_3:
|
||||
_ccm.i2c_3_enable();
|
||||
_iomux.i2c_3_enable();
|
||||
break;
|
||||
case Session::BUTTONS:
|
||||
_iomux.buttons_enable();
|
||||
break;
|
||||
case Session::PWM:
|
||||
_iomux.pwm_enable();
|
||||
break;
|
||||
default:
|
||||
Genode::warning("invalid device");
|
||||
};
|
||||
}
|
||||
|
||||
void disable(Device dev) override
|
||||
{
|
||||
switch (dev) {
|
||||
case Session::IPU:
|
||||
_ccm.ipu_clk_disable();
|
||||
break;
|
||||
default:
|
||||
Genode::warning("invalid device");
|
||||
};
|
||||
}
|
||||
|
||||
void clock_rate(Device dev, unsigned long /* rate */) override
|
||||
{
|
||||
switch (dev) {
|
||||
default:
|
||||
Genode::warning("invalid device");
|
||||
};
|
||||
}
|
||||
|
||||
Board_revision revision() override
|
||||
{
|
||||
switch (_iim.revision()) {
|
||||
case QSB: return QSB;
|
||||
case SMD: return SMD;
|
||||
};
|
||||
return UNKNOWN;
|
||||
}
|
||||
};
|
||||
|
||||
|
||||
class Platform::Root : public Genode::Root_component<Platform::Session_component>
|
||||
{
|
||||
private:
|
||||
|
||||
Genode::Env &_env;
|
||||
|
||||
Iim _iim { _env };
|
||||
Iomux _iomux { _env };
|
||||
Ccm _ccm { _env };
|
||||
Src _src { _env };
|
||||
|
||||
protected:
|
||||
|
||||
Session_component *_create_session(const char *) override {
|
||||
return new (md_alloc()) Session_component(_iim, _iomux, _ccm, _src); }
|
||||
|
||||
public:
|
||||
|
||||
Root(Genode::Env &env,
|
||||
Genode::Allocator &md_alloc)
|
||||
: Genode::Root_component<Session_component>(env.ep(), md_alloc), _env(env)
|
||||
{ }
|
||||
};
|
||||
|
||||
|
||||
struct Main
|
||||
{
|
||||
Genode::Env & env;
|
||||
Genode::Heap heap { env.ram(), env.rm() };
|
||||
Platform::Root root { env, heap };
|
||||
|
||||
Main(Genode::Env & env) : env(env) {
|
||||
env.parent().announce(env.ep().manage(root)); }
|
||||
};
|
||||
|
||||
|
||||
void Component::construct(Genode::Env &env)
|
||||
{
|
||||
Genode::log("--- i.MX53 platform driver ---");
|
||||
|
||||
static Main main(env);
|
||||
}
|
||||
@ -1,43 +0,0 @@
|
||||
/*
|
||||
* \brief System reset controller register description
|
||||
* \author Nikolay Golikov <nik@ksyslabs.org>
|
||||
* \author Stefan Kalkowski <stefan.kalkowski@genode-labs.com>
|
||||
* \date 2013-04-29
|
||||
*/
|
||||
|
||||
/*
|
||||
* Copyright (C) 2013-2017 Genode Labs GmbH
|
||||
*
|
||||
* This file is part of the Genode OS framework, which is distributed
|
||||
* under the terms of the GNU Affero General Public License version 3.
|
||||
*/
|
||||
|
||||
#ifndef _DRIVERS__PLATFORM__SPEC__IMX53__SRC_H_
|
||||
#define _DRIVERS__PLATFORM__SPEC__IMX53__SRC_H_
|
||||
|
||||
/* Genode includes */
|
||||
#include <util/mmio.h>
|
||||
#include <drivers/defs/imx53.h>
|
||||
#include <base/attached_io_mem_dataspace.h>
|
||||
|
||||
class Src : public Genode::Attached_io_mem_dataspace,
|
||||
Genode::Mmio
|
||||
{
|
||||
private:
|
||||
|
||||
struct Ctrl_reg : Register<0x0, 32>
|
||||
{
|
||||
struct Ipu_rst : Bitfield<3, 1> { };
|
||||
};
|
||||
|
||||
public:
|
||||
|
||||
Src(Genode::Env &env)
|
||||
: Genode::Attached_io_mem_dataspace(env, Imx53::SRC_BASE,
|
||||
Imx53::SRC_SIZE),
|
||||
Genode::Mmio((Genode::addr_t)local_addr<void>()) {}
|
||||
|
||||
void reset_ipu() { write<Ctrl_reg::Ipu_rst>(1); }
|
||||
};
|
||||
|
||||
#endif /* _DRIVERS__PLATFORM__SPEC__IMX53__SRC_H_ */
|
||||
@ -1,5 +0,0 @@
|
||||
TARGET = legacy_imx53_platform_drv
|
||||
REQUIRES = arm_v7
|
||||
SRC_CC = main.cc
|
||||
INC_DIR += ${PRG_DIR} $(call select_from_repositories,include/spec/imx53)
|
||||
LIBS = base
|
||||
Loading…
Reference in New Issue
Block a user