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vm_session: adjustments to work with seoul vmm
for foc, nova, sel4 Issue #3111
This commit is contained in:
Alexander Boettcher
committed by
Christian Helmuth
Christian Helmuth
parent
8950de5a89
commit
cc64c43758
@ -46,7 +46,6 @@ static uint32_t svm_features()
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}
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static bool svm_np() { return svm_features() & (1U << 0); }
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static bool svm_instr_decode_support() { return svm_features() & (1U << 7); }
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struct Vcpu;
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@ -137,6 +136,7 @@ struct Vcpu : Genode::Thread
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INTR_INFO = 0x4016,
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INTR_ERROR = 0x4018,
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ENTRY_INST_LEN = 0x401a,
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IDT_INFO = 0x4408,
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IDT_ERROR = 0x440a,
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@ -154,39 +154,44 @@ struct Vcpu : Genode::Thread
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enum Vmcb
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{
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CTRL0_INTR = 1u << 0,
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CTRL0_NMI = 1u << 1,
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CTRL0_INIT = 1u << 3,
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CTRL0_INVD = 1u << 22,
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CTRL0_HLT = 1u << 24,
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CTRL0_VINTR = 1u << 4,
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CTRL0_IO = 1u << 27,
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CTRL0_MSR = 1u << 28,
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CTRL0_SHUTDOWN = 1u << 31,
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AMD_EXIT_INVALID = 0xfd
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AMD_SVM_ENABLE = 1 << 12,
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AMD_EXIT_INVALID = 0xfd,
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};
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enum {
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CR0_PE = 0, /* 1U << 0 - not needed in case of UG */
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CR0_CP = 1U << 1,
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CR0_TS = 1u << 3,
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CR0_NE = 1U << 5,
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CR0_NM = 1U << 29,
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CR0_CD = 1U << 30,
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CR0_PG = 0 /* 1U << 31 - not needed in case of UG */
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};
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addr_t const vmcb_ctrl0 = CTRL0_INTR | CTRL0_NMI | CTRL0_INIT |
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CTRL0_INVD | CTRL0_HLT | CTRL0_IO |
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CTRL0_MSR | CTRL0_SHUTDOWN;
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addr_t const _cr0_mask { CR0_CP | CR0_NM | CR0_NE | CR0_CD };
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addr_t const vmcb_ctrl0 { CTRL0_IO | CTRL0_MSR };
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addr_t const vmcb_ctrl1 { 0 };
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addr_t vmcb_cr0_shadow { 0 };
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addr_t vmcb_cr4_shadow { 0 };
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addr_t const vmcb_cr0_mask { _cr0_mask | CR0_TS };
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addr_t const vmcb_cr0_set { 0 };
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addr_t const vmcb_cr4_mask { 0 };
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addr_t const vmcb_cr4_set { 0 };
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enum { EXIT_ON_HLT = 1U << 7 };
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addr_t const _vmcs_ctrl0 = EXIT_ON_HLT;
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addr_t const _vmcs_ctrl0 { EXIT_ON_HLT };
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addr_t const vmcs_cr0_mask = CR0_PE | CR0_CP | CR0_NM | CR0_NE | CR0_CD | CR0_PG;
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addr_t const vmcs_cr0_set = 0;
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addr_t const vmcs_cr0_mask { _cr0_mask | CR0_PE | CR0_PG };
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addr_t const vmcs_cr0_set { 0 };
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addr_t const vmcs_cr4_mask = CR4_VMX;
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addr_t const vmcs_cr4_set = CR4_VMX;
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addr_t const vmcs_cr4_mask { CR4_VMX };
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addr_t const vmcs_cr4_set { CR4_VMX };
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Signal_context_capability _signal;
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Semaphore _wake_up { 0 };
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@ -211,7 +216,7 @@ struct Vcpu : Genode::Thread
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PAUSE = 1,
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RUN = 2,
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TERMINATE = 3,
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} _remote { PAUSE };
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} _remote { NONE };
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Lock _remote_lock { Lock::UNLOCKED };
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void entry() override
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@ -265,7 +270,6 @@ struct Vcpu : Genode::Thread
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* Fiasoc.OC peculiarities
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*/
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if (_vm_type == Virt::SVM) {
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enum { AMD_SVM_ENABLE = 1 << 12 };
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state.efer.value(state.efer.value() | AMD_SVM_ENABLE);
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}
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if (_vm_type == Virt::SVM) {
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@ -274,12 +278,9 @@ struct Vcpu : Genode::Thread
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if (!vmcb->control_area.np_enable)
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vmcb->control_area.intercept_exceptions |= 1 << 14;
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/* XXX - further stuff needed .. */
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if (!svm_instr_decode_support()) {
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vmcb->control_area.intercept_instruction0 = vmcb_ctrl0;
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vmcb->control_area.intercept_rd_crX = 0x0001; /* cr0 */
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vmcb->control_area.intercept_wr_crX = 0x0001; /* cr0 */
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}
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vmcb->control_area.intercept_instruction0 = vmcb_ctrl0;
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vmcb->control_area.intercept_rd_crX = 0x0001; /* cr0 */
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vmcb->control_area.intercept_wr_crX = 0x0001; /* cr0 */
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}
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if (_vm_type == Virt::VMX) {
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Fiasco::l4_vm_vmx_write(vmcs, Vmcs::CR0_MASK, vmcs_cr0_mask);
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@ -295,6 +296,13 @@ struct Vcpu : Genode::Thread
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Fiasco::l4_vm_vmx_write(vmcs, Vmcs::ENTRY_CTRL, ENTRY_LOAD_EFER);
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}
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if (_vm_type == Virt::SVM)
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_write_amd_state(state, vmcb, vcpu);
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if (_vm_type == Virt::VMX)
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_write_intel_state(state, vmcs, vcpu);
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vcpu->saved_state = L4_VCPU_F_USER_MODE | L4_VCPU_F_FPU_ENABLED;
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State local_state { NONE };
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while (true) {
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@ -303,6 +311,15 @@ struct Vcpu : Genode::Thread
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Lock::Guard guard(_remote_lock);
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local_state = _remote;
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_remote = NONE;
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if (local_state == PAUSE) {
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while (vcpu->sticky_flags) {
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/* consume spurious notifications */
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Fiasco::l4_cap_idx_t tid = native_thread().kcap;
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Fiasco::l4_cap_idx_t irq = tid + Fiasco::TASK_VCPU_IRQ_CAP;
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l4_irq_receive(irq, L4_IPC_RECV_TIMEOUT_0);
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}
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}
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}
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if (local_state == NONE) {
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@ -316,11 +333,6 @@ struct Vcpu : Genode::Thread
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if (_vm_type == Virt::VMX)
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_write_intel_state(state, vmcs, vcpu);
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/* consume spurious notifications */
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Fiasco::l4_cap_idx_t tid = native_thread().kcap;
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Fiasco::l4_cap_idx_t irq = tid + Fiasco::TASK_VCPU_IRQ_CAP;
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l4_irq_receive(irq, L4_IPC_RECV_TIMEOUT_0);
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state.exit_reason = VMEXIT_PAUSED;
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if (_vm_type == Virt::SVM)
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@ -350,8 +362,6 @@ struct Vcpu : Genode::Thread
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if (_vm_type == Virt::VMX)
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_write_intel_state(state, vmcs, vcpu);
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vcpu->saved_state = L4_VCPU_F_USER_MODE | L4_VCPU_F_FPU_ENABLED;
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/* tell Fiasco.OC to run the vCPU */
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l4_msgtag_t tag = l4_thread_vcpu_resume_start();
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tag = l4_thread_vcpu_resume_commit(L4_INVALID_CAP, tag);
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@ -377,9 +387,11 @@ struct Vcpu : Genode::Thread
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}
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/* consume notification */
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Fiasco::l4_cap_idx_t tid = native_thread().kcap;
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Fiasco::l4_cap_idx_t irq = tid + Fiasco::TASK_VCPU_IRQ_CAP;
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l4_irq_receive(irq, L4_IPC_NEVER);
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while (vcpu->sticky_flags) {
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Fiasco::l4_cap_idx_t tid = native_thread().kcap;
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Fiasco::l4_cap_idx_t irq = tid + Fiasco::TASK_VCPU_IRQ_CAP;
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l4_irq_receive(irq, L4_IPC_RECV_TIMEOUT_0);
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}
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}
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state.exit_reason = reason & 0xff;
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@ -400,9 +412,11 @@ struct Vcpu : Genode::Thread
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}
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/* consume notification */
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Fiasco::l4_cap_idx_t tid = native_thread().kcap;
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Fiasco::l4_cap_idx_t irq = tid + Fiasco::TASK_VCPU_IRQ_CAP;
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l4_irq_receive(irq, L4_IPC_RECV_TIMEOUT_0);
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while (vcpu->sticky_flags) {
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Fiasco::l4_cap_idx_t tid = native_thread().kcap;
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Fiasco::l4_cap_idx_t irq = tid + Fiasco::TASK_VCPU_IRQ_CAP;
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l4_irq_receive(irq, L4_IPC_RECV_TIMEOUT_0);
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}
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}
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state.exit_reason = reason & 0xff;
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@ -468,12 +482,8 @@ struct Vcpu : Genode::Thread
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addr_t const cr0 = Fiasco::l4_vm_vmx_read(vmcs, Vmcs::CR0);
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addr_t const cr0_shadow = Fiasco::l4_vm_vmx_read(vmcs, Vmcs::CR0_SHADOW);
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state.cr0.value((cr0 & ~vmcs_cr0_mask) | (cr0_shadow & vmcs_cr0_mask));
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if (state.cr0.value() != cr0_shadow) {
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Genode::error("reset cr0_shadow to cr0 ", Genode::Hex(cr0),
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" ", Genode::Hex(cr0_shadow), "->",
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Genode::Hex(state.cr0.value()));
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if (state.cr0.value() != cr0_shadow)
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Fiasco::l4_vm_vmx_write(vmcs, Vmcs::CR0_SHADOW, state.cr0.value());
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}
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}
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unsigned const cr2 = Fiasco::l4_vm_vmx_get_cr2_index(vmcs);
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@ -484,19 +494,11 @@ struct Vcpu : Genode::Thread
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addr_t const cr4 = Fiasco::l4_vm_vmx_read(vmcs, Vmcs::CR4);
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addr_t const cr4_shadow = Fiasco::l4_vm_vmx_read(vmcs, Vmcs::CR4_SHADOW);
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state.cr4.value((cr4 & ~vmcs_cr4_mask) | (cr4_shadow & vmcs_cr4_mask));
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if (state.cr4.value() != cr4_shadow) {
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Genode::error("reset cr0_shadow to cr4 ", Genode::Hex(cr4),
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" ", Genode::Hex(cr4_shadow), "->",
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Genode::Hex(state.cr4.value()));
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if (state.cr4.value() != cr4_shadow)
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Fiasco::l4_vm_vmx_write(vmcs, Vmcs::CR4_SHADOW,
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state.cr4.value());
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}
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}
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/*
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state.cs.value(Segment{utcb.cs.sel, utcb.cs.ar, utcb.cs.limit,
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utcb.cs.base});
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*/
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using Fiasco::l4_vm_vmx_read;
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using Fiasco::l4_vm_vmx_read_16;
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using Fiasco::l4_vm_vmx_read_32;
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@ -636,7 +638,7 @@ struct Vcpu : Genode::Thread
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state.sp.value(vmcb->state_save_area.rsp);
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state.ip.value(vmcb->state_save_area.rip);
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state.ip_len.value(state.ip_len.value()); /* unsupported on AMD */
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state.ip_len.value(0); /* unsupported on AMD */
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state.dr7.value(vmcb->state_save_area.dr7);
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@ -651,10 +653,20 @@ struct Vcpu : Genode::Thread
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state.r15.value(vcpu->r.r15);
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#endif
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state.cr0.value(vmcb->state_save_area.cr0);
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{
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addr_t const cr0 = vmcb->state_save_area.cr0;
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state.cr0.value((cr0 & ~vmcb_cr0_mask) | (vmcb_cr0_shadow & vmcb_cr0_mask));
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if (state.cr0.value() != vmcb_cr0_shadow)
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vmcb_cr0_shadow = state.cr0.value();
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}
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state.cr2.value(vmcb->state_save_area.cr2);
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state.cr3.value(vmcb->state_save_area.cr3);
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state.cr4.value(vmcb->state_save_area.cr4);
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{
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addr_t const cr4 = vmcb->state_save_area.cr4;
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state.cr4.value((cr4 & ~vmcb_cr4_mask) | (vmcb_cr4_shadow & vmcb_cr4_mask));
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if (state.cr4.value() != vmcb_cr4_shadow)
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vmcb_cr4_shadow = state.cr4.value();
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}
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typedef Genode::Vm_state::Segment Segment;
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@ -733,9 +745,7 @@ struct Vcpu : Genode::Thread
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state.tsc.value(Trace::timestamp());
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state.tsc_offset.value(_tsc_offset);
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if (state.efer.valid()) {
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Genode::error("efer not implemented");
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}
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state.efer.value(vmcb->state_save_area.efer);
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if (state.pdpte_0.valid() || state.pdpte_1.valid() ||
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state.pdpte_2.valid() || state.pdpte_3.valid()) {
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@ -760,12 +770,14 @@ struct Vcpu : Genode::Thread
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using Fiasco::l4_vm_vmx_write;
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if (state.ax.valid() || state.cx.valid() || state.dx.valid() ||
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state.bx.valid() || state.bp.valid() || state.di.valid() ||
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state.si.valid()) {
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state.bx.valid()) {
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vcpu->r.ax = state.ax.value();
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vcpu->r.cx = state.cx.value();
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vcpu->r.dx = state.dx.value();
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vcpu->r.bx = state.bx.value();
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}
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if (state.bp.valid() || state.di.valid() || state.si.valid()) {
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vcpu->r.bp = state.bp.value();
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vcpu->r.di = state.di.value();
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vcpu->r.si = state.si.value();
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@ -825,9 +837,10 @@ struct Vcpu : Genode::Thread
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l4_vm_vmx_write(vmcs, Vmcs::CR4_SHADOW, state.cr4.value());
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}
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#if 1
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if (state.inj_info.valid() || state.inj_error.valid()) {
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addr_t ctrl_0 = Fiasco::l4_vm_vmx_read(vmcs, Vmcs::CTRL_0);
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addr_t ctrl_0 = state.ctrl_primary.valid() ?
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state.ctrl_primary.value() :
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Fiasco::l4_vm_vmx_read(vmcs, Vmcs::CTRL_0);
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if (state.inj_info.value() & 0x2000)
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Genode::warning("unimplemented ", state.inj_info.value() & 0x1000, " ", state.inj_info.value() & 0x2000, " ", Genode::Hex(ctrl_0), " ", Genode::Hex(state.ctrl_secondary.value()));
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@ -844,7 +857,6 @@ struct Vcpu : Genode::Thread
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l4_vm_vmx_write(vmcs, Vmcs::INTR_ERROR,
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state.inj_error.value());
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}
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#endif
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if (state.flags.valid())
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l4_vm_vmx_write(vmcs, Vmcs::FLAGS, state.flags.value());
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@ -855,24 +867,27 @@ struct Vcpu : Genode::Thread
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if (state.ip.valid())
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l4_vm_vmx_write(vmcs, Vmcs::IP, state.ip.value());
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if (state.ip_len.valid())
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l4_vm_vmx_write(vmcs, Vmcs::ENTRY_INST_LEN, state.ip_len.value());
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if (state.efer.valid())
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l4_vm_vmx_write(vmcs, Vmcs::EFER, state.efer.value());
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if (state.ctrl_primary.valid())
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l4_vm_vmx_write(vmcs, Vmcs::CTRL_0,
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_vmcs_ctrl0 | state.ctrl_primary.value());
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_vmcs_ctrl0 | state.ctrl_primary.value());
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if (state.ctrl_secondary.valid())
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l4_vm_vmx_write(vmcs, Vmcs::CTRL_1,
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state.ctrl_secondary.value());
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state.ctrl_secondary.value());
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if (state.intr_state.valid())
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l4_vm_vmx_write(vmcs, Vmcs::STATE_INTR,
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state.intr_state.value());
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state.intr_state.value());
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if (state.actv_state.valid())
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l4_vm_vmx_write(vmcs, Vmcs::STATE_ACTV,
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state.actv_state.valid());
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state.actv_state.value());
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if (state.cs.valid()) {
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l4_vm_vmx_write(vmcs, Vmcs::CS_SEL, state.cs.value().sel);
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@ -964,13 +979,16 @@ struct Vcpu : Genode::Thread
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Fiasco::l4_vcpu_state_t *vcpu)
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{
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if (state.ax.valid() || state.cx.valid() || state.dx.valid() ||
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state.bx.valid() || state.bp.valid() || state.di.valid() ||
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state.si.valid()) {
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state.bx.valid()) {
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vmcb->state_save_area.rax = state.ax.value();
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vcpu->r.ax = state.ax.value();
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vcpu->r.cx = state.cx.value();
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vcpu->r.dx = state.dx.value();
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vcpu->r.bx = state.bx.value();
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}
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if (state.bp.valid() || state.di.valid() || state.si.valid()) {
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vcpu->r.bp = state.bp.value();
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vcpu->r.di = state.di.value();
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vcpu->r.si = state.si.value();
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@ -1007,7 +1025,8 @@ struct Vcpu : Genode::Thread
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vmcb->state_save_area.dr7 = state.dr7.value();
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if (state.cr0.valid()) {
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vmcb->state_save_area.cr0 = state.cr0.value();
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vmcb->state_save_area.cr0 = vmcb_cr0_set | (~vmcb_cr0_mask & state.cr0.value());
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vmcb_cr0_shadow = state.cr0.value();
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#if 0
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vmcb->state_save_area.xcr0 = state.cr0();
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#endif
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@ -1019,13 +1038,36 @@ struct Vcpu : Genode::Thread
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if (state.cr3.valid())
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vmcb->state_save_area.cr3 = state.cr3.value();
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if (state.cr4.valid())
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vmcb->state_save_area.cr4 = state.cr4.value();
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if (state.cr4.valid()) {
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vmcb->state_save_area.cr4 = vmcb_cr4_set | (~vmcb_cr4_mask & state.cr4.value());
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vmcb_cr4_shadow = state.cr4.value();
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}
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if (state.inj_info.valid())
|
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Genode::error(__LINE__, " not implemented ");
|
||||
if (state.inj_error.valid())
|
||||
Genode::error(__LINE__, " not implemented ");
|
||||
if (state.ctrl_primary.valid())
|
||||
vmcb->control_area.intercept_instruction0 = vmcb_ctrl0 |
|
||||
state.ctrl_primary.value();
|
||||
|
||||
if (state.ctrl_secondary.valid())
|
||||
vmcb->control_area.intercept_instruction1 = vmcb_ctrl1 |
|
||||
state.ctrl_secondary.value();
|
||||
|
||||
if (state.inj_info.valid()) {
|
||||
if (state.inj_info.value() & 0x1000) {
|
||||
vmcb->control_area.interrupt_ctl |= (1ul << 8 | 1ul << 20);
|
||||
vmcb->control_area.intercept_instruction0 |= Vmcb::CTRL0_VINTR;
|
||||
} else {
|
||||
vmcb->control_area.interrupt_ctl &= ~(1ul << 8 | 1ul << 20);
|
||||
vmcb->control_area.intercept_instruction0 &= ~Vmcb::CTRL0_VINTR;
|
||||
}
|
||||
vmcb->control_area.eventinj = 0;
|
||||
vmcb->control_area.eventinj |= ~0x3000U & state.inj_info.value();
|
||||
}
|
||||
|
||||
if (state.inj_error.valid()) {
|
||||
vmcb->control_area.eventinj &= ((1ULL << 32) - 1);
|
||||
uint64_t value = (0ULL + state.inj_error.value()) << 32;
|
||||
vmcb->control_area.eventinj |= value;
|
||||
}
|
||||
|
||||
if (state.flags.valid())
|
||||
vmcb->state_save_area.rflags = state.flags.value();
|
||||
@ -1037,14 +1079,7 @@ struct Vcpu : Genode::Thread
|
||||
vmcb->state_save_area.rip = state.ip.value();
|
||||
|
||||
if (state.efer.valid())
|
||||
vmcb->state_save_area.efer = state.efer.value();
|
||||
|
||||
if (state.ctrl_primary.valid())
|
||||
vmcb->control_area.intercept_instruction0 = vmcb_ctrl0 |
|
||||
state.ctrl_primary.value();
|
||||
|
||||
if (state.ctrl_secondary.valid())
|
||||
vmcb->control_area.intercept_instruction1 = state.ctrl_secondary.value();
|
||||
vmcb->state_save_area.efer = state.efer.value() | AMD_SVM_ENABLE;
|
||||
|
||||
if (state.intr_state.valid())
|
||||
vmcb->control_area.interrupt_shadow = state.intr_state.value();
|
||||
@ -1162,7 +1197,7 @@ struct Vcpu : Genode::Thread
|
||||
void resume() {
|
||||
Lock::Guard guard(_remote_lock);
|
||||
|
||||
if (_remote == RUN)
|
||||
if (_remote == RUN || _remote == PAUSE)
|
||||
return;
|
||||
|
||||
_remote = RUN;
|
||||
|
||||
Reference in New Issue
Block a user