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app/pci_decode: prepare pci device information
To discharge the generic platform driver from certain PCI bus scanning, and ACPI + kernel specifics, this commit introduces a new component, which consumes the acpi drivers report and the platform_info from core to prepare a devices ROM for the platform driver that contains all PCI devices and its resources. Fix genodelabs/genode#4495
This commit is contained in:
Stefan Kalkowski
committed by
Christian Helmuth
Christian Helmuth
parent
87021d9fb1
commit
cacb6136fa
53
repos/os/src/app/pci_decode/bridge.h
Normal file
53
repos/os/src/app/pci_decode/bridge.h
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@ -0,0 +1,53 @@
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/*
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* \brief Bridge related PCI information
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* \author Stefan Kalkowski
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* \date 2022-05-04
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*/
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/*
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* Copyright (C) 2022 Genode Labs GmbH
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*
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* This file is part of the Genode OS framework, which is distributed
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* under the terms of the GNU Affero General Public License version 3.
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*/
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#include <base/registry.h>
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#include <pci/types.h>
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using namespace Genode;
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struct Bridge : Registry<Bridge>::Element
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{
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Pci::Bdf bdf;
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Pci::bus_t from;
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Pci::bus_t to;
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Registry<Bridge> sub_bridges {};
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Bridge(Registry<Bridge> & registry,
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Pci::Bdf bdf,
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Pci::bus_t from,
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Pci::bus_t to)
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:
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Registry<Bridge>::Element(registry, *this),
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bdf(bdf), from(from), to(to) { }
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bool behind(Pci::bus_t bus) {
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return from <= bus && bus <= to; }
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template <typename FN>
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void find_bridge(Pci::bus_t bus, FN const & fn) {
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if (!behind(bus))
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return;
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bool found = false;
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sub_bridges.for_each([&] (Bridge & b) {
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if (!b.behind(bus))
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return;
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b.find_bridge(bus, fn);
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found = true;
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});
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if (!found) fn(*this);
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}
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};
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165
repos/os/src/app/pci_decode/irq.h
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165
repos/os/src/app/pci_decode/irq.h
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@ -0,0 +1,165 @@
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/*
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* \brief Interrupt related ACPI information in list models
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* \author Stefan Kalkowski
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* \date 2021-12-12
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*/
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/*
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* Copyright (C) 2021 Genode Labs GmbH
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*
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* This file is part of the Genode OS framework, which is distributed
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* under the terms of the GNU Affero General Public License version 3.
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*/
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#include <base/heap.h>
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#include <pci/types.h>
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#include <util/list_model.h>
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#include <util/register.h>
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#include <bridge.h>
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using namespace Genode;
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using namespace Pci;
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struct Irq_override : List_model<Irq_override>::Element
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{
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struct Flags : Register<8>
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{
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struct Polarity : Bitfield<0, 2>
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{
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enum { HIGH = 1, LOW = 3 };
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};
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struct Mode : Bitfield<2, 2>
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{
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enum { EDGE = 1, LEVEL = 3 };
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};
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};
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irq_line_t from;
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irq_line_t to;
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Flags::access_t flags;
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Irq_override(irq_line_t from,
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irq_line_t to,
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Flags::access_t flags)
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: from(from), to(to), flags(flags) {}
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void generate(Xml_generator & generator, irq_line_t & irq)
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{
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if (irq != from)
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return;
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irq = to;
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using Polarity = Flags::Polarity;
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Flags::access_t polarity = Polarity::get(flags);
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if (polarity == Polarity::HIGH)
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generator.attribute("polarity", "high");
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if (polarity == Polarity::LOW)
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generator.attribute("polarity", "low");
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using Mode = Irq_override::Flags::Mode;
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Flags::access_t mode = Mode::get(flags);
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if (mode == Mode::EDGE)
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generator.attribute("mode", "edge");
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if (mode == Mode::LEVEL)
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generator.attribute("mode", "level");
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}
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};
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struct Irq_override_policy : List_model<Irq_override>::Update_policy
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{
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Heap & heap;
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void destroy_element(Irq_override & irq) {
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destroy(heap, &irq); }
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Irq_override & create_element(Xml_node node)
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{
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return *(new (heap)
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Irq_override(node.attribute_value<uint8_t>("irq", 0xff),
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node.attribute_value<uint8_t>("gsi", 0xff),
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node.attribute_value<uint8_t>("flags", 0)));
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}
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void update_element(Irq_override &, Xml_node) {}
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static bool element_matches_xml_node(Irq_override const & irq,
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Genode::Xml_node node) {
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return irq.from == node.attribute_value("irq", ~0U); }
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static bool node_is_element(Genode::Xml_node node) {
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return node.has_type("irq_override"); }
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Irq_override_policy(Heap & heap) : heap(heap) {}
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};
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struct Irq_routing : List_model<Irq_routing>::Element
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{
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Bdf bridge_bdf;
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dev_t dev;
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irq_pin_t pin;
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irq_line_t to;
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Irq_routing(Bdf bridge_bdf,
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dev_t dev,
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irq_pin_t pin,
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irq_line_t to)
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:
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bridge_bdf(bridge_bdf),
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dev(dev), pin(pin), to(to) {}
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void route(Bridge & bridge,
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dev_t device,
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irq_pin_t p,
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irq_line_t & irq)
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{
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if (!(bridge_bdf == bridge.bdf && dev == device && pin == p))
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return;
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irq = to;
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}
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};
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struct Irq_routing_policy : List_model<Irq_routing>::Update_policy
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{
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Heap & heap;
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void destroy_element(Irq_routing & irq) {
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destroy(heap, &irq); }
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Irq_routing & create_element(Xml_node node)
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{
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rid_t bridge_bdf = node.attribute_value<rid_t>("bridge_bdf", 0xff);
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return *(new (heap)
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Irq_routing(Bdf::bdf(bridge_bdf),
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node.attribute_value<uint8_t>("device", 0xff),
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node.attribute_value<uint8_t>("device_pin", 0xff),
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node.attribute_value<uint8_t>("gsi", 0xff)));
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}
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void update_element(Irq_routing &, Xml_node) {}
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static bool element_matches_xml_node(Irq_routing const & ir,
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Genode::Xml_node node)
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{
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rid_t bridge_bdf = node.attribute_value<rid_t>("bridge_bdf", 0xff);
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return ir.bridge_bdf == Bdf::bdf(bridge_bdf) &&
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ir.dev == node.attribute_value<uint8_t>("device", 0xff) &&
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ir.pin == node.attribute_value<uint8_t>("device_pin", 0xff);
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}
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static bool node_is_element(Genode::Xml_node node) {
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return node.has_type("routing"); }
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Irq_routing_policy(Heap & heap) : heap(heap) {}
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};
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262
repos/os/src/app/pci_decode/main.cc
Normal file
262
repos/os/src/app/pci_decode/main.cc
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@ -0,0 +1,262 @@
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/*
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* \brief PCI configuration space decoder
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* \author Stefan Kalkowski
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* \date 2021-12-12
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*/
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/*
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* Copyright (C) 2021 Genode Labs GmbH
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*
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* This file is part of the Genode OS framework, which is distributed
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* under the terms of the GNU Affero General Public License version 3.
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*/
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#include <base/attached_io_mem_dataspace.h>
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#include <base/attached_rom_dataspace.h>
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#include <base/component.h>
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#include <base/env.h>
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#include <base/heap.h>
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#include <os/reporter.h>
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#include <irq.h>
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#include <pci/config.h>
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using namespace Genode;
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using namespace Pci;
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struct Main
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{
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Env & env;
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Heap heap { env.ram(), env.rm() };
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Attached_rom_dataspace platform_info { env, "platform_info" };
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Attached_rom_dataspace sys_rom { env, "system" };
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Signal_handler<Main> sys_rom_handler { env.ep(), *this,
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&Main::sys_rom_update };
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Expanding_reporter pci_reporter { env, "devices", "devices" };
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Registry<Bridge> bridge_registry {}; /* contains host bridges */
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unsigned msi_number { 0U };
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bool apic_capable { false };
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bool msi_capable { false };
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List_model<Irq_routing> irq_routing_list {};
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List_model<Irq_override> irq_override_list {};
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Constructible<Attached_io_mem_dataspace> pci_config_ds {};
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void parse_pci_function(Bdf bdf, Config & cfg,
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addr_t cfg_phys_base,
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Xml_generator & generator);
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void parse_pci_bus(bus_t bus, bus_t offset, addr_t base,
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addr_t phys_base, Xml_generator & generator);
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void parse_irq_override_rules(Xml_node & xml);
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void parse_pci_config_spaces(Xml_node & xml);
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void sys_rom_update();
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template <typename FN>
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void for_bridge(Pci::bus_t bus, FN const & fn)
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{
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bridge_registry.for_each([&] (Bridge & b) {
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if (b.behind(bus)) b.find_bridge(bus, fn); });
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}
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Main(Env & env);
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};
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void Main::parse_pci_function(Bdf bdf,
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Config & cfg,
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addr_t cfg_phys_base,
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Xml_generator & generator)
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{
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cfg.scan();
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Config::Vendor::access_t vendor = cfg.read<Config::Vendor>();
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Config::Device::access_t device = cfg.read<Config::Device>();
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Config::Header_type::Type::access_t type =
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cfg.read<Config::Header_type::Type>();
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Config::Class_code_rev_id::Class_code::access_t dclass =
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cfg.read<Config::Class_code_rev_id::Class_code>();
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if (type) {
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for_bridge(bdf.bus, [&] (Bridge & parent) {
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Config_type1 bcfg(cfg.base());
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new (heap) Bridge(parent.sub_bridges, bdf,
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bcfg.secondary_bus_number(),
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bcfg.subordinate_bus_number());
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});
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}
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bool msi = cfg.msi_cap.constructed();
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bool msi_x = cfg.msi_x_cap.constructed();
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irq_pin_t irq_pin = cfg.read<Config::Irq_pin>();
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generator.node("device", [&]
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{
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generator.attribute("name", Bdf::string(bdf));
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generator.attribute("type", "pci");
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generator.node("pci-config", [&]
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{
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generator.attribute("address", String<16>(Hex(cfg_phys_base)));
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generator.attribute("bus", String<16>(Hex(bdf.bus)));
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generator.attribute("device", String<16>(Hex(bdf.dev)));
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generator.attribute("function", String<16>(Hex(bdf.fn)));
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generator.attribute("vendor_id", String<16>(Hex(vendor)));
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generator.attribute("device_id", String<16>(Hex(device)));
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generator.attribute("class", String<16>(Hex(dclass)));
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generator.attribute("bridge", cfg.bridge() ? "yes" : "no");
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});
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cfg.for_each_bar([&] (uint64_t addr, size_t size) {
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generator.node("io_mem", [&]
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{
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generator.attribute("address", String<16>(Hex(addr)));
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generator.attribute("size", String<16>(Hex(size)));
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});
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}, [&] (uint64_t addr, size_t size) {
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generator.node("io_port_range", [&]
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{
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generator.attribute("address", String<16>(Hex(addr)));
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generator.attribute("size", String<16>(Hex(size)));
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});
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});
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/* IRQ pins count from 1-4 (INTA-D), zero means no IRQ defined */
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if (!irq_pin)
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return;
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generator.node("irq", [&]
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{
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if (msi_capable && msi_x) {
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generator.attribute("type", "msi-x");
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generator.attribute("number", msi_number++);
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return;
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}
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if (msi_capable && msi) {
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generator.attribute("type", "msi");
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generator.attribute("number", msi_number++);
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return;
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}
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irq_line_t irq = cfg.read<Config::Irq_line>();
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for_bridge(bdf.bus, [&] (Bridge & b) {
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irq_routing_list.for_each([&] (Irq_routing & ir) {
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ir.route(b, bdf.dev, irq_pin-1, irq); });
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});
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irq_override_list.for_each([&] (Irq_override & io) {
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io.generate(generator, irq); });
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generator.attribute("number", irq);
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});
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});
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}
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void Main::parse_pci_bus(bus_t bus,
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bus_t offset,
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addr_t base,
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addr_t phys_base,
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Xml_generator & generator)
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{
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auto per_function = [&] (addr_t config_base, addr_t config_phys_base,
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dev_t dev, func_t fn) {
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Config cfg(config_base);
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if (!cfg.valid())
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return true;
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parse_pci_function({(bus_t)(bus+offset), dev, fn}, cfg,
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config_phys_base, generator);
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return !(fn == 0 && !cfg.read<Config::Header_type::Multi_function>());
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};
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for (dev_t dev = 0; dev < DEVICES_PER_BUS_MAX; dev++) {
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for (func_t fn = 0; fn < FUNCTION_PER_DEVICE_MAX; fn++) {
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unsigned factor = (bus * DEVICES_PER_BUS_MAX + dev) *
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FUNCTION_PER_DEVICE_MAX + fn;
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addr_t config_base = base + factor * FUNCTION_CONFIG_SPACE_SIZE;
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addr_t config_phys_base =
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phys_base + factor * FUNCTION_CONFIG_SPACE_SIZE;
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if (!per_function(config_base, config_phys_base, dev, fn))
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break;
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}
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}
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}
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void Main::parse_pci_config_spaces(Xml_node & xml)
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{
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pci_reporter.generate([&] (Xml_generator & generator)
|
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{
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unsigned host_bridge_num = 0;
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xml.for_each_sub_node("bdf", [&] (Xml_node & xml)
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{
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addr_t const start = xml.attribute_value("start", 0UL);
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addr_t const base = xml.attribute_value("base", 0UL);
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size_t const count = xml.attribute_value("count", 0UL);
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bus_t const bus_off = (bus_t) (start / FUNCTION_PER_BUS_MAX);
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bus_t const bus_count = (bus_t) (count / FUNCTION_PER_BUS_MAX);
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|
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if (host_bridge_num++) {
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error("We do not support multiple host bridges by now!");
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return;
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}
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new (heap) Bridge(bridge_registry, { bus_off, 0, 0 },
|
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bus_off, bus_count);
|
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|
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pci_config_ds.construct(env, base, count * FUNCTION_CONFIG_SPACE_SIZE);
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|
||||
for (bus_t bus = 0; bus < bus_count; bus++)
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parse_pci_bus((bus_t)bus, bus_off,
|
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(addr_t)pci_config_ds->local_addr<void>(),
|
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base, generator);
|
||||
|
||||
pci_config_ds.destruct();
|
||||
});
|
||||
});
|
||||
}
|
||||
|
||||
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void Main::sys_rom_update()
|
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{
|
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sys_rom.update();
|
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|
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Xml_node xml = sys_rom.xml();
|
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|
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if (apic_capable) {
|
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Irq_override_policy policy(heap);
|
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irq_override_list.update_from_xml(policy, xml);
|
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}
|
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|
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if (apic_capable) {
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Irq_routing_policy policy(heap);
|
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irq_routing_list.update_from_xml(policy, xml);
|
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}
|
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|
||||
parse_pci_config_spaces(xml);
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}
|
||||
|
||||
|
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Main::Main(Env & env) : env(env)
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||||
{
|
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sys_rom.sigh(sys_rom_handler);
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platform_info.xml().with_sub_node("kernel", [&] (Xml_node xml)
|
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{
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apic_capable = xml.attribute_value("acpi", false);
|
||||
msi_capable = xml.attribute_value("msi", false);
|
||||
});
|
||||
}
|
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|
||||
|
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void Component::construct(Genode::Env &env) { static Main main(env); }
|
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4
repos/os/src/app/pci_decode/target.mk
Normal file
4
repos/os/src/app/pci_decode/target.mk
Normal file
@ -0,0 +1,4 @@
|
||||
TARGET = pci_decode
|
||||
LIBS = base
|
||||
SRC_CC = main.cc
|
||||
INC_DIR = $(PRG_DIR)
|
||||
Reference in New Issue
Block a user