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Simplify GPIO session interface (fix #707)

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Changes GPIO session interface to a one-GPIO-pin-per-session style. Moreover,
this commit introduces a generic driver interface for GPIO drivers. Thereby
generalizes root- and session component for GPIO.
This commit is contained in:
Stefan Kalkowski 2013-05-06 14:33:30 +02:00 committed by Norman Feske
parent 562ac7d059
commit ca92984bcc
17 changed files with 966 additions and 1411 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

29
base/include/platform/imx53/drivers/board_base.h
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@ -40,6 +40,35 @@ namespace Genode
EPIT_2_MMIO_BASE = 0x53fb0000,
EPIT_2_MMIO_SIZE = 0x00004000,
GPIO1_MMIO_BASE = 0x53f84000,
GPIO1_MMIO_SIZE = 0x4000,
GPIO2_MMIO_BASE = 0x53f88000,
GPIO2_MMIO_SIZE = 0x4000,
GPIO3_MMIO_BASE = 0x53f8c000,
GPIO3_MMIO_SIZE = 0x4000,
GPIO4_MMIO_BASE = 0x53f90000,
GPIO4_MMIO_SIZE = 0x4000,
GPIO5_MMIO_BASE = 0x53fdc000,
GPIO5_MMIO_SIZE = 0x4000,
GPIO6_MMIO_BASE = 0x53fe0000,
GPIO6_MMIO_SIZE = 0x4000,
GPIO7_MMIO_BASE = 0x53fe4000,
GPIO7_MMIO_SIZE = 0x4000,
GPIO1_IRQL = 50,
GPIO1_IRQH = 51,
GPIO2_IRQL = 52,
GPIO2_IRQH = 53,
GPIO3_IRQL = 54,
GPIO3_IRQH = 55,
GPIO4_IRQL = 56,
GPIO4_IRQH = 57,
GPIO5_IRQL = 103,
GPIO5_IRQH = 104,
GPIO6_IRQL = 105,
GPIO6_IRQH = 106,
GPIO7_IRQL = 107,
GPIO7_IRQH = 108,
TZIC_MMIO_BASE = 0x0fffc000,
TZIC_MMIO_SIZE = 0x00004000,

20
base/include/platform/panda/drivers/board_base.h
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@ -63,6 +63,26 @@ namespace Genode
HDMI_MMIO_BASE = 0x58006000,
HDMI_MMIO_SIZE = 0x00001000,
/* GPIO */
GPIO1_MMIO_BASE = 0x4a310000,
GPIO1_MMIO_SIZE = 0x1000,
GPIO1_IRQ = 29 + 32,
GPIO2_MMIO_BASE = 0x48055000,
GPIO2_MMIO_SIZE = 0x1000,
GPIO2_IRQ = 30 + 32,
GPIO3_MMIO_BASE = 0x48057000,
GPIO3_MMIO_SIZE = 0x1000,
GPIO3_IRQ = 31 + 32,
GPIO4_MMIO_BASE = 0x48059000,
GPIO4_MMIO_SIZE = 0x1000,
GPIO4_IRQ = 32 + 32,
GPIO5_MMIO_BASE = 0x4805b000,
GPIO5_MMIO_SIZE = 0x1000,
GPIO5_IRQ = 33 + 32,
GPIO6_MMIO_BASE = 0x4805d000,
GPIO6_MMIO_SIZE = 0x1000,
GPIO6_IRQ = 34 + 32,
/* misc */
SECURITY_EXTENSION = 0,
SYS_CLK = 38400000,

128
os/include/gpio/component.h Normal file
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@ -0,0 +1,128 @@
/*
* \brief GPIO-session component
* \author Stefan Kalkowski
* \date 2013-05-03
*/
/*
* Copyright (C) 2011-2013 Genode Labs GmbH
*
* This file is part of the Genode OS framework, which is distributed
* under the terms of the GNU General Public License version 2.
*/
#ifndef _INCLUDE__GPIO__COMPONENT_H_
#define _INCLUDE__GPIO__COMPONENT_H_
#include <base/printf.h>
#include <root/component.h>
#include <gpio_session/gpio_session.h>
#include <gpio/driver.h>
namespace Gpio {
class Session_component;
class Root;
};
class Gpio::Session_component : public Genode::Rpc_object<Gpio::Session>
{
private:
Driver &_driver;
unsigned long _pin;
Genode::Signal_context_capability _sigh;
public:
Session_component(Driver &driver, unsigned long gpio_pin)
: _driver(driver), _pin(gpio_pin) { }
~Session_component()
{
if (_sigh.valid())
_driver.unregister_signal(_pin);
}
/************************************
** Gpio::Session interface **
************************************/
void direction(Direction d) { _driver.direction(_pin, (d == IN)); }
void write(bool level) { _driver.write(_pin, level); }
bool read() { return _driver.read(_pin); }
void irq_enable(bool enable) { _driver.irq_enable(_pin, enable); }
void irq_sigh(Genode::Signal_context_capability cap)
{
if (cap.valid()) {
_sigh = cap;
_driver.register_signal(_pin, cap);
}
}
void irq_type(Irq_type type)
{
switch (type) {
case HIGH_LEVEL:
_driver.high_detect(_pin);
break;
case LOW_LEVEL:
_driver.low_detect(_pin);
break;
case RISING_EDGE:
_driver.rising_detect(_pin);
break;
case FALLING_EDGE:
_driver.falling_detect(_pin);
};
}
void debouncing(unsigned int us)
{
if (us) {
_driver.debounce_time(_pin, us);
_driver.debounce_enable(_pin, true);
} else
_driver.debounce_enable(_pin, false);
}
};
class Gpio::Root : public Genode::Root_component<Gpio::Session_component>
{
private:
Driver &_driver;
protected:
Session_component *_create_session(const char *args)
{
unsigned long pin =
Genode::Arg_string::find_arg(args, "gpio").ulong_value(0);
Genode::size_t ram_quota =
Genode::Arg_string::find_arg(args, "ram_quota").ulong_value(0);
if (!_driver.gpio_valid(pin))
throw Invalid_args();
if (ram_quota < sizeof(Session_component)) {
PWRN("Insufficient dontated ram_quota (%zd bytes), require %zd bytes",
ram_quota, sizeof(Session_component));
throw Genode::Root::Quota_exceeded();
}
return new (md_alloc()) Session_component(_driver, pin);
}
public:
Root(Genode::Rpc_entrypoint *session_ep,
Genode::Allocator *md_alloc, Driver &driver)
: Genode::Root_component<Gpio::Session_component>(session_ep, md_alloc),
_driver(driver) { }
};
#endif /* _INCLUDE__GPIO__COMPONENT_H_ */

78
os/include/gpio/config.h Normal file
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@ -0,0 +1,78 @@
/*
* \brief Access to GPIO driver configuration
* \author Stefan Kalkowski
* \date 2013-05-06
*
* Taken from the OMAP4 GPIO driver written by Ivan Loskutov.
*
* Configure GPIO
* Example:
* <config>
* <gpio num="123" mode="I"/>
* <gpio num="124" mode="O" value="0"/>
* </config>
*
* num - GPIO pin number
* mode - input(I) or output(O)
* value - output level (1 or 0), only for output mode
*/
/*
* Copyright (C) 2010-2013 Genode Labs GmbH
*
* This file is part of the Genode OS framework, which is distributed
* under the terms of the GNU General Public License version 2.
*/
#ifndef _INCLUDE__GPIO__CONFIG_H_
#define _INCLUDE__GPIO__CONFIG_H_
#include <base/exception.h>
#include <os/config.h>
#include <gpio/driver.h>
namespace Gpio {
class Invalid_gpio_number : Genode::Exception {};
class Invalid_mode : Genode::Exception {};
static void process_config(Gpio::Driver &driver);
}
void Gpio::process_config(Gpio::Driver &driver) {
try {
Genode::Xml_node gpio_node = Genode::config()->xml_node().sub_node("gpio");
for (;; gpio_node = gpio_node.next("gpio")) {
unsigned num = 0;
char mode[2] = {0};
unsigned value = 0;
try {
gpio_node.attribute("num").value(&num);
if (!driver.gpio_valid(num)) throw Invalid_gpio_number();
gpio_node.attribute("mode").value(mode, sizeof(mode));
if (mode[0] == 'O' || mode[0] == 'o') {
gpio_node.attribute("value").value(&value);
driver.write(num, value);
driver.direction(num, false);
} else if (mode[0] == 'I' || mode[0] == 'i') {
driver.direction(num, true);
} else throw Invalid_mode();
PINF("gpio %d mode %s value=%d", num, mode, value);
} catch(Genode::Xml_node::Nonexistent_attribute) {
PWRN("Missing attribute. Ignore node.");
} catch(Gpio::Invalid_gpio_number) {
PWRN("Invalid GPIO number %d. Ignore node", num);
}
if (gpio_node.is_last("gpio")) break;
}
}
catch (Genode::Xml_node::Nonexistent_sub_node) {
PWRN("No GPIO config");
}
}
#endif /* _INCLUDE__GPIO__CONFIG_H_ */

119
os/include/gpio/driver.h Normal file
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@ -0,0 +1,119 @@
/*
* \brief GPIO driver interface
* \author Stefan Kalkowski
* \date 2013-05-03
*/
/*
* Copyright (C) 2011-2013 Genode Labs GmbH
*
* This file is part of the Genode OS framework, which is distributed
* under the terms of the GNU General Public License version 2.
*/
#ifndef _INCLUDE__GPIO__DRIVER_H_
#define _INCLUDE__GPIO__DRIVER_H_
/* Genode includes */
#include <base/signal.h>
namespace Gpio {
struct Driver;
}
struct Gpio::Driver {
/**
* Set direction of GPIO pin, whether it's an input or output one
*
*\param gpio corresponding gpio pin number
*/
virtual void direction(unsigned gpio, bool input) = 0;
/**
* Set output level (high or low)
*
*\param gpio corresponding gpio pin number
*/
virtual void write(unsigned gpio, bool enable) = 0;
/**
* Read input level (high or low)
*
*\param gpio corresponding gpio pin number
*/
virtual bool read(unsigned gpio) = 0;
/**
* Enable/disable debounce logic for the GPIO pin
*
*\param gpio corresponding gpio pin number
*/
virtual void debounce_enable(unsigned gpio, bool enable) = 0;
/**
* Set delay for debounce logic for the GPIO pin
*
*\param gpio corresponding gpio pin number
*/
virtual void debounce_time(unsigned gpio, unsigned long us) = 0;
/**
* Set IRQ trigger state to falling edge-triggered
*
*\param gpio corresponding gpio pin number
*/
virtual void falling_detect(unsigned gpio) = 0;
/**
* Set IRQ trigger state to rising edge-triggered
*
*\param gpio corresponding gpio pin number
*/
virtual void rising_detect(unsigned gpio) = 0;
/**
* Set IRQ trigger state to high level-triggered
*
*\param gpio corresponding gpio pin number
*/
virtual void high_detect(unsigned gpio) = 0;
/**
* Set IRQ trigger state to low level-triggered
*
*\param gpio corresponding gpio pin number
*/
virtual void low_detect(unsigned gpio) = 0;
/**
* Enable/disable IRQ for specified GPIO pin
*
*\param gpio corresponding gpio pin number
*/
virtual void irq_enable(unsigned gpio, bool enable) = 0;
/**
* Register signal handler for interrupts
*
*\param gpio corresponding gpio pin number
*/
virtual void register_signal(unsigned gpio,
Genode::Signal_context_capability cap) = 0;
/**
* Unregister signal handler
*
*\param gpio corresponding gpio pin number
*/
virtual void unregister_signal(unsigned gpio) = 0;
/**
* Check whether GPIO number is valid
*
*\param gpio corresponding gpio pin number
*/
virtual bool gpio_valid(unsigned gpio) = 0;
};
#endif /* _INCLUDE__GPIO__DRIVER_H_ */

61
os/include/gpio_session/client.h
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@ -1,6 +1,7 @@
/*
* \brief Client-side Gpio session interface
* \author Ivan Loskutov <ivan.loskutov@ksyslabs.org>
* \author Stefan Kalkowski <Stefan.kalkowski@genode-labs.com>
* \date 2012-06-23
*/
@ -25,57 +26,15 @@ namespace Gpio {
explicit Session_client(Session_capability session)
: Genode::Rpc_client<Session>(session) { }
void direction_output(int gpio, bool enable)
{
call<Rpc_direction_output>(gpio, enable);
}
void direction_input(int gpio)
{
call<Rpc_direction_input>(gpio);
}
void dataout(int gpio, bool enable)
{
call<Rpc_dataout>(gpio, enable);
}
int datain(int gpio)
{
return call<Rpc_datain>(gpio);
}
void debounce_enable(int gpio, bool enable)
{
call<Rpc_debounce_enable>(gpio, enable);
}
void debouncing_time(int gpio, unsigned int us)
{
call<Rpc_debouncing_time>(gpio, us);
}
void falling_detect(int gpio, bool enable)
{
call<Rpc_falling_detect>(gpio, enable);
}
void rising_detect(int gpio, bool enable)
{
call<Rpc_rising_detect>(gpio, enable);
}
void irq_enable(int gpio, bool enable)
{
call<Rpc_irq_enable>(gpio, enable);
}
void irq_sigh(Signal_context_capability cap, int gpio)
{
call<Rpc_irq_sigh>(cap, gpio);
}
void direction(Direction d) { call<Rpc_direction>(d); }
void write(bool level) { call<Rpc_write>(level); }
bool read() { return call<Rpc_read>(); }
void debouncing(unsigned int us) { call<Rpc_debouncing>(us); }
void irq_type(Irq_type it) { call<Rpc_irq_type>(it); }
void irq_enable(bool enable) { call<Rpc_irq_enable>(enable); }
void irq_sigh(Genode::Signal_context_capability cap) {
call<Rpc_irq_sigh>(cap); }
};
}
#endif /* _INCLUDE__GPIO_SESSION_H__CLIENT_H_ */
#endif /* _INCLUDE__GPIO_SESSION_H__CLIENT_H_ */

9
os/include/gpio_session/connection.h
View File

@ -1,6 +1,7 @@
/*
* \brief Connection to Gpio session
* \author Ivan Loskutov <ivan.loskutov@ksyslabs.org>
* \author Stefan Kalkowski <stefan.kalkowski@genode-labs.com>
* \date 2012-06-23
*/
@ -22,11 +23,9 @@ namespace Gpio {
struct Connection : Genode::Connection<Session>, Session_client
{
Connection()
:
Genode::Connection<Session>(session("ram_quota=4K")),
Session_client(cap())
{ }
Connection(unsigned long gpio_pin)
: Genode::Connection<Session>(session("ram_quota=8K, gpio=%zd", gpio_pin)),
Session_client(cap()) { }
};
}

161
os/include/gpio_session/gpio_session.h
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@ -1,6 +1,7 @@
/*
* \brief Gpio session interface
* \author Ivan Loskutov <ivan.loskutov@ksyslabs.org>
* \author Stefan Kalkowski <stefan.kalkowski@genode-labs.com>
* \date 2012-06-23
*/
@ -21,126 +22,82 @@
namespace Gpio {
using namespace Genode;
struct Session : Genode::Session
{
static const char *service_name() { return "Gpio"; }
enum Direction { IN, OUT };
enum Irq_type { LOW_LEVEL, HIGH_LEVEL, FALLING_EDGE, RISING_EDGE };
virtual ~Session() { }
/**
* Configure direction on a specified GPIO pin as output
*
* \param gpio number of the pin
* \param enable logic level on the pin
*/
virtual void direction_output(int gpio, bool enable) = 0;
/**
* Configure direction on a specified GPIO pin as input
*
* \param gpio number of the pin
*/
virtual void direction_input(int gpio) = 0;
/**
* Set the logic level on a specified GPIO pin
*
* \param gpio number of the pin
* \param enable logic level on the pin
*/
virtual void dataout(int gpio, bool enable) = 0;
/**
* Read the logic level on a specified GPIO pin
*
* \param gpio number of the pin
*
* \return level on specified GPIO pin
*/
virtual int datain(int gpio) = 0;
/**
* Enable the debounce on a specified input GPIO pin
*
* \param gpio number of the pin
*/
virtual void debounce_enable(int gpio, bool enable) = 0;
/**
* Set the debouncing time for all input pins of GPIO bank
* Configure direction of the GPIO pin
*
* \param gpio number of the pin
* \param d direction of the pin
*/
virtual void debouncing_time(int gpio, unsigned int us) = 0;
/**
* Configure the interrupt request on occurence of a falling edge on
* a specified input GPIO pin
*
* \param gpio number of the pin
*/
virtual void falling_detect(int gpio, bool enable) = 0;
/**
* Configure the interrupt request on occurence of a rising edge on
* a specified input GPIO pin
*
* \param gpio number of the pin
*/
virtual void rising_detect(int gpio, bool enable) = 0;
/**
* Enable or disable the interrupt on a specified GPIO pin
*
* \param gpio number of the pin
* \param enable interrupt status( true - enable, false - disable)
*/
virtual void irq_enable(int gpio, bool enable) = 0;
virtual void direction(Direction d) = 0;
/**
* Register signal handler to be notified on interrupt on a specified
* GPIO pin
*
* \param cap capability of signal-context to handle GPIO
* interrupt
* \param gpio number of the pin
*
* This function is used for a set up signal handler for a specified
* GPIO interrupt. Signal emited to the client if IRQ on pin configured
* when the driver handles this IRQ.
* Write the logic level of the GPIO pin
*
* \param enable logic level on the pin
*/
virtual void irq_sigh(Signal_context_capability cap, int gpio) = 0;
virtual void write(bool enable) = 0;
/**
* Read the logic level on a specified GPIO pin
*
* \return level on specified GPIO pin
*/
virtual bool read() = 0;
/**
* Set the debouncing time
*
* \param us debouncing time in microseconds, zero means no debouncing
*/
virtual void debouncing(unsigned int us) = 0;
/**
* Configure the type of interrupt for the GPIO pin
*
* \param it type of IRQ
*/
virtual void irq_type(Irq_type it) = 0;
/**
* Enable or disable the interrupt of the GPIO pin
*
* \param enable interrupt status( true - enable, false - disable)
*/
virtual void irq_enable(bool enable) = 0;
/**
* Register signal handler to be notified on interrupt
*
* \param cap capability of signal-context to handle GPIO interrupt
*/
virtual void irq_sigh(Genode::Signal_context_capability cap) = 0;
/*******************
** RPC interface **
*******************/
GENODE_RPC(Rpc_direction_output, void, direction_output, int, bool);
GENODE_RPC(Rpc_direction_input, void, direction_input, int);
GENODE_RPC(Rpc_dataout, void, dataout, int, bool);
GENODE_RPC(Rpc_datain, int, datain, int);
GENODE_RPC(Rpc_debounce_enable, void, debounce_enable, int, bool);
GENODE_RPC(Rpc_debouncing_time, void, debouncing_time, int, unsigned int);
GENODE_RPC(Rpc_falling_detect, void, falling_detect, int, bool);
GENODE_RPC(Rpc_rising_detect, void, rising_detect, int, bool);
GENODE_RPC(Rpc_irq_enable, void, irq_enable, int, bool);
GENODE_RPC(Rpc_irq_sigh, void, irq_sigh, Signal_context_capability, int);
GENODE_RPC(Rpc_direction, void, direction, Direction);
GENODE_RPC(Rpc_write, void, write, bool);
GENODE_RPC(Rpc_read, bool, read);
GENODE_RPC(Rpc_debouncing, void, debouncing, unsigned int);
GENODE_RPC(Rpc_irq_type, void, irq_type, Irq_type);
GENODE_RPC(Rpc_irq_enable, void, irq_enable, bool);
GENODE_RPC(Rpc_irq_sigh, void, irq_sigh, Genode::Signal_context_capability);
typedef Meta::Type_tuple<Rpc_direction_output,
Meta::Type_tuple<Rpc_direction_input,
Meta::Type_tuple<Rpc_dataout,
Meta::Type_tuple<Rpc_datain,
Meta::Type_tuple<Rpc_debounce_enable,
Meta::Type_tuple<Rpc_debouncing_time,
Meta::Type_tuple<Rpc_falling_detect,
Meta::Type_tuple<Rpc_rising_detect,
Meta::Type_tuple<Rpc_irq_enable,
Meta::Type_tuple<Rpc_irq_sigh,
Meta::Empty>
> > > > > > > > > Rpc_functions;
GENODE_RPC_INTERFACE(Rpc_direction, Rpc_write, Rpc_read,
Rpc_debouncing, Rpc_irq_type, Rpc_irq_enable,
Rpc_irq_sigh);
};
}

545
os/src/drivers/gpio/imx53/driver.h
View File

@ -2,12 +2,13 @@
* \brief Gpio driver for the i.MX53
* \author Ivan Loskutov <ivan.loskutov@ksyslabs.org>
* \author Nikolay Golikov <nik@ksyslabs.org>
* \author Stefan Kalkowski <stefan.kalkowski@genode-labs.com>
* \date 2012-12-04
*/
/*
* Copyright (C) 2012 Ksys Labs LLC
* Copyright (C) 2012 Genode Labs GmbH
* Copyright (C) 2012-2013 Genode Labs GmbH
*
* This file is part of the Genode OS framework, which is distributed
* under the terms of the GNU General Public License version 2.
@ -17,391 +18,273 @@
#define _DRIVER_H_
/* Genode includes */
#include <os/attached_io_mem_dataspace.h>
#include <drivers/board_base.h>
#include <gpio/driver.h>
#include <irq_session/connection.h>
#include <timer_session/connection.h>
#include <util/mmio.h>
#include <base/signal.h>
/* local includes */
#include "gpio.h"
namespace Gpio {
using namespace Genode;
class Driver;
}
static int verbose = 0;
class Gpio::Driver
{
public:
enum {
GPIO1L_IRQ = 50,
GPIO1H_IRQ = 51,
GPIO2L_IRQ = 52,
GPIO2H_IRQ = 53,
GPIO3L_IRQ = 54,
GPIO3H_IRQ = 55,
GPIO4L_IRQ = 56,
GPIO4H_IRQ = 57,
GPIO5L_IRQ = 103,
GPIO5H_IRQ = 104,
GPIO6L_IRQ = 105,
GPIO6H_IRQ = 106,
GPIO7L_IRQ = 107,
GPIO7H_IRQ = 108,
};
class Imx53_driver : public Gpio::Driver
{
private:
struct Timer_delayer : Timer::Connection, Mmio::Delayer
enum {
MAX_BANKS = 7,
MAX_PINS = 32
};
struct Timer_delayer : Timer::Connection, Genode::Mmio::Delayer
{
/**
* Implementation of 'Delayer' interface
*/
void usleep(unsigned us)
{
/* polling */
if (us == 0)
return;
unsigned ms = us / 1000;
if (ms == 0)
ms = 1;
Timer::Connection::msleep(ms);
}
void usleep(unsigned us) { Timer::Connection::usleep(us); }
} _delayer;
/* memory map */
enum {
GPIO1_MMIO_BASE = 0x53f84000,
GPIO1_MMIO_SIZE = 0x4000,
GPIO2_MMIO_BASE = 0x53f88000,
GPIO2_MMIO_SIZE = 0x4000,
class Gpio_bank
{
public:
GPIO3_MMIO_BASE = 0x53f8c000,
GPIO3_MMIO_SIZE = 0x4000,
void handle_irq();
GPIO4_MMIO_BASE = 0x53f90000,
GPIO4_MMIO_SIZE = 0x4000,
private:
GPIO5_MMIO_BASE = 0x53fdc000,
GPIO5_MMIO_SIZE = 0x4000,
class Irq_handler : public Genode::Thread<4096>
{
private:
GPIO6_MMIO_BASE = 0x53fe0000,
GPIO6_MMIO_SIZE = 0x4000,
Genode::Irq_connection _irq;
Gpio_bank *_bank;
GPIO7_MMIO_BASE = 0x53fe4000,
GPIO7_MMIO_SIZE = 0x4000,
public:
NR_GPIOS = 7,
MAX_GPIOS = 224,
Irq_handler(unsigned irq, Gpio_bank *bank)
: Genode::Thread<4096>("irq handler"),
_irq(irq), _bank(bank) { start(); }
void entry()
{
while (true) {
_irq.wait_for_irq();
_bank->handle_irq();
}
}
};
Gpio_reg _reg;
Irq_handler _irqh_low;
Irq_handler _irqh_high;
Genode::Signal_context_capability _sig_cap[MAX_PINS];
bool _irq_enabled[MAX_PINS];
Genode::Lock _lock;
public:
Gpio_bank(Genode::addr_t base, Genode::size_t size,
unsigned irq_low, unsigned irq_high)
: _reg(base, size),
_irqh_low(irq_low, this),
_irqh_high(irq_high, this) { }
Gpio_reg* regs() { return &_reg; }
void irq(int pin, bool enable)
{
_reg.write<Gpio_reg::Int_mask>(enable ? 1 : 0, pin);
_irq_enabled[pin] = enable;
}
void sigh(int pin, Genode::Signal_context_capability cap) {
_sig_cap[pin] = cap; }
};
Attached_io_mem_dataspace _gpio1_mmio;
Gpio_reg _gpio1;
Attached_io_mem_dataspace _gpio2_mmio;
Gpio_reg _gpio2;
Attached_io_mem_dataspace _gpio3_mmio;
Gpio_reg _gpio3;
Attached_io_mem_dataspace _gpio4_mmio;
Gpio_reg _gpio4;
Attached_io_mem_dataspace _gpio5_mmio;
Gpio_reg _gpio5;
Attached_io_mem_dataspace _gpio6_mmio;
Gpio_reg _gpio6;
Attached_io_mem_dataspace _gpio7_mmio;
Gpio_reg _gpio7;
static Gpio_bank _gpio_bank[MAX_BANKS];
Gpio_reg* _gpio_bank[NR_GPIOS];
int _gpio_bank_index(int gpio) { return gpio >> 5; }
int _gpio_index(int gpio) { return gpio & 0x1f; }
bool _irq_enabled[MAX_GPIOS];
Signal_context_capability _sign[MAX_GPIOS];
struct Debounce_stat
Imx53_driver()
{
unsigned int us;
bool enable;
Debounce_stat() : us(0), enable(false) { }
} _debounce_stat[MAX_GPIOS];
for (unsigned i = 0; i < MAX_BANKS; ++i) {
Gpio_reg *regs = _gpio_bank[i].regs();
for (unsigned j = 0; j < MAX_PINS; j++) {
regs->write<Gpio_reg::Int_conf>(Gpio_reg::Int_conf::LOW_LEVEL, j);
regs->write<Gpio_reg::Int_mask>(0, j);
}
regs->write<Gpio_reg::Int_stat>(0xffffffff);
}
}
public:
Driver();
static Imx53_driver& factory();
bool set_gpio_direction(int gpio, bool is_input);
bool set_gpio_dataout(int gpio, bool enable);
int get_gpio_datain(int gpio);
bool set_gpio_debounce_enable(int gpio, bool enable);
bool set_gpio_debouncing_time(int gpio, unsigned int us);
bool set_gpio_falling_detect(int gpio, bool enable);
bool set_gpio_rising_detect(int gpio, bool enable);
bool set_gpio_irq_enable(int gpio, bool enable);
void register_signal(Signal_context_capability cap, int gpio)
/******************************
** Gpio::Driver interface **
******************************/
void direction(unsigned gpio, bool input)
{
if (!_sign[gpio].valid()) {
_sign[gpio] = cap;
}
if (verbose) PDBG("gpio=%d input=%d", gpio, input);
Gpio_reg *gpio_reg = _gpio_bank[_gpio_bank_index(gpio)].regs();
gpio_reg->write<Gpio_reg::Dir>(input ? 0 : 1,
_gpio_index(gpio));
}
void handle_event(int irq_number);
private:
Gpio_reg *_get_gpio_bank(int gpio) { return _gpio_bank[gpio >> 5]; }
bool _gpio_valid(int gpio) { return (gpio < MAX_GPIOS) ? true : false; }
int _get_gpio_index(int gpio) { return gpio & 0x1f; }
inline void _irq_signal_send(int gpio)
void write(unsigned gpio, bool level)
{
if (_sign[gpio].valid()) {
if (verbose)
PDBG("gpio=%d", gpio);
if (verbose) PDBG("gpio=%d level=%d", gpio, level);
Signal_transmitter transmitter(_sign[gpio]);
transmitter.submit();
}
Gpio_reg *gpio_reg = _gpio_bank[_gpio_bank_index(gpio)].regs();
gpio_reg->write<Gpio_reg::Data>(level ? 1 : 0,
_gpio_index(gpio));
}
inline void _irq_event(int gpio_bank, uint32_t status)
bool read(unsigned gpio)
{
for (int i=0; i<32; i++) {
if ((status & (1 << i)) && _irq_enabled[(gpio_bank<<5) + i])
_irq_signal_send( (gpio_bank<<5) + i );
}
if (verbose) PDBG("gpio=%d", gpio);
Gpio_reg *gpio_reg = _gpio_bank[_gpio_bank_index(gpio)].regs();
return gpio_reg->read<Gpio_reg::Pad_stat>(_gpio_index(gpio));
}
void debounce_enable(unsigned gpio, bool enable)
{
PWRN("Not supported!");
}
void debounce_time(unsigned gpio, unsigned long us)
{
PWRN("Not supported!");
}
void falling_detect(unsigned gpio)
{
if (verbose) PDBG("gpio=%d", gpio);
Gpio_reg *gpio_reg = _gpio_bank[_gpio_bank_index(gpio)].regs();
gpio_reg->write<Gpio_reg::Int_conf>(Gpio_reg::Int_conf::FAL_EDGE,
_gpio_index(gpio));
}
void rising_detect(unsigned gpio)
{
if (verbose) PDBG("gpio=%d", gpio);
Gpio_reg *gpio_reg = _gpio_bank[_gpio_bank_index(gpio)].regs();
gpio_reg->write<Gpio_reg::Int_conf>(Gpio_reg::Int_conf::RIS_EDGE,
_gpio_index(gpio));
}
void high_detect(unsigned gpio)
{
if (verbose) PDBG("gpio=%d", gpio);
Gpio_reg *gpio_reg = _gpio_bank[_gpio_bank_index(gpio)].regs();
gpio_reg->write<Gpio_reg::Int_conf>(Gpio_reg::Int_conf::HIGH_LEVEL,
_gpio_index(gpio));
}
void low_detect(unsigned gpio)
{
if (verbose) PDBG("gpio=%d", gpio);
Gpio_reg *gpio_reg = _gpio_bank[_gpio_bank_index(gpio)].regs();
gpio_reg->write<Gpio_reg::Int_conf>(Gpio_reg::Int_conf::LOW_LEVEL,
_gpio_index(gpio));
}
void irq_enable(unsigned gpio, bool enable)
{
if (verbose) PDBG("gpio=%d enable=%d", gpio, enable);
_gpio_bank[_gpio_bank_index(gpio)].irq(_gpio_index(gpio), enable);
}
void register_signal(unsigned gpio,
Genode::Signal_context_capability cap)
{
if (verbose) PDBG("gpio=%d", gpio);
_gpio_bank[_gpio_bank_index(gpio)].sigh(_gpio_index(gpio), cap); }
void unregister_signal(unsigned gpio)
{
if (verbose) PDBG("gpio=%d", gpio);
Genode::Signal_context_capability cap;
_gpio_bank[_gpio_bank_index(gpio)].sigh(_gpio_index(gpio), cap);
}
bool gpio_valid(unsigned gpio) { return gpio < (MAX_PINS*MAX_BANKS); }
};
Gpio::Driver::Driver()
:
_gpio1_mmio(GPIO1_MMIO_BASE, GPIO1_MMIO_SIZE),
_gpio1((addr_t)_gpio1_mmio.local_addr<void>()),
_gpio2_mmio(GPIO2_MMIO_BASE, GPIO2_MMIO_SIZE),
_gpio2((addr_t)_gpio2_mmio.local_addr<void>()),
_gpio3_mmio(GPIO3_MMIO_BASE, GPIO3_MMIO_SIZE),
_gpio3((addr_t)_gpio3_mmio.local_addr<void>()),
_gpio4_mmio(GPIO4_MMIO_BASE, GPIO4_MMIO_SIZE),
_gpio4((addr_t)_gpio4_mmio.local_addr<void>()),
_gpio5_mmio(GPIO5_MMIO_BASE, GPIO5_MMIO_SIZE),
_gpio5((addr_t)_gpio5_mmio.local_addr<void>()),
_gpio6_mmio(GPIO6_MMIO_BASE, GPIO6_MMIO_SIZE),
_gpio6((addr_t)_gpio6_mmio.local_addr<void>()),
_gpio7_mmio(GPIO7_MMIO_BASE, GPIO7_MMIO_SIZE),
_gpio7((addr_t)_gpio7_mmio.local_addr<void>())
Imx53_driver::Gpio_bank Imx53_driver::_gpio_bank[Imx53_driver::MAX_BANKS] = {
Gpio_bank(Genode::Board_base::GPIO1_MMIO_BASE,
Genode::Board_base::GPIO1_MMIO_SIZE,
Genode::Board_base::GPIO1_IRQL,
Genode::Board_base::GPIO1_IRQH),
Gpio_bank(Genode::Board_base::GPIO2_MMIO_BASE,
Genode::Board_base::GPIO2_MMIO_SIZE,
Genode::Board_base::GPIO2_IRQL,
Genode::Board_base::GPIO2_IRQH),
Gpio_bank(Genode::Board_base::GPIO3_MMIO_BASE,
Genode::Board_base::GPIO3_MMIO_SIZE,
Genode::Board_base::GPIO3_IRQL,
Genode::Board_base::GPIO3_IRQH),
Gpio_bank(Genode::Board_base::GPIO4_MMIO_BASE,
Genode::Board_base::GPIO4_MMIO_SIZE,
Genode::Board_base::GPIO4_IRQL,
Genode::Board_base::GPIO4_IRQH),
Gpio_bank(Genode::Board_base::GPIO5_MMIO_BASE,
Genode::Board_base::GPIO5_MMIO_SIZE,
Genode::Board_base::GPIO5_IRQL,
Genode::Board_base::GPIO5_IRQH),
Gpio_bank(Genode::Board_base::GPIO6_MMIO_BASE,
Genode::Board_base::GPIO6_MMIO_SIZE,
Genode::Board_base::GPIO6_IRQL,
Genode::Board_base::GPIO6_IRQH),
Gpio_bank(Genode::Board_base::GPIO7_MMIO_BASE,
Genode::Board_base::GPIO7_MMIO_SIZE,
Genode::Board_base::GPIO7_IRQL,
Genode::Board_base::GPIO7_IRQH),
};
Imx53_driver& Imx53_driver::factory()
{
_gpio_bank[0] = &_gpio1;
_gpio_bank[1] = &_gpio2;
_gpio_bank[2] = &_gpio3;
_gpio_bank[3] = &_gpio4;
_gpio_bank[4] = &_gpio5;
_gpio_bank[5] = &_gpio6;
_gpio_bank[6] = &_gpio7;
for (int i = 0; i < MAX_GPIOS; ++i) {
Gpio_reg *gpio_reg = _get_gpio_bank(i);
gpio_reg->write<Gpio_reg::Int_conf::Pin>(Gpio_reg::Int_conf::HIGH_LEVEL,
_get_gpio_index(i));
}
static Imx53_driver driver;
return driver;
}
bool Gpio::Driver::set_gpio_direction(int gpio, bool is_input)
void Imx53_driver::Gpio_bank::handle_irq()
{
if (verbose) {
PDBG("gpio=%d is_input=%d", gpio, is_input);
Genode::Lock::Guard lock_guard(_lock);
unsigned long status = _reg.read<Gpio_reg::Int_stat>();
for(unsigned i = 0; i < MAX_PINS; i++) {
if ((status & (1 << i)) && _irq_enabled[i] &&
_sig_cap[i].valid())
Genode::Signal_transmitter(_sig_cap[i]).submit();
}
if (!_gpio_valid(gpio))
return false;
Gpio_reg *gpio_reg = _get_gpio_bank(gpio);
if (is_input)
gpio_reg->write<Gpio_reg::Dir::Pin>(0, _get_gpio_index(gpio));
else
gpio_reg->write<Gpio_reg::Dir::Pin>(1, _get_gpio_index(gpio));
return true;
_reg.write<Gpio_reg::Int_stat>(0xffffffff);
}
bool Gpio::Driver::set_gpio_dataout(int gpio, bool enable)
{
if (verbose)
PDBG("gpio=%d enable=%d", gpio, enable);
if (!_gpio_valid(gpio))
return false;
Gpio_reg *gpio_reg = _get_gpio_bank(gpio);
if (enable)
gpio_reg->write<Gpio_reg::Data::Pin>(1, _get_gpio_index(gpio));
else
gpio_reg->write<Gpio_reg::Data::Pin>(0, _get_gpio_index(gpio));
return true;
}
int Gpio::Driver::get_gpio_datain(int gpio)
{
if (verbose)
PDBG("gpio=%d", gpio);
if (!_gpio_valid(gpio))
return -1;
Gpio_reg *gpio_reg = _get_gpio_bank(gpio);
if (_debounce_stat[gpio].enable)
_delayer.usleep(_debounce_stat[gpio].us);
return gpio_reg->read<Gpio_reg::Pad_stat::Pin>(_get_gpio_index(gpio));
}
bool Gpio::Driver::set_gpio_debounce_enable(int gpio, bool enable)
{
if (verbose)
PDBG("gpio=%d enable=%d", gpio, enable);
if (!_gpio_valid(gpio))
return false;
_debounce_stat[gpio].enable = enable;
return true;
}
bool Gpio::Driver::set_gpio_debouncing_time(int gpio, unsigned int us)
{
if (verbose)
PDBG("gpio=%d us=%d", gpio, us);
if (!_gpio_valid(gpio))
return false;
_debounce_stat[gpio].us = us;
return true;
}
bool Gpio::Driver::set_gpio_falling_detect(int gpio, bool enable)
{
if (verbose)
PDBG("gpio=%d enable=%d", gpio, enable);
if (!_gpio_valid(gpio))
return false;
Gpio_reg *gpio_reg = _get_gpio_bank(gpio);
if (enable)
gpio_reg->write<Gpio_reg::Int_conf::Pin>(Gpio_reg::Int_conf::FAL_EDGE,
_get_gpio_index(gpio));
else
gpio_reg->write<Gpio_reg::Int_conf::Pin>(Gpio_reg::Int_conf::HIGH_LEVEL,
_get_gpio_index(gpio));
return true;
}
bool Gpio::Driver::set_gpio_rising_detect(int gpio, bool enable)
{
if (verbose)
PDBG("gpio=%d enable=%d", gpio, enable);
if (!_gpio_valid(gpio))
return false;
Gpio_reg *gpio_reg = _get_gpio_bank(gpio);
if (enable)
gpio_reg->write<Gpio_reg::Int_conf::Pin>(Gpio_reg::Int_conf::RIS_EDGE,
_get_gpio_index(gpio));
else
gpio_reg->write<Gpio_reg::Int_conf::Pin>(Gpio_reg::Int_conf::HIGH_LEVEL,
_get_gpio_index(gpio));
return true;
}
bool Gpio::Driver::set_gpio_irq_enable(int gpio, bool enable)
{
if (verbose)
PDBG("gpio=%d enable=%d", gpio, enable);
if (!_gpio_valid(gpio))
return false;
Gpio_reg *gpio_reg = _get_gpio_bank(gpio);
if (enable)
gpio_reg->write<Gpio_reg::Int_mask::Pin>(1, _get_gpio_index(gpio));
else
gpio_reg->write<Gpio_reg::Int_mask::Pin>(0, _get_gpio_index(gpio));
_irq_enabled[gpio] = enable;
return true;
}
void Gpio::Driver::handle_event(int irq_number)
{
if (verbose)
PDBG("IRQ #%d\n", irq_number);
int gpio_bank = 0;
switch (irq_number) {
case GPIO1L_IRQ:
case GPIO1H_IRQ:
gpio_bank = 0;
break;
case GPIO2L_IRQ:
case GPIO2H_IRQ:
gpio_bank = 1;
break;
case GPIO3L_IRQ:
case GPIO3H_IRQ:
gpio_bank = 2;
break;
case GPIO4L_IRQ:
case GPIO4H_IRQ:
gpio_bank = 3;
break;
case GPIO5L_IRQ:
case GPIO5H_IRQ:
gpio_bank = 4;
break;
case GPIO6L_IRQ:
case GPIO6H_IRQ:
gpio_bank = 5;
break;
case GPIO7L_IRQ:
case GPIO7H_IRQ:
gpio_bank = 6;
break;
default:
PERR("Unknown Irq number!\n");
return;
}
int stat = _gpio_bank[gpio_bank]->read<Gpio_reg::Int_stat>();
if (verbose)
PDBG("GPIO1 IRQSTATUS=%08x\n", stat);
_irq_event(gpio_bank, stat);
_gpio_bank[gpio_bank]->write<Gpio_reg::Int_stat>(0xffffffff);
}
#endif /* _DRIVER_H_ */

52
os/src/drivers/gpio/imx53/gpio.h
View File

@ -1,12 +1,13 @@
/*
* \brief Gpio driver for the i.MX53
* \author Nikolay Golikov <nik@ksyslabs.org>
* \author Stefan Kalkowski <stefan.kalkowski@genode-labs.com>
* \date 2012-12-06
*/
/*
* Copyright (C) 2012 Ksys Labs LLC
* Copyright (C) 2012 Genode Labs GmbH
* Copyright (C) 2012-2013 Genode Labs GmbH
*
* This file is part of the Genode OS framework, which is distributed
* under the terms of the GNU General Public License version 2.
@ -15,30 +16,20 @@
#ifndef _GPIO_H_
#define _GPIO_H_
/* Genode includes */
#include <os/attached_io_mem_dataspace.h>
#include <util/mmio.h>
struct Gpio_reg : Genode::Mmio
struct Gpio_reg : Genode::Attached_io_mem_dataspace, Genode::Mmio
{
Gpio_reg(Genode::addr_t const mmio_base) : Genode::Mmio(mmio_base) { }
struct Data : Register_array<0x0, 32, 32, 1>
{
struct Pin : Bitfield<0, 1> { };
};
struct Dir : Register_array<0x4, 32, 32, 1>
{
struct Pin : Bitfield<0, 1> { };
};
struct Pad_stat : Register_array<0x8, 32, 32, 1>
{
struct Pin : Bitfield<0, 1> { };
};
Gpio_reg(Genode::addr_t const mmio_base,
Genode::size_t const mmio_size)
: Genode::Attached_io_mem_dataspace(mmio_base, mmio_size),
Genode::Mmio((Genode::addr_t)local_addr<void>()) { }
struct Data : Register_array<0x0, 32, 32, 1> {};
struct Dir : Register_array<0x4, 32, 32, 1> {};
struct Pad_stat : Register_array<0x8, 32, 32, 1> {};
struct Int_conf : Register_array<0xc, 32, 32, 2>
{
enum {
@ -47,24 +38,11 @@ struct Gpio_reg : Genode::Mmio
RIS_EDGE,
FAL_EDGE
};
struct Pin : Bitfield<0, 2> { };
};
struct Int_mask : Register_array<0x14, 32, 32, 1>
{
struct Pin : Bitfield<0, 1> { };
};
struct Int_stat : Register_array<0x18, 32, 32, 1>
{
struct Pin : Bitfield<0, 1> { };
};
struct Edge_sel : Register_array<0x1c, 32, 32, 1>
{
struct Pin : Bitfield<0, 1> { };
};
struct Int_mask : Register_array<0x14, 32, 32, 1> {};
struct Int_stat : Register_array<0x18, 32, 32, 1> {};
struct Edge_sel : Register_array<0x1c, 32, 32, 1> {};
};
#endif
#endif /* _GPIO_H_ */

50
os/src/drivers/gpio/imx53/irq_handler.h
View File

@ -1,50 +0,0 @@
/*
* \brief Gpio irq-handler
* \author Ivan Loskutov <ivan.loskutov@ksyslabs.org>
* \date 2012-06-23
*/
/*
* Copyright (C) 2012 Ksys Labs LLC
* Copyright (C) 2012 Genode Labs GmbH
*
* This file is part of the Genode OS framework, which is distributed
* under the terms of the GNU General Public License version 2.
*/
#ifndef _IRQ_HANDLER_H_
#define _IRQ_HANDLER_H_
/* Genode includes */
#include <base/thread.h>
#include <irq_session/connection.h>
/* local includes */
#include "driver.h"
class Irq_handler : Genode::Thread<4096>
{
private:
int _irq_number;
Genode::Irq_connection _irq;
Gpio::Driver &_driver;
public:
Irq_handler(int irq_number, Gpio::Driver &driver)
: _irq_number(irq_number), _irq(irq_number), _driver(driver)
{
start();
}
void entry()
{
while (1) {
_driver.handle_event(_irq_number);
_irq.wait_for_irq();
}
}
};
#endif /* _IRQ_HANDLER_H_ */

195
os/src/drivers/gpio/imx53/main.cc
View File

@ -2,219 +2,46 @@
* \brief Gpio driver for the i.MX53
* \author Ivan Loskutov <ivan.loskutov@ksyslabs.org>
* \author Nikolay Golikov <nik@ksyslabs.org>
* \author Stefan Kalkowski <stefan.kalkowski@genode-labs.com>
* \date 2012-12-09
*/
/*
* Copyright (C) 2012 Ksys Labs LLC
* Copyright (C) 2012 Genode Labs GmbH
* Copyright (C) 2012-2013 Genode Labs GmbH
*
* This file is part of the Genode OS framework, which is distributed
* under the terms of the GNU General Public License version 2.
*/
/* Genode includes */
#include <gpio_session/gpio_session.h>
#include <cap_session/connection.h>
#include <dataspace/client.h>
#include <base/printf.h>
#include <base/sleep.h>
#include <root/component.h>
#include <os/config.h>
#include <os/static_root.h>
#include <util/string.h>
#include <cap_session/connection.h>
#include <gpio/component.h>
#include <gpio/config.h>
/* local includes */
#include "driver.h"
#include "irq_handler.h"
namespace Gpio {
using namespace Genode;
class Session_component;
}
class Gpio::Session_component : public Genode::Rpc_object<Gpio::Session>
{
private:
Driver &_driver;
Signal_context_capability _read_avail_sigh;
public:
Session_component(Driver &driver)
: _driver(driver)
{
}
/************************************
** Gpio::Session interface **
************************************/
void direction_output(int gpio, bool enable)
{
_driver.set_gpio_dataout(gpio, enable);
_driver.set_gpio_direction(gpio, false);
}
void direction_input(int gpio)
{
_driver.set_gpio_direction(gpio, true);
}
void dataout(int gpio, bool enable)
{
_driver.set_gpio_dataout(gpio, enable);
}
int datain(int gpio) { return _driver.get_gpio_datain(gpio); }
void debounce_enable(int gpio, bool enable)
{
_driver.set_gpio_debounce_enable(gpio, enable);
}
void debouncing_time(int gpio, unsigned int us)
{
_driver.set_gpio_debouncing_time(gpio, us);
}
void falling_detect(int gpio, bool enable)
{
_driver.set_gpio_falling_detect(gpio, enable);
}
void rising_detect(int gpio, bool enable)
{
_driver.set_gpio_rising_detect(gpio, enable);
}
void irq_enable(int gpio, bool enable)
{
_driver.set_gpio_irq_enable(gpio, enable);
}
void irq_sigh(Signal_context_capability cap, int gpio)
{
_driver.register_signal(cap, gpio);
}
};
#include <driver.h>
int main(int, char **)
{
using namespace Gpio;
using namespace Genode;
printf("--- i.MX53 gpio driver ---\n");
Driver driver;
Irq_handler gpio1l_irq(Driver::GPIO1L_IRQ, driver);
Irq_handler gpio1h_irq(Driver::GPIO1H_IRQ, driver);
Irq_handler gpio2l_irq(Driver::GPIO2L_IRQ, driver);
Irq_handler gpio2h_irq(Driver::GPIO2H_IRQ, driver);
Irq_handler gpio3l_irq(Driver::GPIO3L_IRQ, driver);
Irq_handler gpio3h_irq(Driver::GPIO3H_IRQ, driver);
Irq_handler gpio4l_irq(Driver::GPIO4L_IRQ, driver);
Irq_handler gpio4h_irq(Driver::GPIO4H_IRQ, driver);
Irq_handler gpio5l_irq(Driver::GPIO5L_IRQ, driver);
Irq_handler gpio5h_irq(Driver::GPIO5H_IRQ, driver);
Irq_handler gpio6l_irq(Driver::GPIO6L_IRQ, driver);
Irq_handler gpio6h_irq(Driver::GPIO6H_IRQ, driver);
Irq_handler gpio7l_irq(Driver::GPIO7L_IRQ, driver);
Irq_handler gpio7h_irq(Driver::GPIO7H_IRQ, driver);
/*
* Configure GPIO
* Example:
* <config>
* <gpio num="123" mode="I"/>
* <gpio num="124" mode="O" value="0"/>
* </config>
*
* num - GPIO pin number
* mode - input(I) or output(O)
* value - output level (1 or 0), only for output mode
*/
try {
Genode::Xml_node gpio_node = Genode::config()->xml_node().sub_node("gpio");
for (;; gpio_node = gpio_node.next("gpio")) {
unsigned num;
char mode[2] = {0};
unsigned value = 0;
bool value_ok;
do {
try {
gpio_node.attribute("num").value(&num);
}
catch (Genode::Xml_node::Nonexistent_attribute)
{
PERR("Missing \"num\" attribute. Ignore node.");
break;
}
try {
gpio_node.attribute("mode").value(mode, sizeof(mode));
}
catch (Genode::Xml_node::Nonexistent_attribute)
{
PERR("Missing \"mode\" attribute. Ignore node.");
break;
}
try {
value_ok = gpio_node.attribute("value").value(&value);
}
catch (Genode::Xml_node::Nonexistent_attribute)
{
value_ok = false;
}
if (mode[0] == 'O' || mode[0] == 'o') {
if (!value_ok) {
PERR("Missing \"value\" attribute for Output mode. Ignore node.");
break;
}
if (value > 1) {
PERR("Incorrect \"value\" attribute for Output mode. Ignore node.");
break;
}
driver.set_gpio_dataout(num, value);
driver.set_gpio_direction(num, false);
} else if (mode[0] == 'I' || mode[0] == 'i') {
driver.set_gpio_direction(num, true);
} else {
PERR("Incorrect value of \"mode\" attribute. Ignore node.");
break;
}
PDBG("gpio %d mode %s value=%s",
num, mode, value_ok ? (value==0 ? "0" : value==1 ? "1" : "error") : "-");
} while (0);
if (gpio_node.is_last("gpio")) break;
}
}
catch (Genode::Xml_node::Nonexistent_sub_node) {
PERR("No GPIO config");
}
Imx53_driver &driver = Imx53_driver::factory();
Gpio::process_config(driver);
/*
* Initialize server entry point
*/
enum { STACK_SIZE = 4096 };
static Cap_connection cap;
Sliced_heap sliced_heap(env()->ram_session(), env()->rm_session());
static Rpc_entrypoint ep(&cap, STACK_SIZE, "gpio_ep");
/*
* Let the entry point serve the gpio session and root interfaces
*/
static Session_component gpio_session(driver);
static Static_root<Gpio::Session> gpio_root(ep.manage(&gpio_session));
static Gpio::Root gpio_root(&ep, &sliced_heap, driver);
/*
* Announce service

584
os/src/drivers/gpio/omap4/driver.h
View File

@ -1,6 +1,7 @@
/*
* \brief Gpio driver for the OMAP4
* \author Ivan Loskutov <ivan.loskutov@ksyslabs.org>
* \author Stefan Kalkowski <stefan.kalkowski@genode-labs.com>
* \date 2012-06-23
*/
@ -16,37 +17,28 @@
#define _DRIVER_H_
/* Genode includes */
#include <os/attached_io_mem_dataspace.h>
#include <drivers/board_base.h>
#include <gpio/driver.h>
#include <irq_session/connection.h>
#include <timer_session/connection.h>
#include <util/mmio.h>
#include <base/signal.h>
/* local includes */
#include "gpio.h"
namespace Gpio {
using namespace Genode;
class Driver;
}
static int verbose = 0;
class Gpio::Driver
{
public:
enum {
GPIO1_IRQ = 29 + 32,
GPIO2_IRQ = 30 + 32,
GPIO3_IRQ = 31 + 32,
GPIO4_IRQ = 32 + 32,
GPIO5_IRQ = 33 + 32,
GPIO6_IRQ = 34 + 32,
};
class Omap4_driver : public Gpio::Driver
{
private:
struct Timer_delayer : Timer::Connection, Mmio::Delayer
enum {
MAX_BANKS = 6,
MAX_PINS = 32
};
struct Timer_delayer : Timer::Connection, Genode::Mmio::Delayer
{
/**
* Implementation of 'Delayer' interface
@ -54,384 +46,238 @@ class Gpio::Driver
void usleep(unsigned us) { Timer::Connection::usleep(us); }
} _delayer;
/* memory map */
enum {
GPIO1_MMIO_BASE = 0x4a310000,
GPIO1_MMIO_SIZE = 0x1000,
GPIO2_MMIO_BASE = 0x48055000,
GPIO2_MMIO_SIZE = 0x1000,
class Gpio_bank : public Genode::Thread<4096>
{
private:
GPIO3_MMIO_BASE = 0x48057000,
GPIO3_MMIO_SIZE = 0x1000,
Gpio_reg _reg;
Genode::Irq_connection _irq;
Genode::Signal_context_capability _sig_cap[MAX_PINS];
bool _irq_enabled[MAX_PINS];
GPIO4_MMIO_BASE = 0x48059000,
GPIO4_MMIO_SIZE = 0x1000,
public:
GPIO5_MMIO_BASE = 0x4805b000,
GPIO5_MMIO_SIZE = 0x1000,
Gpio_bank(Genode::addr_t base, Genode::size_t size,
unsigned irq)
: Genode::Thread<4096>("irq handler"),
_reg(base, size), _irq(irq)
{
for (unsigned i = 0; i < MAX_PINS; i++)
_irq_enabled[i] = false;
start();
}
GPIO6_MMIO_BASE = 0x4805d000,
GPIO6_MMIO_SIZE = 0x1000,
void entry()
{
unsigned long status;
NR_GPIOS = 6,
MAX_GPIOS = 192,
while (true) {
_reg.write<Gpio_reg::Irqstatus_0>(0xffffffff);
_irq.wait_for_irq();
status = _reg.read<Gpio_reg::Irqstatus_0>();
for(unsigned i = 0; i < MAX_PINS; i++) {
if ((status & (1 << i)) && _irq_enabled[i] &&
_sig_cap[i].valid())
Genode::Signal_transmitter(_sig_cap[i]).submit();
}
}
}
Gpio_reg* regs() { return &_reg; }
void irq(int pin, bool enable)
{
if (enable) {
_reg.write<Gpio_reg::Irqstatus_0>(1 << pin);
_reg.write<Gpio_reg::Irqstatus_set_0>(1 << pin);
}
else
_reg.write<Gpio_reg::Irqstatus_clr_0>(1 << pin);
_irq_enabled[pin] = enable;
}
void sigh(int pin, Genode::Signal_context_capability cap) {
_sig_cap[pin] = cap; }
};
Attached_io_mem_dataspace _gpio1_mmio;
Gpio_reg _gpio1;
Attached_io_mem_dataspace _gpio2_mmio;
Gpio_reg _gpio2;
Attached_io_mem_dataspace _gpio3_mmio;
Gpio_reg _gpio3;
Attached_io_mem_dataspace _gpio4_mmio;
Gpio_reg _gpio4;
Attached_io_mem_dataspace _gpio5_mmio;
Gpio_reg _gpio5;
Attached_io_mem_dataspace _gpio6_mmio;
Gpio_reg _gpio6;
static Gpio_bank _gpio_bank[MAX_BANKS];
Gpio_reg *_gpio_bank[NR_GPIOS];
int _gpio_bank_index(int gpio) { return gpio >> 5; }
int _gpio_index(int gpio) { return gpio & 0x1f; }
bool irq_enabled[MAX_GPIOS];
Signal_context_capability _sign[MAX_GPIOS];
Omap4_driver()
{
for (int i = 0; i < MAX_BANKS; ++i) {
if (verbose)
PDBG("GPIO%d ctrl=%08x",
i+1, _gpio_bank[i].regs()->read<Gpio_reg::Ctrl>());
}
}
public:
Driver();
static Omap4_driver& factory();
bool set_gpio_direction(int gpio, bool is_input);
bool set_gpio_dataout(int gpio, bool enable);
int get_gpio_datain(int gpio);
bool set_gpio_debounce_enable(int gpio, bool enable);
bool set_gpio_debouncing_time(int gpio, unsigned int us);
bool set_gpio_falling_detect(int gpio, bool enable);
bool set_gpio_rising_detect(int gpio, bool enable);
bool set_gpio_irq_enable(int gpio, bool enable);
void register_signal(Signal_context_capability cap, int gpio)
/******************************
** Gpio::Driver interface **
******************************/
void direction(unsigned gpio, bool input)
{
if (!_sign[gpio].valid())
{
_sign[gpio] = cap;
}
if (verbose) PDBG("gpio=%d input=%d", gpio, input);
Gpio_reg *gpio_reg = _gpio_bank[_gpio_bank_index(gpio)].regs();
gpio_reg->write<Gpio_reg::Oe>(input ? 1 : 0, _gpio_index(gpio));
}
void handle_event(int irq_number);
private:
Gpio_reg *_get_gpio_bank(int gpio) { return _gpio_bank[gpio >> 5]; }
bool _gpio_valid(int gpio) { return (gpio < MAX_GPIOS) ? true : false; }
int _get_gpio_index(int gpio) { return gpio & 0x1f; }
inline void _irq_signal_send(int gpio)
void write(unsigned gpio, bool level)
{
if (_sign[gpio].valid())
{
if (verbose)
PDBG("gpio=%d", gpio);
Signal_transmitter transmitter(_sign[gpio]);
transmitter.submit();
}
if (verbose) PDBG("gpio=%d level=%d", gpio, level);
Gpio_reg *gpio_reg = _gpio_bank[_gpio_bank_index(gpio)].regs();
if (level)
gpio_reg->write<Gpio_reg::Setdataout>(1 << _gpio_index(gpio));
else
gpio_reg->write<Gpio_reg::Cleardataout>(1 << _gpio_index(gpio));
}
inline void _irq_event(int gpio_bank, uint32_t status)
bool read(unsigned gpio)
{
for(int i=0; i<32; i++)
{
if ( (status & (1 << i)) && irq_enabled[(gpio_bank<<5) + i] )
_irq_signal_send( (gpio_bank<<5) + i );
}
if (verbose) PDBG("gpio=%d", gpio);
Gpio_reg *gpio_reg = _gpio_bank[_gpio_bank_index(gpio)].regs();
return gpio_reg->read<Gpio_reg::Datain>(_gpio_index(gpio));
}
void _handle_event_gpio1();
void _handle_event_gpio2();
void _handle_event_gpio3();
void _handle_event_gpio4();
void _handle_event_gpio5();
void _handle_event_gpio6();
void debounce_enable(unsigned gpio, bool enable)
{
if (verbose) PDBG("gpio=%d enable=%d", gpio, enable);
Gpio_reg *gpio_reg = _gpio_bank[_gpio_bank_index(gpio)].regs();
gpio_reg->write<Gpio_reg::Debounceenable>(enable ? 1 : 0,
_gpio_index(gpio));
}
void debounce_time(unsigned gpio, unsigned long us)
{
if (verbose) PDBG("gpio=%d us=%ld", gpio, us);
unsigned char debounce;
if (us < 32)
debounce = 0x01;
else if (us > 7936)
debounce = 0xff;
else
debounce = (us / 0x1f) - 1;
Gpio_reg *gpio_reg = _gpio_bank[_gpio_bank_index(gpio)].regs();
gpio_reg->write<Gpio_reg::Debouncingtime::Time>(debounce);
}
void falling_detect(unsigned gpio)
{
if (verbose) PDBG("gpio=%d", gpio);
Gpio_reg *gpio_reg = _gpio_bank[_gpio_bank_index(gpio)].regs();
gpio_reg->write<Gpio_reg::Leveldetect0> (0, _gpio_index(gpio));
gpio_reg->write<Gpio_reg::Leveldetect1> (0, _gpio_index(gpio));
gpio_reg->write<Gpio_reg::Fallingdetect>(1, _gpio_index(gpio));
gpio_reg->write<Gpio_reg::Risingdetect> (0, _gpio_index(gpio));
}
void rising_detect(unsigned gpio)
{
if (verbose) PDBG("gpio=%d", gpio);
Gpio_reg *gpio_reg = _gpio_bank[_gpio_bank_index(gpio)].regs();
gpio_reg->write<Gpio_reg::Leveldetect0> (0, _gpio_index(gpio));
gpio_reg->write<Gpio_reg::Leveldetect1> (0, _gpio_index(gpio));
gpio_reg->write<Gpio_reg::Fallingdetect>(0, _gpio_index(gpio));
gpio_reg->write<Gpio_reg::Risingdetect> (1, _gpio_index(gpio));
}
void high_detect(unsigned gpio)
{
if (verbose) PDBG("gpio=%d", gpio);
Gpio_reg *gpio_reg = _gpio_bank[_gpio_bank_index(gpio)].regs();
gpio_reg->write<Gpio_reg::Leveldetect0> (0, _gpio_index(gpio));
gpio_reg->write<Gpio_reg::Leveldetect1> (1, _gpio_index(gpio));
gpio_reg->write<Gpio_reg::Fallingdetect>(0, _gpio_index(gpio));
gpio_reg->write<Gpio_reg::Risingdetect> (0, _gpio_index(gpio));
}
void low_detect(unsigned gpio)
{
if (verbose) PDBG("gpio=%d", gpio);
Gpio_reg *gpio_reg = _gpio_bank[_gpio_bank_index(gpio)].regs();
gpio_reg->write<Gpio_reg::Leveldetect0> (1, _gpio_index(gpio));
gpio_reg->write<Gpio_reg::Leveldetect1> (0, _gpio_index(gpio));
gpio_reg->write<Gpio_reg::Fallingdetect>(0, _gpio_index(gpio));
gpio_reg->write<Gpio_reg::Risingdetect> (0, _gpio_index(gpio));
}
void irq_enable(unsigned gpio, bool enable)
{
if (verbose) PDBG("gpio=%d enable=%d", gpio, enable);
_gpio_bank[_gpio_bank_index(gpio)].irq(_gpio_index(gpio), enable);
}
void register_signal(unsigned gpio,
Genode::Signal_context_capability cap)
{
if (verbose) PDBG("gpio=%d", gpio);
_gpio_bank[_gpio_bank_index(gpio)].sigh(_gpio_index(gpio), cap); }
void unregister_signal(unsigned gpio)
{
if (verbose) PDBG("gpio=%d", gpio);
Genode::Signal_context_capability cap;
_gpio_bank[_gpio_bank_index(gpio)].sigh(_gpio_index(gpio), cap);
}
bool gpio_valid(unsigned gpio) { return gpio < (MAX_PINS*MAX_BANKS); }
};
Gpio::Driver::Driver()
:
_gpio1_mmio(GPIO1_MMIO_BASE, GPIO1_MMIO_SIZE),
_gpio1((addr_t)_gpio1_mmio.local_addr<void>()),
_gpio2_mmio(GPIO2_MMIO_BASE, GPIO2_MMIO_SIZE),
_gpio2((addr_t)_gpio2_mmio.local_addr<void>()),
_gpio3_mmio(GPIO3_MMIO_BASE, GPIO3_MMIO_SIZE),
_gpio3((addr_t)_gpio3_mmio.local_addr<void>()),
_gpio4_mmio(GPIO4_MMIO_BASE, GPIO4_MMIO_SIZE),
_gpio4((addr_t)_gpio4_mmio.local_addr<void>()),
_gpio5_mmio(GPIO5_MMIO_BASE, GPIO5_MMIO_SIZE),
_gpio5((addr_t)_gpio5_mmio.local_addr<void>()),
_gpio6_mmio(GPIO6_MMIO_BASE, GPIO6_MMIO_SIZE),
_gpio6((addr_t)_gpio6_mmio.local_addr<void>())
Omap4_driver::Gpio_bank Omap4_driver::_gpio_bank[Omap4_driver::MAX_BANKS] = {
Gpio_bank(Genode::Board_base::GPIO1_MMIO_BASE,
Genode::Board_base::GPIO1_MMIO_SIZE,
Genode::Board_base::GPIO1_IRQ),
Gpio_bank(Genode::Board_base::GPIO2_MMIO_BASE,
Genode::Board_base::GPIO2_MMIO_SIZE,
Genode::Board_base::GPIO2_IRQ),
Gpio_bank(Genode::Board_base::GPIO3_MMIO_BASE,
Genode::Board_base::GPIO3_MMIO_SIZE,
Genode::Board_base::GPIO3_IRQ),
Gpio_bank(Genode::Board_base::GPIO4_MMIO_BASE,
Genode::Board_base::GPIO4_MMIO_SIZE,
Genode::Board_base::GPIO4_IRQ),
Gpio_bank(Genode::Board_base::GPIO5_MMIO_BASE,
Genode::Board_base::GPIO5_MMIO_SIZE,
Genode::Board_base::GPIO5_IRQ),
Gpio_bank(Genode::Board_base::GPIO6_MMIO_BASE,
Genode::Board_base::GPIO6_MMIO_SIZE,
Genode::Board_base::GPIO6_IRQ),
};
Omap4_driver& Omap4_driver::factory()
{
_gpio_bank[0] = &_gpio1;
_gpio_bank[1] = &_gpio2;
_gpio_bank[2] = &_gpio3;
_gpio_bank[3] = &_gpio4;
_gpio_bank[4] = &_gpio5;
_gpio_bank[5] = &_gpio6;
for (int i = 0; i < NR_GPIOS; ++i)
{
uint32_t r = _gpio_bank[i]->read<Gpio_reg::Ctrl>();
if (verbose)
PDBG("GPIO%d ctrl=%08x", i+1, r);
}
}
bool Gpio::Driver::set_gpio_direction(int gpio, bool is_input)
{
if (verbose)
PDBG("gpio=%d is_input=%d", gpio, is_input);
if (!_gpio_valid(gpio))
return false;
Gpio_reg *gpio_reg = _get_gpio_bank(gpio);
uint32_t value = gpio_reg->read<Gpio_reg::Oe>();
if (is_input)
value |= (1 << _get_gpio_index(gpio));
else
value &= ~(1 << _get_gpio_index(gpio));
gpio_reg->write<Gpio_reg::Oe>(value);
return true;
}
bool Gpio::Driver::set_gpio_dataout(int gpio, bool enable)
{
if (verbose)
PDBG("gpio=%d enable=%d", gpio, enable);
if (!_gpio_valid(gpio))
return false;
Gpio_reg *gpio_reg = _get_gpio_bank(gpio);
if (enable)
gpio_reg->write<Gpio_reg::Setdataout>(1 << _get_gpio_index(gpio));
else
gpio_reg->write<Gpio_reg::Cleardataout>(1 << _get_gpio_index(gpio));
return true;
}
int Gpio::Driver::get_gpio_datain(int gpio)
{
if (verbose)
PDBG("gpio=%d", gpio);
if (!_gpio_valid(gpio))
return -1;
Gpio_reg *gpio_reg = _get_gpio_bank(gpio);
uint32_t value = gpio_reg->read<Gpio_reg::Datain>();
return (value & (1 << _get_gpio_index(gpio))) != 0 ;
}
bool Gpio::Driver::set_gpio_debounce_enable(int gpio, bool enable)
{
if (verbose)
PDBG("gpio=%d enable=%d", gpio, enable);
if (!_gpio_valid(gpio))
return false;
Gpio_reg *gpio_reg = _get_gpio_bank(gpio);
uint32_t value = gpio_reg->read<Gpio_reg::Debounceenable>();
if (enable)
value |= (1 << _get_gpio_index(gpio));
else
value &= ~(1 << _get_gpio_index(gpio));
gpio_reg->write<Gpio_reg::Debounceenable>(value);
return true;
}
bool Gpio::Driver::set_gpio_debouncing_time(int gpio, unsigned int us)
{
if (verbose)
PDBG("gpio=%d us=%d", gpio, us);
if (!_gpio_valid(gpio))
return false;
unsigned char debounce;
if (us < 32)
debounce = 0x01;
else if (us > 7936)
debounce = 0xff;
else
debounce = (us / 0x1f) - 1;
Gpio_reg *gpio_reg = _get_gpio_bank(gpio);
gpio_reg->write<Gpio_reg::Debouncingtime::Time>(debounce);
return true;
}
bool Gpio::Driver::set_gpio_falling_detect(int gpio, bool enable)
{
if (verbose)
PDBG("gpio=%d enable=%d", gpio, enable);
if (!_gpio_valid(gpio))
return false;
Gpio_reg *gpio_reg = _get_gpio_bank(gpio);
uint32_t value = gpio_reg->read<Gpio_reg::Fallingdetect>();
if (enable)
value |= (1 << _get_gpio_index(gpio));
else
value &= ~(1 << _get_gpio_index(gpio));
gpio_reg->write<Gpio_reg::Fallingdetect>(value);
return true;
}
bool Gpio::Driver::set_gpio_rising_detect(int gpio, bool enable)
{
if (verbose)
PDBG("gpio=%d enable=%d", gpio, enable);
if (!_gpio_valid(gpio))
return false;
Gpio_reg *gpio_reg = _get_gpio_bank(gpio);
uint32_t value = gpio_reg->read<Gpio_reg::Risingdetect>();
if (enable)
value |= (1 << _get_gpio_index(gpio));
else
value &= ~(1 << _get_gpio_index(gpio));
gpio_reg->write<Gpio_reg::Risingdetect>(value);
return true;
}
bool Gpio::Driver::set_gpio_irq_enable(int gpio, bool enable)
{
if (verbose)
PDBG("gpio=%d enable=%d", gpio, enable);
if (!_gpio_valid(gpio))
return false;
Gpio_reg *gpio_reg = _get_gpio_bank(gpio);
if (enable)
{
gpio_reg->write<Gpio_reg::Irqstatus_0>(1 << _get_gpio_index(gpio));
gpio_reg->write<Gpio_reg::Irqstatus_set_0>(1 << _get_gpio_index(gpio));
irq_enabled[gpio] = true;
}
else
{
gpio_reg->write<Gpio_reg::Irqstatus_clr_0>(1 << _get_gpio_index(gpio));
irq_enabled[gpio] = false;
}
return true;
}
void Gpio::Driver::handle_event(int irq_number)
{
if (verbose)
PDBG("IRQ #%d\n", irq_number-32);
switch(irq_number)
{
case GPIO1_IRQ: _handle_event_gpio1(); break;
case GPIO2_IRQ: _handle_event_gpio2(); break;
case GPIO3_IRQ: _handle_event_gpio3(); break;
case GPIO4_IRQ: _handle_event_gpio4(); break;
case GPIO5_IRQ: _handle_event_gpio5(); break;
case GPIO6_IRQ: _handle_event_gpio6(); break;
}
}
void Gpio::Driver::_handle_event_gpio1()
{
int sts = _gpio1.read<Gpio_reg::Irqstatus_0>();
if (verbose)
PDBG("GPIO1 IRQSTATUS=%08x\n", sts);
_irq_event(0, sts);
_gpio1.write<Gpio_reg::Irqstatus_0>(0xffffffff);
}
void Gpio::Driver::_handle_event_gpio2()
{
int sts = _gpio2.read<Gpio_reg::Irqstatus_0>();
if (verbose)
PDBG("GPIO2 IRQSTATUS=%08x\n", sts);
_irq_event(1, sts);
_gpio2.write<Gpio_reg::Irqstatus_0>(0xffffffff);
}
void Gpio::Driver::_handle_event_gpio3()
{
int sts = _gpio3.read<Gpio_reg::Irqstatus_0>();
if (verbose)
PDBG("GPIO3 IRQSTATUS=%08x\n", sts);
_irq_event(2, sts);
_gpio3.write<Gpio_reg::Irqstatus_0>(0xffffffff);
}
void Gpio::Driver::_handle_event_gpio4()
{
int sts = _gpio4.read<Gpio_reg::Irqstatus_0>();
if (verbose)
PDBG("GPIO4 IRQSTATUS=%08x\n", sts);
_irq_event(3, sts);
_gpio4.write<Gpio_reg::Irqstatus_0>(0xffffffff);
}
void Gpio::Driver::_handle_event_gpio5()
{
int sts = _gpio5.read<Gpio_reg::Irqstatus_0>();
if (verbose)
PDBG("GPIO5 IRQSTATUS=%08x\n", sts);
_irq_event(4, sts);
_gpio5.write<Gpio_reg::Irqstatus_0>(0xffffffff);
}
void Gpio::Driver::_handle_event_gpio6()
{
int sts = _gpio6.read<Gpio_reg::Irqstatus_0>();
if (verbose)
PDBG("GPIO6 IRQSTATUS=%08x\n", sts);
_irq_event(5, sts);
_gpio6.write<Gpio_reg::Irqstatus_0>(0xffffffff);
static Omap4_driver driver;
return driver;
}
#endif /* _DRIVER_H_ */

23
os/src/drivers/gpio/omap4/gpio.h
View File

@ -1,6 +1,7 @@
/*
* \brief OMAP4 GPIO definitions
* \author Ivan Loskutov <ivan.loskutov@ksyslabs.org>
* \author Stefan Kalkowski <stefan.kalkowski@genode-labs.com>
* \date 2012-06-23
*/
@ -16,29 +17,33 @@
#define _GPIO_H_
/* Genode includes */
#include <os/attached_io_mem_dataspace.h>
#include <util/mmio.h>
struct Gpio_reg : Genode::Mmio
struct Gpio_reg : Genode::Attached_io_mem_dataspace, Genode::Mmio
{
Gpio_reg(Genode::addr_t const mmio_base) : Genode::Mmio(mmio_base) { }
Gpio_reg(Genode::addr_t const mmio_base,
Genode::size_t const mmio_size)
: Genode::Attached_io_mem_dataspace(mmio_base, mmio_size),
Genode::Mmio((Genode::addr_t)local_addr<void>()) { }
struct Oe : Register<0x134, 32> {};
struct Oe : Register_array<0x134, 32, 32, 1> {};
struct Irqstatus_0 : Register<0x02c, 32> {};
struct Irqstatus_set_0 : Register<0x034, 32> {};
struct Irqstatus_clr_0 : Register<0x03c, 32> {};
struct Ctrl : Register<0x130, 32> {};
struct Leveldetect0 : Register<0x140, 32> {};
struct Leveldetect1 : Register<0x144, 32> {};
struct Risingdetect : Register<0x148, 32> {};
struct Fallingdetect : Register<0x14c, 32> {};
struct Debounceenable : Register<0x150, 32> {};
struct Leveldetect0 : Register_array<0x140, 32, 32, 1> {};
struct Leveldetect1 : Register_array<0x144, 32, 32, 1> {};
struct Risingdetect : Register_array<0x148, 32, 32, 1> {};
struct Fallingdetect : Register_array<0x14c, 32, 32, 1> {};
struct Debounceenable : Register_array<0x150, 32, 32, 1> {};
struct Debouncingtime : Register<0x154, 32>
{
struct Time : Bitfield<0, 8> {};
};
struct Cleardataout : Register<0x190, 32> {};
struct Setdataout : Register<0x194, 32> {};
struct Datain : Register<0x138, 32> {};
struct Datain : Register_array<0x138, 32, 32, 1> {};
};
#endif /* _GPIO_H_ */

53
os/src/drivers/gpio/omap4/irq_handler.h
View File

@ -1,53 +0,0 @@
/*
* \brief Gpio irq-handler
* \author Ivan Loskutov <ivan.loskutov@ksyslabs.org>
* \date 2012-06-23
*/
/*
* Copyright (C) 2012 Ksys Labs LLC
* Copyright (C) 2012-2013 Genode Labs GmbH
*
* This file is part of the Genode OS framework, which is distributed
* under the terms of the GNU General Public License version 2.
*/
#ifndef _IRQ_HANDLER_H_
#define _IRQ_HANDLER_H_
/* Genode includes */
#include <base/thread.h>
#include <irq_session/connection.h>
/* local includes */
#include "driver.h"
class Irq_handler : Genode::Thread<4096>
{
private:
int _irq_number;
Genode::Irq_connection _irq;
Gpio::Driver &_driver;
public:
Irq_handler(int irq_number, Gpio::Driver &driver)
:
_irq_number(irq_number),
_irq(irq_number),
_driver(driver)
{
start();
}
void entry()
{
while (1) {
_driver.handle_event(_irq_number);
_irq.wait_for_irq();
}
}
};
#endif /* _IRQ_HANDLER_H_ */

190
os/src/drivers/gpio/omap4/main.cc
View File

@ -1,6 +1,7 @@
/*
* \brief Gpio driver for the OMAP4
* \author Ivan Loskutov <ivan.loskutov@ksyslabs.org>
* \author Stefan Kalkowski <stefan.kalkowski@genode-labs.com>
* \date 2012-06-23
*/
@ -13,204 +14,33 @@
*/
/* Genode includes */
#include <gpio_session/gpio_session.h>
#include <cap_session/connection.h>
#include <dataspace/client.h>
#include <base/printf.h>
#include <base/sleep.h>
#include <root/component.h>
#include <os/config.h>
#include <os/static_root.h>
#include <util/string.h>
#include <cap_session/connection.h>
#include <gpio/component.h>
#include <gpio/config.h>
/* local includes */
#include "driver.h"
#include "irq_handler.h"
namespace Gpio {
using namespace Genode;
class Session_component;
};
class Gpio::Session_component : public Genode::Rpc_object<Gpio::Session>
{
private:
Driver &_driver;
Signal_context_capability _read_avail_sigh;
public:
Session_component(Driver &driver)
:
_driver(driver)
{
}
/************************************
** Gpio::Session interface **
************************************/
void direction_output(int gpio, bool enable)
{
_driver.set_gpio_dataout(gpio, enable);
_driver.set_gpio_direction(gpio, false);
}
void direction_input(int gpio)
{
_driver.set_gpio_direction(gpio, true);
}
void dataout(int gpio, bool enable)
{
_driver.set_gpio_dataout(gpio, enable);
}
int datain(int gpio)
{
return _driver.get_gpio_datain(gpio);
}
void debounce_enable(int gpio, bool enable)
{
_driver.set_gpio_debounce_enable(gpio, enable);
}
void debouncing_time(int gpio, unsigned int us)
{
_driver.set_gpio_debouncing_time(gpio, us);
}
void falling_detect(int gpio, bool enable)
{
_driver.set_gpio_falling_detect(gpio, enable);
}
void rising_detect(int gpio, bool enable)
{
_driver.set_gpio_rising_detect(gpio, enable);
}
void irq_enable(int gpio, bool enable)
{
_driver.set_gpio_irq_enable(gpio, enable);
}
void irq_sigh(Signal_context_capability cap, int gpio)
{
_driver.register_signal(cap, gpio);
}
};
#include <driver.h>
int main(int, char **)
{
using namespace Gpio;
using namespace Genode;
printf("--- omap4 gpio driver ---\n");
Driver driver;
Irq_handler gpio1_irq(Driver::GPIO1_IRQ, driver);
Irq_handler gpio2_irq(Driver::GPIO2_IRQ, driver);
Irq_handler gpio3_irq(Driver::GPIO3_IRQ, driver);
Irq_handler gpio4_irq(Driver::GPIO4_IRQ, driver);
Irq_handler gpio5_irq(Driver::GPIO5_IRQ, driver);
Irq_handler gpio6_irq(Driver::GPIO6_IRQ, driver);
/*
* Configure GPIO
* Example:
* <config>
* <gpio num="123" mode="I"/>
* <gpio num="124" mode="O" value="0"/>
* </config>
*
* num - GPIO pin number
* mode - input(I) or output(O)
* value - output level (1 or 0), only for output mode
*/
try {
Genode::Xml_node gpio_node = Genode::config()->xml_node().sub_node("gpio");
for (;; gpio_node = gpio_node.next("gpio")) {
unsigned num;
char mode[2] = {0};
unsigned value = 0;
bool value_ok;
do {
try {
gpio_node.attribute("num").value(&num);
}
catch(Genode::Xml_node::Nonexistent_attribute)
{
PERR("Missing \"num\" attribute. Ignore node.");
break;
}
try {
gpio_node.attribute("mode").value(mode, sizeof(mode));
}
catch(Genode::Xml_node::Nonexistent_attribute)
{
PERR("Missing \"mode\" attribute. Ignore node.");
break;
}
try {
value_ok = gpio_node.attribute("value").value(&value);
}
catch(Genode::Xml_node::Nonexistent_attribute)
{
value_ok = false;
}
if (mode[0] == 'O' || mode[0] == 'o')
{
if (!value_ok) {
PERR("Missing \"value\" attribute for Output mode. Ignore node.");
break;
}
if (value > 1) {
PERR("Incorrect \"value\" attribute for Output mode. Ignore node.");
break;
}
driver.set_gpio_dataout(num, value);
driver.set_gpio_direction(num, false);
} else if (mode[0] == 'I' || mode[0] == 'i') {
driver.set_gpio_direction(num, true);
} else {
PERR("Incorrect value of \"mode\" attribute. Ignore node.");
break;
}
PDBG("gpio %d mode %s value=%s",
num, mode, value_ok ? (value==0 ? "0" : value==1 ? "1" : "error") : "-"
);
} while(0);
if (gpio_node.is_last("gpio")) break;
}
}
catch (Genode::Xml_node::Nonexistent_sub_node) {
PERR("No GPIO config");
}
Omap4_driver &driver = Omap4_driver::factory();
Gpio::process_config(driver);
/*
* Initialize server entry point
*/
enum { STACK_SIZE = 4096 };
static Cap_connection cap;
Sliced_heap sliced_heap(env()->ram_session(), env()->rm_session());
static Rpc_entrypoint ep(&cap, STACK_SIZE, "gpio_ep");
/*
* Let the entry point serve the gpio session and root interfaces
*/
static Session_component gpio_session(driver);
static Static_root<Gpio::Session> gpio_root(ep.manage(&gpio_session));
static Gpio::Root gpio_root(&ep, &sliced_heap, driver);
/*
* Announce service

80
os/src/test/gpio_drv/gpio_test.h
View File

@ -27,27 +27,28 @@ class Gpio_test
public:
enum {
LED1_GPIO = 7,
LED2_GPIO = 8,
BUTTON_GPIO = 121,
GPIO4_IRQ = 32 + 32,
LED1_GPIO = 7,
LED2_GPIO = 8,
BUTTON_GPIO = 121,
GPIO4_IRQ = 32 + 32,
};
private:
Gpio::Connection _gpio;
Gpio::Connection _gpio_led1;
Gpio::Connection _gpio_led2;
Gpio::Connection _gpio_button;
Gpio::Connection _gpio_irq4;
Signal_receiver sig_rec;
Signal_context sig_ctx;
public:
Gpio_test();
~Gpio_test();
void wait_for_signal()
{
sig_rec.wait_for_signal();
}
Gpio_test();
void wait_for_signal() {
sig_rec.wait_for_signal(); }
bool polling_test();
bool irq_test();
@ -55,17 +56,14 @@ class Gpio_test
Gpio_test::Gpio_test()
: _gpio_led1(LED1_GPIO),
_gpio_led2(LED2_GPIO),
_gpio_button(BUTTON_GPIO),
_gpio_irq4(GPIO4_IRQ)
{
/* initialize GPIO_121 */
_gpio.debouncing_time(BUTTON_GPIO, 31*100);
_gpio.debounce_enable(BUTTON_GPIO, 1);
_gpio.irq_sigh(sig_rec.manage(&sig_ctx), BUTTON_GPIO);
}
Gpio_test::~Gpio_test()
{
_gpio_button.debouncing(31*100);
_gpio_button.irq_sigh(sig_rec.manage(&sig_ctx));
}
@ -74,23 +72,25 @@ bool Gpio_test::polling_test()
printf("---------- Polling test ----------\n");
printf("\nPush and hold button...\n");
_gpio.dataout(LED1_GPIO, true);
_gpio.dataout(LED2_GPIO, false);
volatile int gpio_state;
_gpio_led1.write(true);
_gpio_led2.write(false);
volatile bool gpio_state;
do {
gpio_state = _gpio.datain(BUTTON_GPIO);
gpio_state = _gpio_button.read();
} while (gpio_state);
printf("OK\n");
_gpio.dataout(LED1_GPIO, false);
_gpio.dataout(LED2_GPIO, true);
_gpio_led1.write(false);
_gpio_led2.write(true);
printf("\nRelease button...\n");
do {
gpio_state = _gpio.datain(BUTTON_GPIO);
gpio_state = _gpio_button.read();
} while (!gpio_state);
printf("OK\n");
@ -102,35 +102,35 @@ bool Gpio_test::irq_test()
{
printf("---------- IRQ test ----------\n");
_gpio.falling_detect(BUTTON_GPIO, 1);
_gpio.irq_enable(BUTTON_GPIO, 1);
_gpio_button.irq_type(Gpio::Session::FALLING_EDGE);
_gpio_button.irq_enable(true);
_gpio.dataout(LED1_GPIO, true);
_gpio.dataout(LED2_GPIO, false);
_gpio_led1.write(true);
_gpio_led2.write(false);
printf("\nPush and hold button...\n");
wait_for_signal();
_gpio.irq_enable(BUTTON_GPIO, 0);
_gpio_button.irq_enable(false);
printf("OK\n");
_gpio.falling_detect(BUTTON_GPIO, 0);
_gpio.rising_detect(BUTTON_GPIO, 1);
_gpio.irq_enable(BUTTON_GPIO, 1);
_gpio_button.irq_type(Gpio::Session::RISING_EDGE);
_gpio_button.irq_enable(true);
_gpio.dataout(LED1_GPIO, false);
_gpio.dataout(LED2_GPIO, true);
_gpio_led1.write(false);
_gpio_led2.write(true);
printf("\nRelease button...\n");
wait_for_signal();
_gpio.irq_enable(BUTTON_GPIO, 0);
_gpio_button.irq_enable(false);
printf("OK\n");
_gpio.falling_detect(BUTTON_GPIO, 0);
_gpio.rising_detect(BUTTON_GPIO, 0);
_gpio_button.irq_type(Gpio::Session::HIGH_LEVEL);
return true;
}