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os: initial preparation for 64Bit AHCI support

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The AHCI driver seems to work on x86_64, though it should be treated
carefully because for now all adresses involved are <= 32Bit.
This commit is contained in:
Josef Söntgen 2013-11-26 16:41:38 +01:00 committed by Norman Feske
parent 1884e16ecf
commit c6ed7f13bf
4 changed files with 26 additions and 9 deletions
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4
os/lib/mk/x86_32/ahci.mk → os/lib/mk/x86/ahci.mk
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@ -1,11 +1,11 @@
# #
# \brief Toolchain configurations for AHCI on X86 32 bit # \brief Toolchain configurations for AHCI on X86
# \author Martin Stein <martin.stein@genode-labs.com> # \author Martin Stein <martin.stein@genode-labs.com>
# \date 2013-05-17 # \date 2013-05-17
# #
# add include directories # add include directories
INC_DIR += $(REP_DIR)/src/drivers/ahci/x86_32 INC_DIR += $(REP_DIR)/src/drivers/ahci/x86
# include less specific config # include less specific config
include $(REP_DIR)/lib/mk/ahci.inc include $(REP_DIR)/lib/mk/ahci.inc

31
os/src/drivers/ahci/include/ahci_device_base.h
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@ -104,11 +104,22 @@ class Ahci_port : public Reg_base
{ {
public: public:
/* command list base (lower 32 bit) */ /* command list base */
void cmd_list_base(addr_t cmd_base) { _set(0x0, cmd_base); } void cmd_list_base(addr_t cmd_base)
{
uint64_t addr = cmd_base;
_set(0x0, addr);
_set(0x4, addr >> 32);
}
/* receive FIS base address (lower 32 bit) */ /* receive FIS base address */
void fis_base(addr_t fis_base) { _set(0x8, fis_base); } void fis_base(addr_t fis_base)
{
uint64_t addr = fis_base;
_set(0x8, addr);
_set(0xc, addr);
}
/* interrupt status */ /* interrupt status */
uint32_t intr_status() { return _value(0x10); } uint32_t intr_status() { return _value(0x10); }
@ -309,6 +320,8 @@ struct Command_table
enum { MAX_BYTES = 1 << 22 }; /* 4MB = one PRD */ enum { MAX_BYTES = 1 << 22 }; /* 4MB = one PRD */
uint8_t *fis = (uint8_t *)this; uint8_t *fis = (uint8_t *)this;
uint64_t addr = phys_addr;
/* setup FIS */ /* setup FIS */
fis[0] = 0x27; /* type = host to device */ fis[0] = 0x27; /* type = host to device */
fis[1] = 0x80; /* set update command flag */ fis[1] = 0x80; /* set update command flag */
@ -324,7 +337,10 @@ struct Command_table
fis[13] = (blk_cnt >> 8) & 0xff; /* sector count 8 - 15 */ fis[13] = (blk_cnt >> 8) & 0xff; /* sector count 8 - 15 */
/* setup PRD for DMA */ /* setup PRD for DMA */
memcpy(&fis[0x80], &phys_addr, 4); /* DBA: data base address */ uint32_t addr_l = addr;
uint32_t addr_u = addr >> 32;
memcpy(&fis[0x80], &addr_l, 4); /* DBA: data base address */
memcpy(&fis[0x84], &addr_u, 4); /* DBA: data base address upper */
uint32_t bytes = (blk_cnt * 512) - 1; uint32_t bytes = (blk_cnt * 512) - 1;
if (bytes + 1 > MAX_BYTES) { if (bytes + 1 > MAX_BYTES) {
@ -407,9 +423,10 @@ class Ahci_device_base
_port->fis_base(phys); _port->fis_base(phys);
virt += 256; phys += 256; virt += 256; phys += 256;
uint64_t addr = phys;
/* setup command table (128 byte aligned (cache line size)) */ /* setup command table (128 byte aligned (cache line size)) */
_cmd_list->cmd_table_base_l = phys; _cmd_list->cmd_table_base_l = addr;
_cmd_list->cmd_table_base_u = 0; _cmd_list->cmd_table_base_u = addr >> 32;
_cmd_table = (struct Command_table *)(virt); _cmd_table = (struct Command_table *)(virt);
} }

0
os/src/drivers/ahci/x86_32/ahci_device.h → os/src/drivers/ahci/x86/ahci_device.h
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0
os/src/drivers/ahci/x86_32/ahci_driver.h → os/src/drivers/ahci/x86/ahci_driver.h
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