diff --git a/repos/base/include/spec/x86/cpu/vcpu_state.h b/repos/base/include/spec/x86/cpu/vcpu_state.h
index 2c6ac5b0f5..0df15b1c94 100644
--- a/repos/base/include/spec/x86/cpu/vcpu_state.h
+++ b/repos/base/include/spec/x86/cpu/vcpu_state.h
@@ -47,6 +47,8 @@ class Genode::Vcpu_state
 
 	public:
 
+		Vcpu_state() = default;
+
 		template <typename T>
 		class Register : Noncopyable
 		{
@@ -94,85 +96,85 @@ class Genode::Vcpu_state
 			addr_t   base;
 		};
 
-		Register<addr_t> ax;
-		Register<addr_t> cx;
-		Register<addr_t> dx;
-		Register<addr_t> bx;
+		Register<addr_t> ax { };
+		Register<addr_t> cx { };
+		Register<addr_t> dx { };
+		Register<addr_t> bx { };
 
-		Register<addr_t> bp;
-		Register<addr_t> si;
-		Register<addr_t> di;
+		Register<addr_t> bp { };
+		Register<addr_t> si { };
+		Register<addr_t> di { };
 
-		Register<addr_t> sp;
-		Register<addr_t> ip;
-		Register<addr_t> ip_len;
-		Register<addr_t> flags;
+		Register<addr_t> sp { };
+		Register<addr_t> ip { };
+		Register<addr_t> ip_len { };
+		Register<addr_t> flags { };
 
-		Register<Segment> es;
-		Register<Segment> ds;
-		Register<Segment> fs;
-		Register<Segment> gs;
-		Register<Segment> cs;
-		Register<Segment> ss;
-		Register<Segment> tr;
-		Register<Segment> ldtr;
+		Register<Segment> es { };
+		Register<Segment> ds { };
+		Register<Segment> fs { };
+		Register<Segment> gs { };
+		Register<Segment> cs { };
+		Register<Segment> ss { };
+		Register<Segment> tr { };
+		Register<Segment> ldtr { };
 
-		Register<Range> gdtr;
-		Register<Range> idtr;
+		Register<Range> gdtr { };
+		Register<Range> idtr { };
 
-		Register<addr_t> cr0;
-		Register<addr_t> cr2;
-		Register<addr_t> cr3;
-		Register<addr_t> cr4;
+		Register<addr_t> cr0 { };
+		Register<addr_t> cr2 { };
+		Register<addr_t> cr3 { };
+		Register<addr_t> cr4 { };
 
-		Register<addr_t> dr7;
+		Register<addr_t> dr7 { };
 
-		Register<addr_t> sysenter_ip;
-		Register<addr_t> sysenter_sp;
-		Register<addr_t> sysenter_cs;
+		Register<addr_t> sysenter_ip { };
+		Register<addr_t> sysenter_sp { };
+		Register<addr_t> sysenter_cs { };
 
-		Register<uint64_t> qual_primary;
-		Register<uint64_t> qual_secondary;
+		Register<uint64_t> qual_primary { };
+		Register<uint64_t> qual_secondary { };
 
-		Register<uint32_t> ctrl_primary;
-		Register<uint32_t> ctrl_secondary;
+		Register<uint32_t> ctrl_primary { };
+		Register<uint32_t> ctrl_secondary { };
 
-		Register<uint32_t> inj_info;
-		Register<uint32_t> inj_error;
+		Register<uint32_t> inj_info { };
+		Register<uint32_t> inj_error { };
 
-		Register<uint32_t> intr_state;
-		Register<uint32_t> actv_state;
+		Register<uint32_t> intr_state { };
+		Register<uint32_t> actv_state { };
 
-		Register<uint64_t> tsc;
-		Register<uint64_t> tsc_offset;
-		Register<uint64_t> tsc_aux;
+		Register<uint64_t> tsc { };
+		Register<uint64_t> tsc_offset { };
+		Register<uint64_t> tsc_aux { };
 
-		Register<addr_t>   efer;
+		Register<addr_t>   efer { };
 
-		Register<uint64_t> pdpte_0;
-		Register<uint64_t> pdpte_1;
-		Register<uint64_t> pdpte_2;
-		Register<uint64_t> pdpte_3;
+		Register<uint64_t> pdpte_0 { };
+		Register<uint64_t> pdpte_1 { };
+		Register<uint64_t> pdpte_2 { };
+		Register<uint64_t> pdpte_3 { };
 
-		Register<uint64_t> r8;
-		Register<uint64_t> r9;
-		Register<uint64_t> r10;
-		Register<uint64_t> r11;
-		Register<uint64_t> r12;
-		Register<uint64_t> r13;
-		Register<uint64_t> r14;
-		Register<uint64_t> r15;
+		Register<uint64_t> r8  { };
+		Register<uint64_t> r9  { };
+		Register<uint64_t> r10 { };
+		Register<uint64_t> r11 { };
+		Register<uint64_t> r12 { };
+		Register<uint64_t> r13 { };
+		Register<uint64_t> r14 { };
+		Register<uint64_t> r15 { };
 
-		Register<uint64_t> star;
-		Register<uint64_t> lstar;
-		Register<uint64_t> cstar;
-		Register<uint64_t> fmask;
-		Register<uint64_t> kernel_gs_base;
+		Register<uint64_t> star  { };
+		Register<uint64_t> lstar { };
+		Register<uint64_t> cstar { };
+		Register<uint64_t> fmask { };
+		Register<uint64_t> kernel_gs_base { };
 
-		Register<uint32_t> tpr;
-		Register<uint32_t> tpr_threshold;
+		Register<uint32_t> tpr { };
+		Register<uint32_t> tpr_threshold { };
 
-		unsigned exit_reason;
+		unsigned exit_reason { };
 
 		class Fpu : Noncopyable
 		{
@@ -216,7 +218,7 @@ class Genode::Vcpu_state
 				}
 		};
 
-		Fpu fpu __attribute__((aligned(16)));
+		Fpu fpu __attribute__((aligned(16))) { };
 
 		/*
 		 * Registers transfered by hypervisor from guest on VM exit are charged.