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platform/x86: improve DMA memory alignment

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If the DMA memory allocation alignment is unfortunate (not natural size
aligned), the IOMMU (AMD/INTEL) may not use larger(super) pages with effects
on the page table walk frequency and TLB caching.

Issue #4820
This commit is contained in:
Alexander Boettcher 2023-04-26 11:59:42 +02:00 committed by Christian Helmuth
parent 98a31bbfdb
commit bdbfa532cd
1 changed files with 9 additions and 1 deletions
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10
repos/os/src/drivers/platform/device_pd.cc
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@ -94,7 +94,14 @@ addr_t Device_pd::_dma_addr(addr_t const phys_addr,
});
}
return _dma_alloc.alloc_aligned(size, 12).convert<addr_t>(
/* natural size align (to some limit) for better IOMMU TLB usage */
unsigned size_align_log2 = unsigned(log2(size));
if (size_align_log2 < 12) /* 4 kB */
size_align_log2 = 12;
if (size_align_log2 > 24) /* 16 MB */
size_align_log2 = 24;
return _dma_alloc.alloc_aligned(size, size_align_log2).convert<addr_t>(
[&] (void *ptr) { return (addr_t)ptr; },
[&] (Alloc_error err) -> addr_t {
switch (err) {
@ -102,6 +109,7 @@ addr_t Device_pd::_dma_addr(addr_t const phys_addr,
case Alloc_error::OUT_OF_CAPS: throw Out_of_caps();
case Alloc_error::DENIED:
error("Could not allocate DMA area of size: ", size,
" alignment: ", size_align_log2,
" total avail: ", _dma_alloc.avail(),
" (error: ", err, ")");
break;