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base-hw: disable L2 cache on Pandaboard (fix #797)

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* Fix bitfield typo in TTBR0 register for ARMv7
This commit is contained in:
Stefan Kalkowski 2013-07-09 17:10:51 +02:00 committed by Christian Helmuth
parent 731493641b
commit ba273fb6fb
2 changed files with 25 additions and 1 deletions
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2
base-hw/src/core/cpu/arm_v7.h
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@ -122,7 +122,7 @@ namespace Arm_v7
*/ */
struct Ttbr0 : Arm::Cpu::Ttbr0 struct Ttbr0 : Arm::Cpu::Ttbr0
{ {
struct Nos : Bitfield<6,1> { }; /* not outer shareable */ struct Nos : Bitfield<5,1> { }; /* not outer shareable */
struct Irgn_1 : Bitfield<0,1> { }; /* inner cachable mode */ struct Irgn_1 : Bitfield<0,1> { }; /* inner cachable mode */
struct Irgn_0 : Bitfield<6,1> { }; /* inner cachable mode */ struct Irgn_0 : Bitfield<6,1> { }; /* inner cachable mode */

24
base-hw/src/core/panda/tlb.h
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@ -29,6 +29,23 @@ namespace Genode
*/ */
class Core_tlb : public Tlb class Core_tlb : public Tlb
{ {
private:
/**
* On Pandaboard the L2 cache needs to be disabled by a
* TrustZone hypervisor call
*/
void _disable_outer_l2_cache()
{
asm volatile (
"stmfd sp!, {r0-r12} \n"
"mov r0, #0 \n"
"ldr r12, =0x102 \n"
"dsb \n"
"smc #0 \n"
"ldmfd sp!, {r0-r12}");
}
public: public:
/** /**
@ -37,6 +54,13 @@ namespace Genode
Core_tlb() Core_tlb()
{ {
using namespace Genode; using namespace Genode;
/*
* Disable L2-cache by now, or we get into deep trouble with the MMU
* not using the L2 cache
*/
_disable_outer_l2_cache();
map_core_area(Board::RAM_0_BASE, Board::RAM_0_SIZE, 0); map_core_area(Board::RAM_0_BASE, Board::RAM_0_SIZE, 0);
map_core_area(Board::MMIO_0_BASE, Board::MMIO_0_SIZE, 1); map_core_area(Board::MMIO_0_BASE, Board::MMIO_0_SIZE, 1);
map_core_area(Board::MMIO_1_BASE, Board::MMIO_1_SIZE, 1); map_core_area(Board::MMIO_1_BASE, Board::MMIO_1_SIZE, 1);