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pistachio: size-aligned I/O mem mapping in core

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This commit circumvents faulty behaviour of base-pistachio, if
the PCI config space gets requested megabyte-wise. It occurs that
we get a mapping sequence in between sigma0, core and component,
like the following: 0xe1000000 => 0xbf001000 => 0x10b000,
with the consequence that the component stalls when accessing
the latter one. By requesting I/O memory aligned to the size,
the faulty behaviour vanishes.

Ref #4686
This commit is contained in:
Stefan Kalkowski
2022-11-21 15:35:11 +01:00
committed by Christian Helmuth
parent 424ed1b79a
commit b596db3eed
1 changed files with 3 additions and 3 deletions
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repos/base-pistachio/src/core/io_mem_session_support.cc
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@ -66,10 +66,10 @@ addr_t Io_mem_session_component::_map_local(addr_t base, size_t size)
if (is_conventional_memory(base)) if (is_conventional_memory(base))
return base; return base;
/* align large I/O dataspaces on a super-page boundary within core */ /* align large I/O dataspaces to super page size, otherwise to size */
size_t const align = (size >= get_super_page_size()) size_t const align = (size >= get_super_page_size())
? get_super_page_size_log2() ? get_super_page_size_log2()
: get_page_size_log2(); : log2(size);
return platform().region_alloc().alloc_aligned(size, align).convert<addr_t>( return platform().region_alloc().alloc_aligned(size, align).convert<addr_t>(
[&] (void *ptr) { return (addr_t)ptr; }, [&] (void *ptr) { return (addr_t)ptr; },