From b2440a72c304041d64d9295df6cebc1f0b21ed32 Mon Sep 17 00:00:00 2001
From: Alexander Boettcher <alexander.boettcher@genode-labs.com>
Date: Wed, 28 Jul 2021 15:33:17 +0200
Subject: [PATCH] gpu/intel: add more debug registers

issue #4254
---
 repos/os/src/drivers/gpu/intel/mmio.h       | 47 +++++++++++++++++++++
 repos/os/src/drivers/gpu/intel/mmio_dump.cc | 30 ++++++++++++-
 2 files changed, 75 insertions(+), 2 deletions(-)

diff --git a/repos/os/src/drivers/gpu/intel/mmio.h b/repos/os/src/drivers/gpu/intel/mmio.h
index 436fc4b429..90f8d3c671 100644
--- a/repos/os/src/drivers/gpu/intel/mmio.h
+++ b/repos/os/src/drivers/gpu/intel/mmio.h
@@ -347,6 +347,11 @@ class Igd::Mmio : public Genode::Mmio
 		 ** Debug registers **
 		 *********************/
 
+		/*
+		 * Ancient (2008) Volume 1: Graphics Core p. 225
+		 */
+		struct HW_MEMRD : Register<0x2060, 32> { };
+
 		/*
 		 * Ancient (2008) Volume 1: Graphics Core p. 228
 		 */
@@ -430,6 +435,16 @@ class Igd::Mmio : public Genode::Mmio
 
 		struct RCS_ACTHD : ACTHD_BASE<0x2000> { };
 
+		/*
+		 * Ancient (2008) Volume 1: Graphics Core p. 232
+		 */
+		struct DMA_FADD_PREF : Register<0x2078, 32> { };
+
+		/*
+		 * Ancient (2008) Volume 1: Graphics Core p. 235
+		 */
+		struct NOP_ID : Register<0x2094, 32> { };
+
 		/*
 		 * Ancient (2008) Volume 1: Graphics Core p. 205
 		 */
@@ -621,6 +636,8 @@ class Igd::Mmio : public Genode::Mmio
 		struct HWS_PGA_VCSUNIT1 : Register<0x1C080, 32> { };
 		struct HWS_PGA_BCSUNIT  : Register<0x22080, 32> { };
 
+		struct PWRCTXA  : Register<0x02088, 32> { };
+
 		/*
 		 * IHD-OS-BDW-Vol 2c-11.15 p. 1370
 		 */
@@ -673,6 +690,14 @@ class Igd::Mmio : public Genode::Mmio
 			struct Force_wake_request_for_thread_0  : Bitfield< 0, 1> { };
 		};
 
+		struct DRIVER_RENDER_FWAKE_ACK : Register<0x0D84, 32> {
+			struct Rcs_force_wake_enable_mask : Bitfield<16, 1> { };
+			struct Rcs_force_wake_enable      : Bitfield< 0, 1> { };
+		};
+
+		struct ELEM_DESCRIPTOR1 : Register<0x4400, 32> { };
+		struct ELEM_DESCRIPTOR2 : Register<0x4404, 32> { };
+
 		/*
 		 * IHD-OS-BDW-Vol 2c-11.15 p. 703
 		 *
@@ -813,6 +838,28 @@ class Igd::Mmio : public Genode::Mmio
 
 		struct PGTBL_CTL2 : Register<0x20C4, 32> { };
 
+		/*
+		 * Ancient (2008) Volume 1: Graphics Core p. 252
+		 */
+		struct INSTPM : Register<0x20c0, 32> { };
+
+		/*
+		 * Ancient (2008) Volume 1: Graphics Core p. 252
+		 */
+		struct Cache_Mode_0 : Register<0x2120, 32> { };
+		struct Cache_Mode_1 : Register<0x2124, 32> { };
+		struct CTXT_SR_CTL  : Register<0x2714, 32> { };
+		struct BB_STATE     : Register<0x2110, 32> { };
+		struct BB_ADDR      : Register<0x2140, 32> { };
+		struct CCID         : Register<0x2180, 32> { };
+		struct CXT_SIZE       : Register<0x21A0, 32> { };
+		struct CXT_SIZE_NOEXT : Register<0x21A4, 32> { };
+		struct MI_DISP_PWR_DWN : Register<0x20E0, 32> { };
+		struct MI_ARB_STATE    : Register<0x20E4, 32> { };
+		struct MI_RDRET_STATE  : Register<0x20FC, 32> { };
+		struct MI_MODE         : Register<0x209c, 32> { };
+		struct ECOSKPD         : Register<0x21D0, 32> { };
+
 	private:
 
 		Mmio::Delayer &_delayer;
diff --git a/repos/os/src/drivers/gpu/intel/mmio_dump.cc b/repos/os/src/drivers/gpu/intel/mmio_dump.cc
index 65d5a5738a..67c482f252 100644
--- a/repos/os/src/drivers/gpu/intel/mmio_dump.cc
+++ b/repos/os/src/drivers/gpu/intel/mmio_dump.cc
@@ -26,8 +26,34 @@ void Igd::Mmio::dump()
 	log("  Execlist_enable:           ", Hex(read<GFX_MODE::Execlist_enable>()));
 	log("  Virtual_addressing_enable: ", Hex(read<GFX_MODE::Virtual_addressing_enable>()));
 	log("  Ppgtt_enable:              ", Hex(read<GFX_MODE::Ppgtt_enable>()));
-	log("HWS_PGA: ", Hex(read<HWS_PGA_RCSUNIT>()));
-	log("HWSTAM: ", Hex(read<HWSTAM>()));
+	log("0x2080 - HWS_PGA: ", Hex(read<HWS_PGA_RCSUNIT>()));
+	log("0x2088 - PWRCTXA: ", Hex(read<PWRCTXA>()));
+	log("0x2098 - HWSTAM: ", Hex(read<HWSTAM>()));
+	log("0x0D84 - DRIVER_RENDER_FWAKE_ACK: ", Hex(read<DRIVER_RENDER_FWAKE_ACK>()));
+	log("0x4400 - ELEM_DESCRIPTOR1 :        ", Hex(read<ELEM_DESCRIPTOR1>()));
+	log("0x4404 - ELEM_DESCRIPTOR2 :        ", Hex(read<ELEM_DESCRIPTOR2>()));
+	log("0x2060 - HW_MEMRD :        ", Hex(read<HW_MEMRD>()));
+	log("0x2064 - IPEIR:          ", Hex(read<IPEIR>()));
+	log("0x2068 - IPEHR:          ", Hex(read<IPEHR>()));
+	log("0x206C - RCS_INSTDONE:   ", Hex(read<RCS_INSTDONE>()));
+	log("0x207C - RCS_ACTHD:      ", Hex(read<RCS_ACTHD>()));
+	log("0x2078 - DMA_FADD_PREF:  ", Hex(read<DMA_FADD_PREF>()));
+	log("0x207C - RCS_INSTDONE_1: ", Hex(read<RCS_INSTDONE_1>()));
+	log("0x2094 - NOP_ID:         ", Hex(read<NOP_ID>()));
+	log("0x20C0 - INSTPM:         ", Hex(read<INSTPM>()));
+	log("0x2120 - Cache_mode_0:   ", Hex(read<Cache_Mode_0>()));
+	log("0x2124 - Cache_mode_1:   ", Hex(read<Cache_Mode_1>()));
+	log("0x2714 - Ctx S/R Ctrl:   ", Hex(read<CTXT_SR_CTL>()));
+	log("0x2140 - BB_ADDR:        ", Hex(read<BB_ADDR>()));
+	log("0x2110 - BB_STATE:       ", Hex(read<BB_STATE>()));
+	log("0x2180 - CCID:           ", Hex(read<CCID>()));
+	log("0x21A0 - CXT_SIZE:       ", Hex(read<CXT_SIZE>()));
+	log("0x21A4 - CXT_SIZE_EXT:   ", Hex(read<CXT_SIZE_NOEXT>()));
+	log("0x20E0 - MI_DISP_PWR_DWN ", Hex(read<MI_DISP_PWR_DWN>()));
+	log("0x20E4 - MI_ARB_STATE    ", Hex(read<MI_ARB_STATE>()));
+	log("0x20FC - MI_RDRET_STATE  ", Hex(read<MI_RDRET_STATE>()));
+	log("0x209C - MI_MODE         ", Hex(read<MI_MODE>()));
+	log("0x21D0 - ECOSKPD         ", Hex(read<ECOSKPD>()));
 }