diff --git a/repos/base-hw/src/core/spec/x86_64/mode_transition.s b/repos/base-hw/src/core/spec/x86_64/mode_transition.s
index 8f4ad81a0c..db36342962 100644
--- a/repos/base-hw/src/core/spec/x86_64/mode_transition.s
+++ b/repos/base-hw/src/core/spec/x86_64/mode_transition.s
@@ -303,6 +303,17 @@
 	.global _mt_gdt_end
 	_mt_gdt_end:
 
+	/************************************************
+	 ** Temporary interrupt stack                  **
+	 ** Set as RSP for privilege levels 0-2 in TSS **
+	 ** See Intel SDM Vol. 3A, section 7.7         **
+	 ************************************************/
+
+	.p2align 8
+	.space 7 * 8
+	.global _mt_kernel_interrupt_stack
+	_mt_kernel_interrupt_stack:
+
 	/* end of the mode transition code */
 	.global _mt_end
 	_mt_end: