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92b3171765
@ -24,9 +24,11 @@ namespace Regulator {
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CLK_USB30,
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CLK_USB20,
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CLK_MMC0,
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CLK_HDMI,
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PWR_SATA,
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PWR_USB30,
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PWR_USB20,
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PWR_HDMI,
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MAX,
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INVALID
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};
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@ -37,14 +39,16 @@ namespace Regulator {
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};
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Regulator_name names[] = {
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{ CLK_CPU, "clock-cpu" },
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{ CLK_SATA, "clock-sata" },
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{ CLK_USB30, "clock-usb3.0" },
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{ CLK_USB20, "clock-usb2.0" },
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{ CLK_MMC0, "clock-mmc0" },
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{ PWR_SATA, "power-sata" },
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{ PWR_USB30, "power-usb3.0" },
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{ PWR_USB20, "power-usb2.0" },
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{ CLK_CPU, "clock-cpu" },
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{ CLK_SATA, "clock-sata" },
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{ CLK_USB30, "clock-usb3.0" },
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{ CLK_USB20, "clock-usb2.0" },
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{ CLK_MMC0, "clock-mmc0" },
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{ CLK_HDMI, "clock-hdmi" },
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{ PWR_SATA, "power-sata" },
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{ PWR_USB30, "power-usb3.0" },
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{ PWR_USB20, "power-usb2.0" },
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{ PWR_HDMI, "power-hdmi"},
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};
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Regulator_id regulator_id_by_name(const char * name)
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@ -187,7 +187,11 @@ class Cmu : public Regulator::Driver,
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};
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struct Clk_gate_ip_gscl : Register<0x10920, 32> { };
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struct Clk_gate_ip_disp1 : Register<0x10928, 32> { };
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struct Clk_gate_ip_disp1 : Register<0x10928, 32>
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{
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struct Clk_mixer : Bitfield<5, 1> { };
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struct Clk_hdmi : Bitfield<6, 1> { };
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};
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struct Clk_gate_ip_mfc : Register<0x1092c, 32> { };
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struct Clk_gate_ip_g3d : Register<0x10930, 32> { };
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struct Clk_gate_ip_gen : Register<0x10934, 32> { };
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@ -204,15 +208,27 @@ class Cmu : public Regulator::Driver,
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struct Sata_phy_i2c : Bitfield<25, 1> { };
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};
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struct Clk_src_disp1_0 : Register<0x1022c, 32>
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{
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struct Hdmi_sel : Bitfield<20, 1> { };
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};
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struct Clk_src_mask_disp1_0 : Register<0x1032c, 32>
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{
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struct Hdmi_mask : Bitfield<20, 1> { };
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};
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struct Clk_gate_ip_peric : Register<0x10950, 32>
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{
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struct Clk_uart2 : Bitfield<2, 1> { };
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struct Clk_pwm : Bitfield<24, 1> { };
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struct Clk_uart2 : Bitfield<2, 1> { };
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struct Clk_i2chdmi : Bitfield<14, 1> { };
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struct Clk_pwm : Bitfield<24, 1> { };
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};
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struct Clk_gate_block : Register<0x10980, 32>
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{
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struct Clk_gen : Bitfield<2, 1> { };
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struct Clk_disp1 : Bitfield<5, 1> { };
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struct Clk_gen : Bitfield<2, 1> { };
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};
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@ -320,6 +336,18 @@ class Cmu : public Regulator::Driver,
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** Device functions **
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**********************/
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void _hdmi_enable()
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{
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write<Clk_gate_ip_peric::Clk_i2chdmi>(1);
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Clk_gate_ip_disp1::access_t gd1 = read<Clk_gate_ip_disp1>();
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Clk_gate_ip_disp1::Clk_mixer::set(gd1, 1);
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Clk_gate_ip_disp1::Clk_hdmi::set(gd1, 1);
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write<Clk_gate_ip_disp1>(gd1);
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write<Clk_gate_block::Clk_disp1>(1);
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write<Clk_src_mask_disp1_0::Hdmi_mask>(1);
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write<Clk_src_disp1_0::Hdmi_sel>(1);
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}
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void _sata_enable()
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{
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/* enable I2C for SATA */
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@ -358,6 +386,9 @@ class Cmu : public Regulator::Driver,
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case CLK_SATA:
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_sata_enable();
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break;
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case CLK_HDMI:
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_hdmi_enable();
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break;
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case CLK_USB30:
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_usb30_enable();
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break;
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@ -413,7 +444,7 @@ class Cmu : public Regulator::Driver,
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write<Clk_gate_ip_isp0>(0);
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write<Clk_gate_ip_isp1>(0);
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write<Clk_gate_sclk_isp>(0);
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write<Clk_gate_ip_gscl>(0);
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write<Clk_gate_ip_gscl>(0);
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write<Clk_gate_ip_disp1>(0);
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write<Clk_gate_ip_mfc>(0);
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write<Clk_gate_ip_g3d>(0);
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@ -33,10 +33,12 @@ struct Driver_factory : Regulator::Driver_factory
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case Regulator::CLK_USB30:
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case Regulator::CLK_USB20:
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case Regulator::CLK_MMC0:
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case Regulator::CLK_HDMI:
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return _cmu;
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case Regulator::PWR_SATA:
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case Regulator::PWR_USB30:
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case Regulator::PWR_USB20:
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case Regulator::PWR_HDMI:
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return _pmu;
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default:
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throw Root::Invalid_args(); /* invalid regulator */
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@ -57,7 +57,12 @@ class Pmu : public Regulator::Driver,
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struct Stat : Register<OFFSET, 32>::template Bitfield<0, 1> { };
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};
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typedef Control<0x700> Hdmi_phy_control;
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struct Hdmi_phy_control : Register<0x700, 32>
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{
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struct Enable : Bitfield<0, 1> { };
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struct Div_ratio : Bitfield<16, 10> { };
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};
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typedef Control<0x704> Usbdrd_phy_control;
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typedef Control<0x708> Usbhost_phy_control;
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typedef Control<0x70c> Efnand_phy_control;
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@ -98,6 +103,14 @@ class Pmu : public Regulator::Driver,
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while (read<typename S::Stat>() != 0) ;
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}
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template <typename C, typename S>
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void _enable_domain()
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{
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if (read<typename S::Stat>() == 7)
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return;
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write<typename C::Local_pwr_cfg>(7);
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while (read<typename S::Stat>() != 7) ;
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}
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void _enable(unsigned long id)
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{
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@ -111,6 +124,13 @@ class Pmu : public Regulator::Driver,
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case PWR_SATA :
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write<Sata_phy_control::Enable>(1);
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break;
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case PWR_HDMI: {
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_enable_domain<Disp1_configuration, Disp1_status>();
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Hdmi_phy_control::access_t hpc = read<Hdmi_phy_control>();
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Hdmi_phy_control::Div_ratio::set(hpc, 150);
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Hdmi_phy_control::Enable::set(hpc, 1);
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write<Hdmi_phy_control>(hpc);
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break; }
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default:
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PWRN("Unsupported for %s", names[id].name);
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}
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