gpu/intel: add more debug registers

issue #4254
This commit is contained in:
Alexander Boettcher 2021-08-03 16:44:16 +02:00 committed by Christian Helmuth
parent c9809fde67
commit 8a285a7bee
2 changed files with 19 additions and 0 deletions

View File

@ -481,6 +481,10 @@ class Igd::Mmio : public Genode::Mmio
struct Reserved : B::template Bitfield<16, 16> { }; /* MBZ */
struct Error_identity_bits : B::template Bitfield< 0, 16> { };
struct Error_instruction : B::template Bitfield<0, 1> { };
struct Error_mem_refresh : B::template Bitfield<1, 1> { };
struct Error_page_table : B::template Bitfield<4, 1> { };
};
struct RCS_EIR : EIR_BASE<0x2000> { };

View File

@ -78,6 +78,21 @@ void Igd::Mmio::error_dump()
}
log("RCS_EIR: ", Hex(read<RCS_EIR>()));
if (read<RCS_EIR::Error_identity_bits>()) {
if (read<RCS_EIR::Error_instruction>())
log(" Error_instruction");
if (read<RCS_EIR::Error_mem_refresh>())
log(" Error_mem_refresh");
if (read<RCS_EIR::Error_page_table>())
log(" Error_page_table");
auto type = read<RCS_EIR::Error_identity_bits>();
if (type != (RCS_EIR::Error_page_table::masked(type) |
RCS_EIR::Error_mem_refresh::masked(type) |
RCS_EIR::Error_instruction::masked(type)))
log(" some unknown error bits are set");
}
log("RCS_ESR: ", Hex(read<RCS_ESR>()));
log("RCS_EMR: ", Hex(read<RCS_EMR>()));
log("RCS_INSTDONE: ", Hex(read<RCS_INSTDONE>()));