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hw: integrate interrupt controllers into board.h

Browse Source 
Additionally, unify more implementation details in between different
usage patterns of ARM's generic interrupt controller (v2)

Ref #3445
This commit is contained in:
Stefan Kalkowski 2019-07-10 13:30:54 +02:00 committed by Christian Helmuth
parent fe426e6f8f
commit 875858b2cc
86 changed files with 293 additions and 392 deletions
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2
repos/base-hw/lib/mk/spec/arm_v6/core-hw-rpi.mk
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@ -9,9 +9,9 @@ INC_DIR += $(REP_DIR)/src/core/spec/rpi
# add C++ sources # add C++ sources
SRC_CC += platform_services.cc SRC_CC += platform_services.cc
SRC_CC += spec/arm/bcm2835_pic.cc
SRC_CC += spec/arm/cpu.cc SRC_CC += spec/arm/cpu.cc
SRC_CC += spec/rpi/timer.cc SRC_CC += spec/rpi/timer.cc
SRC_CC += spec/rpi/pic.cc
# include less specific configuration # include less specific configuration
include $(REP_DIR)/lib/mk/spec/arm_v6/core-hw.inc include $(REP_DIR)/lib/mk/spec/arm_v6/core-hw.inc

2
repos/base-hw/lib/mk/spec/arm_v7/bootstrap-hw-arndale.mk
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@ -1,7 +1,7 @@
INC_DIR += $(BASE_DIR)/../base-hw/src/bootstrap/spec/arndale INC_DIR += $(BASE_DIR)/../base-hw/src/bootstrap/spec/arndale
SRC_CC += bootstrap/spec/arm/cortex_a15_cpu.cc SRC_CC += bootstrap/spec/arm/cortex_a15_cpu.cc
SRC_CC += bootstrap/spec/arndale/pic.cc SRC_CC += bootstrap/spec/arm/gicv2.cc
SRC_CC += bootstrap/spec/arndale/platform.cc SRC_CC += bootstrap/spec/arndale/platform.cc
SRC_CC += bootstrap/spec/arm/arm_v7_cpu.cc SRC_CC += bootstrap/spec/arm/arm_v7_cpu.cc
SRC_CC += hw/spec/32bit/memory_map.cc SRC_CC += hw/spec/32bit/memory_map.cc

2
repos/base-hw/lib/mk/spec/arm_v7/bootstrap-hw-imx6q_sabrelite.mk
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@ -4,7 +4,7 @@ SRC_S += bootstrap/spec/arm/crt0.s
SRC_CC += bootstrap/spec/arm/cpu.cc SRC_CC += bootstrap/spec/arm/cpu.cc
SRC_CC += bootstrap/spec/arm/cortex_a9_mmu.cc SRC_CC += bootstrap/spec/arm/cortex_a9_mmu.cc
SRC_CC += bootstrap/spec/arm/pic.cc SRC_CC += bootstrap/spec/arm/gicv2.cc
SRC_CC += bootstrap/spec/arm/imx6_platform.cc SRC_CC += bootstrap/spec/arm/imx6_platform.cc
SRC_CC += bootstrap/spec/arm/arm_v7_cpu.cc SRC_CC += bootstrap/spec/arm/arm_v7_cpu.cc
SRC_CC += hw/spec/32bit/memory_map.cc SRC_CC += hw/spec/32bit/memory_map.cc

2
repos/base-hw/lib/mk/spec/arm_v7/bootstrap-hw-imx7d_sabre.mk
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@ -1,7 +1,7 @@
INC_DIR += $(BASE_DIR)/../base-hw/src/bootstrap/spec/imx7d_sabre INC_DIR += $(BASE_DIR)/../base-hw/src/bootstrap/spec/imx7d_sabre
SRC_CC += bootstrap/spec/arm/cortex_a15_cpu.cc SRC_CC += bootstrap/spec/arm/cortex_a15_cpu.cc
SRC_CC += bootstrap/spec/arndale/pic.cc SRC_CC += bootstrap/spec/arm/gicv2.cc
SRC_CC += bootstrap/spec/imx7d_sabre/platform.cc SRC_CC += bootstrap/spec/imx7d_sabre/platform.cc
SRC_CC += bootstrap/spec/arm/arm_v7_cpu.cc SRC_CC += bootstrap/spec/arm/arm_v7_cpu.cc
SRC_CC += hw/spec/32bit/memory_map.cc SRC_CC += hw/spec/32bit/memory_map.cc

2
repos/base-hw/lib/mk/spec/arm_v7/bootstrap-hw-nit6_solox.mk
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@ -4,7 +4,7 @@ SRC_S += bootstrap/spec/arm/crt0.s
SRC_CC += bootstrap/spec/arm/cpu.cc SRC_CC += bootstrap/spec/arm/cpu.cc
SRC_CC += bootstrap/spec/arm/cortex_a9_mmu.cc SRC_CC += bootstrap/spec/arm/cortex_a9_mmu.cc
SRC_CC += bootstrap/spec/arm/pic.cc SRC_CC += bootstrap/spec/arm/gicv2.cc
SRC_CC += bootstrap/spec/arm/imx6_platform.cc SRC_CC += bootstrap/spec/arm/imx6_platform.cc
SRC_CC += bootstrap/spec/arm/arm_v7_cpu.cc SRC_CC += bootstrap/spec/arm/arm_v7_cpu.cc
SRC_CC += hw/spec/32bit/memory_map.cc SRC_CC += hw/spec/32bit/memory_map.cc

2
repos/base-hw/lib/mk/spec/arm_v7/bootstrap-hw-odroid_xu.mk
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@ -1,7 +1,7 @@
INC_DIR += $(BASE_DIR)/../base-hw/src/bootstrap/spec/odroid_xu INC_DIR += $(BASE_DIR)/../base-hw/src/bootstrap/spec/odroid_xu
SRC_CC += bootstrap/spec/arm/cortex_a15_cpu.cc SRC_CC += bootstrap/spec/arm/cortex_a15_cpu.cc
SRC_CC += bootstrap/spec/arm/pic.cc SRC_CC += bootstrap/spec/arm/gicv2.cc
SRC_CC += bootstrap/spec/odroid_xu/platform.cc SRC_CC += bootstrap/spec/odroid_xu/platform.cc
SRC_CC += bootstrap/spec/arm/arm_v7_cpu.cc SRC_CC += bootstrap/spec/arm/arm_v7_cpu.cc
SRC_CC += hw/spec/32bit/memory_map.cc SRC_CC += hw/spec/32bit/memory_map.cc

2
repos/base-hw/lib/mk/spec/arm_v7/bootstrap-hw-panda.mk
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@ -3,7 +3,7 @@ NR_OF_CPUS = 2
INC_DIR += $(BASE_DIR)/../base-hw/src/bootstrap/spec/panda INC_DIR += $(BASE_DIR)/../base-hw/src/bootstrap/spec/panda
SRC_CC += bootstrap/spec/arm/cpu.cc SRC_CC += bootstrap/spec/arm/cpu.cc
SRC_CC += bootstrap/spec/arm/cortex_a9_mmu.cc SRC_CC += bootstrap/spec/arm/cortex_a9_mmu.cc
SRC_CC += bootstrap/spec/arm/pic.cc SRC_CC += bootstrap/spec/arm/gicv2.cc
SRC_CC += bootstrap/spec/panda/platform.cc SRC_CC += bootstrap/spec/panda/platform.cc
SRC_CC += bootstrap/spec/arm/arm_v7_cpu.cc SRC_CC += bootstrap/spec/arm/arm_v7_cpu.cc
SRC_CC += hw/spec/32bit/memory_map.cc SRC_CC += hw/spec/32bit/memory_map.cc

2
repos/base-hw/lib/mk/spec/arm_v7/bootstrap-hw-pbxa9.mk
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@ -4,7 +4,7 @@ SRC_S += bootstrap/spec/arm/crt0.s
SRC_CC += bootstrap/spec/arm/cpu.cc SRC_CC += bootstrap/spec/arm/cpu.cc
SRC_CC += bootstrap/spec/arm/cortex_a9_mmu.cc SRC_CC += bootstrap/spec/arm/cortex_a9_mmu.cc
SRC_CC += bootstrap/spec/arm/pic.cc SRC_CC += bootstrap/spec/arm/gicv2.cc
SRC_CC += bootstrap/spec/pbxa9/platform.cc SRC_CC += bootstrap/spec/pbxa9/platform.cc
SRC_CC += bootstrap/spec/arm/arm_v7_cpu.cc SRC_CC += bootstrap/spec/arm/arm_v7_cpu.cc
SRC_CC += hw/spec/32bit/memory_map.cc SRC_CC += hw/spec/32bit/memory_map.cc

2
repos/base-hw/lib/mk/spec/arm_v7/bootstrap-hw-wand_quad.mk
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@ -4,7 +4,7 @@ SRC_S += bootstrap/spec/arm/crt0.s
SRC_CC += bootstrap/spec/arm/cpu.cc SRC_CC += bootstrap/spec/arm/cpu.cc
SRC_CC += bootstrap/spec/arm/cortex_a9_mmu.cc SRC_CC += bootstrap/spec/arm/cortex_a9_mmu.cc
SRC_CC += bootstrap/spec/arm/pic.cc SRC_CC += bootstrap/spec/arm/gicv2.cc
SRC_CC += bootstrap/spec/arm/imx6_platform.cc SRC_CC += bootstrap/spec/arm/imx6_platform.cc
SRC_CC += bootstrap/spec/arm/arm_v7_cpu.cc SRC_CC += bootstrap/spec/arm/arm_v7_cpu.cc
SRC_CC += hw/spec/32bit/memory_map.cc SRC_CC += hw/spec/32bit/memory_map.cc

2
repos/base-hw/lib/mk/spec/arm_v7/bootstrap-hw-zynq_qemu.mk
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@ -4,7 +4,7 @@ SRC_S += bootstrap/spec/arm/crt0.s
SRC_CC += bootstrap/spec/arm/cpu.cc SRC_CC += bootstrap/spec/arm/cpu.cc
SRC_CC += bootstrap/spec/arm/cortex_a9_mmu.cc SRC_CC += bootstrap/spec/arm/cortex_a9_mmu.cc
SRC_CC += bootstrap/spec/arm/pic.cc SRC_CC += bootstrap/spec/arm/gicv2.cc
SRC_CC += bootstrap/spec/zynq/platform.cc SRC_CC += bootstrap/spec/zynq/platform.cc
SRC_CC += bootstrap/spec/arm/arm_v7_cpu.cc SRC_CC += bootstrap/spec/arm/arm_v7_cpu.cc
SRC_CC += hw/spec/32bit/memory_map.cc SRC_CC += hw/spec/32bit/memory_map.cc

2
repos/base-hw/lib/mk/spec/arm_v7/core-hw-arndale.mk
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@ -9,7 +9,7 @@ INC_DIR += $(REP_DIR)/src/core/spec/arndale
INC_DIR += $(REP_DIR)/src/core/spec/arm_v7/virtualization INC_DIR += $(REP_DIR)/src/core/spec/arm_v7/virtualization
# add C++ sources # add C++ sources
SRC_CC += spec/arm_gic/pic.cc SRC_CC += spec/arm/gicv2.cc
SRC_CC += spec/arndale/platform_services.cc SRC_CC += spec/arndale/platform_services.cc
SRC_CC += kernel/vm_thread_on.cc SRC_CC += kernel/vm_thread_on.cc
SRC_CC += spec/arm_v7/virtualization/kernel/vm.cc SRC_CC += spec/arm_v7/virtualization/kernel/vm.cc

2
repos/base-hw/lib/mk/spec/arm_v7/core-hw-imx53_qsb.inc
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@ -9,7 +9,7 @@
INC_DIR += $(REP_DIR)/src/core/spec/imx53_qsb INC_DIR += $(REP_DIR)/src/core/spec/imx53_qsb
INC_DIR += $(REP_DIR)/src/core/spec/imx53 INC_DIR += $(REP_DIR)/src/core/spec/imx53
SRC_CC += spec/imx53/pic.cc SRC_CC += spec/arm/imx_tzic.cc
SRC_CC += spec/imx53/timer.cc SRC_CC += spec/imx53/timer.cc
# include less specific configuration # include less specific configuration

2
repos/base-hw/lib/mk/spec/arm_v7/core-hw-imx7d_sabre.mk
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@ -9,7 +9,7 @@ INC_DIR += $(REP_DIR)/src/core/spec/imx7d_sabre
INC_DIR += $(REP_DIR)/src/core/spec/arm_v7/virtualization INC_DIR += $(REP_DIR)/src/core/spec/arm_v7/virtualization
# add C++ sources # add C++ sources
SRC_CC += spec/arm_gic/pic.cc SRC_CC += spec/arm/gicv2.cc
SRC_CC += spec/arndale/platform_services.cc SRC_CC += spec/arndale/platform_services.cc
SRC_CC += spec/imx7d_sabre/timer.cc SRC_CC += spec/imx7d_sabre/timer.cc
SRC_CC += kernel/vm_thread_on.cc SRC_CC += kernel/vm_thread_on.cc

2
repos/base-hw/lib/mk/spec/arm_v7/core-hw-odroid_xu.mk
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@ -8,7 +8,7 @@
INC_DIR += $(REP_DIR)/src/core/spec/odroid_xu INC_DIR += $(REP_DIR)/src/core/spec/odroid_xu
# add C++ sources # add C++ sources
SRC_CC += spec/arm_gic/pic.cc SRC_CC += spec/arm/gicv2.cc
SRC_CC += kernel/vm_thread_off.cc SRC_CC += kernel/vm_thread_off.cc
SRC_CC += platform_services.cc SRC_CC += platform_services.cc

2
repos/base-hw/lib/mk/spec/arm_v7/core-hw-usb_armory.mk
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@ -16,7 +16,7 @@ SRC_CC += kernel/vm_thread_on.cc
SRC_CC += spec/arm_v7/trustzone/kernel/vm.cc SRC_CC += spec/arm_v7/trustzone/kernel/vm.cc
SRC_CC += spec/arm_v7/vm_session_component.cc SRC_CC += spec/arm_v7/vm_session_component.cc
SRC_CC += spec/arm_v7/trustzone/vm_session_component.cc SRC_CC += spec/arm_v7/trustzone/vm_session_component.cc
SRC_CC += spec/imx53/pic.cc SRC_CC += spec/arm/imx_tzic.cc
SRC_CC += spec/imx53/timer.cc SRC_CC += spec/imx53/timer.cc
# add assembly sources # add assembly sources

2
repos/base-hw/lib/mk/spec/arm_v8/core-hw-rpi3.mk
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@ -10,7 +10,7 @@ SRC_CC += spec/arm_v8/cpu.cc
SRC_CC += spec/arm_v8/kernel/thread.cc SRC_CC += spec/arm_v8/kernel/thread.cc
SRC_CC += spec/arm_v8/kernel/cpu.cc SRC_CC += spec/arm_v8/kernel/cpu.cc
SRC_CC += spec/arm/platform_support.cc SRC_CC += spec/arm/platform_support.cc
SRC_CC += spec/rpi3/pic.cc SRC_CC += spec/arm/bcm2837_pic.cc
SRC_CC += spec/rpi3/timer.cc SRC_CC += spec/rpi3/timer.cc
SRC_CC += spec/64bit/memory_map.cc SRC_CC += spec/64bit/memory_map.cc

1
repos/base-hw/lib/mk/spec/cortex_a15/core-hw.inc
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@ -6,7 +6,6 @@
# add include paths # add include paths
INC_DIR += $(BASE_DIR)/../base-hw/src/core/spec/cortex_a15 INC_DIR += $(BASE_DIR)/../base-hw/src/core/spec/cortex_a15
INC_DIR += $(BASE_DIR)/../base-hw/src/core/spec/arm_gic
# add C++ sources # add C++ sources
SRC_CC += spec/cortex_a15/cpu.cc SRC_CC += spec/cortex_a15/cpu.cc

3
repos/base-hw/lib/mk/spec/cortex_a9/core-hw.inc
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@ -6,12 +6,11 @@
# add include paths # add include paths
INC_DIR += $(BASE_DIR)/../base-hw/src/core/spec/cortex_a9 INC_DIR += $(BASE_DIR)/../base-hw/src/core/spec/cortex_a9
INC_DIR += $(BASE_DIR)/../base-hw/src/core/spec/arm_gic
# add C++ sources # add C++ sources
SRC_CC += spec/cortex_a9/board.cc SRC_CC += spec/cortex_a9/board.cc
SRC_CC += spec/cortex_a9/timer.cc SRC_CC += spec/cortex_a9/timer.cc
SRC_CC += spec/arm_gic/pic.cc SRC_CC += spec/arm/gicv2.cc
SRC_CC += spec/arm/kernel/lock.cc SRC_CC += spec/arm/kernel/lock.cc
SRC_CC += kernel/vm_thread_off.cc SRC_CC += kernel/vm_thread_off.cc
SRC_CC += kernel/cpu_mp.cc SRC_CC += kernel/cpu_mp.cc

2
repos/base-hw/src/bootstrap/platform.h
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@ -47,6 +47,7 @@ class Bootstrap::Platform
Mmio_space const core_mmio; Mmio_space const core_mmio;
unsigned cpus { NR_OF_CPUS }; unsigned cpus { NR_OF_CPUS };
::Board::Boot_info info { }; ::Board::Boot_info info { };
::Board::Pic pic { };
Board(); Board();
}; };
@ -123,7 +124,6 @@ class Bootstrap::Platform
Board board { }; Board board { };
Bootstrap::Cpu cpu { }; Bootstrap::Cpu cpu { };
Bootstrap::Pic pic { };
Ram_allocator ram_alloc { }; Ram_allocator ram_alloc { };
Memory_region const bootstrap_region; Memory_region const bootstrap_region;
Genode::Constructible<Pd> core_pd { }; Genode::Constructible<Pd> core_pd { };

2
repos/base-hw/src/bootstrap/spec/arm/cortex_a9_mmu.cc
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@ -118,7 +118,7 @@ unsigned Bootstrap::Platform::enable_mmu()
Actlr::disable_smp(); Actlr::disable_smp();
/* locally initialize interrupt controller */ /* locally initialize interrupt controller */
pic.init_cpu_local(); board.pic.init_cpu_local();
Cpu::invalidate_data_cache(); Cpu::invalidate_data_cache();
data_cache_invalidated.inc(); data_cache_invalidated.inc();

26
repos/base-hw/src/bootstrap/spec/arndale/pic.cc → repos/base-hw/src/bootstrap/spec/arm/gicv2.cc
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@ -5,25 +5,23 @@
*/ */
/* /*
* Copyright (C) 2012-2017 Genode Labs GmbH * Copyright (C) 2012-2019 Genode Labs GmbH
* *
* This file is part of the Genode OS framework, which is distributed * This file is part of the Genode OS framework, which is distributed
* under the terms of the GNU Affero General Public License version 3. * under the terms of the GNU Affero General Public License version 3.
*/ */
#include <hw/spec/arm/cortex_a15.h> #include <board.h>
#include <spec/arm/pic.h>
#include <platform.h>
using Bootstrap::Platform; void Board::Pic::init_cpu_local()
void Bootstrap::Pic::init_cpu_local()
{ {
if (Board::NON_SECURE) {
_cpui.write<Cpu_interface::Ctlr>(0); _cpui.write<Cpu_interface::Ctlr>(0);
/* mark software-generated IRQs as being non-secure */ /* mark software-generated IRQs as being non-secure */
for (unsigned i = 0; i < min_spi; i++) for (unsigned i = 0; i < min_spi; i++)
_distr.write<Distributor::Igroupr::Group_status>(1, i); _distr.write<Distributor::Igroupr::Group_status>(1, i);
}
/* disable the priority filter */ /* disable the priority filter */
_cpui.write<Cpu_interface::Pmr::Priority>(_distr.min_priority()); _cpui.write<Cpu_interface::Pmr::Priority>(_distr.min_priority());
@ -33,14 +31,18 @@ void Bootstrap::Pic::init_cpu_local()
/* enable device */ /* enable device */
Cpu_interface::Ctlr::access_t v = 0; Cpu_interface::Ctlr::access_t v = 0;
if (Board::NON_SECURE) {
Cpu_interface::Ctlr::Enable_grp0::set(v, 1); Cpu_interface::Ctlr::Enable_grp0::set(v, 1);
Cpu_interface::Ctlr::Enable_grp1::set(v, 1); Cpu_interface::Ctlr::Enable_grp1::set(v, 1);
Cpu_interface::Ctlr::Fiq_en::set(v, 1); Cpu_interface::Ctlr::Fiq_en::set(v, 1);
} else {
Cpu_interface::Ctlr::Enable::set(v, 1);
}
_cpui.write<Cpu_interface::Ctlr>(v); _cpui.write<Cpu_interface::Ctlr>(v);
} }
Hw::Pic::Pic() Hw::Gicv2::Gicv2()
: _distr(Board::Cpu_mmio::IRQ_CONTROLLER_DISTR_BASE), : _distr(Board::Cpu_mmio::IRQ_CONTROLLER_DISTR_BASE),
_cpui (Board::Cpu_mmio::IRQ_CONTROLLER_CPU_BASE), _cpui (Board::Cpu_mmio::IRQ_CONTROLLER_CPU_BASE),
_last_iar(Cpu_interface::Iar::Irq_id::bits(spurious_id)), _last_iar(Cpu_interface::Iar::Irq_id::bits(spurious_id)),
@ -51,15 +53,21 @@ Hw::Pic::Pic()
/* configure every shared peripheral interrupt */ /* configure every shared peripheral interrupt */
for (unsigned i = min_spi; i <= _max_irq; i++) { for (unsigned i = min_spi; i <= _max_irq; i++) {
/* mark as non-secure */ if (Board::NON_SECURE) {
_distr.write<Distributor::Igroupr::Group_status>(1, i); _distr.write<Distributor::Igroupr::Group_status>(1, i);
}
_distr.write<Distributor::Icfgr::Edge_triggered>(0, i); _distr.write<Distributor::Icfgr::Edge_triggered>(0, i);
_distr.write<Distributor::Ipriorityr::Priority>(0, i); _distr.write<Distributor::Ipriorityr::Priority>(0, i);
_distr.write<Distributor::Icenabler::Clear_enable>(1, i); _distr.write<Distributor::Icenabler::Clear_enable>(1, i);
} }
/* enable device */ /* enable device */
Distributor::Ctlr::access_t v = 0; Distributor::Ctlr::access_t v = 0;
if (Board::NON_SECURE) {
Distributor::Ctlr::Enable_grp0::set(v, 1); Distributor::Ctlr::Enable_grp0::set(v, 1);
Distributor::Ctlr::Enable_grp1::set(v, 1); Distributor::Ctlr::Enable_grp1::set(v, 1);
} else {
Distributor::Ctlr::Enable::set(v, 1);
}
_distr.write<Distributor::Ctlr>(v); _distr.write<Distributor::Ctlr>(v);
} }

12
repos/base-hw/src/bootstrap/spec/arm/pic.h → repos/base-hw/src/bootstrap/spec/arm/gicv2.h
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@ -11,16 +11,16 @@
* under the terms of the GNU Affero General Public License version 3. * under the terms of the GNU Affero General Public License version 3.
*/ */
#ifndef _SRC__BOOTSTRAP__SPEC__ARM__PIC_H_ #ifndef _SRC__BOOTSTRAP__SPEC__ARM__GICV2_H_
#define _SRC__BOOTSTRAP__SPEC__ARM__PIC_H_ #define _SRC__BOOTSTRAP__SPEC__ARM__GICV2_H_
#include <hw/spec/arm/pic.h> #include <hw/spec/arm/gicv2.h>
namespace Bootstrap { struct Pic; } namespace Board { struct Pic; }
struct Bootstrap::Pic : Hw::Pic struct Board::Pic : Hw::Gicv2
{ {
void init_cpu_local(); void init_cpu_local();
}; };
#endif /* _SRC__BOOTSTRAP__SPEC__ARM__PIC_H_ */ #endif /* _SRC__BOOTSTRAP__SPEC__ARM__GICV2_H_ */

49
repos/base-hw/src/bootstrap/spec/arm/pic.cc
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@ -1,49 +0,0 @@
/*
* \brief Programmable interrupt controller for core
* \author Stefan Kalkowski
* \date 2012-10-24
*/
/*
* Copyright (C) 2012-2013 Genode Labs GmbH
*
* This file is part of the Genode OS framework, which is distributed
* under the terms of the GNU Affero General Public License version 3.
*/
#include <spec/arm/pic.h>
#include <platform.h>
using Bootstrap::Platform;
void Bootstrap::Pic::init_cpu_local()
{
/* disable the priority filter */
_cpui.write<Cpu_interface::Pmr::Priority>(_distr.min_priority());
/* disable preemption of IRQ handling by other IRQs */
_cpui.write<Cpu_interface::Bpr::Binary_point>(~0);
/* enable device */
_cpui.write<Cpu_interface::Ctlr::Enable>(1);
}
Hw::Pic::Pic()
: _distr(Board::Cpu_mmio::IRQ_CONTROLLER_DISTR_BASE),
_cpui (Board::Cpu_mmio::IRQ_CONTROLLER_CPU_BASE),
_last_iar(Cpu_interface::Iar::Irq_id::bits(spurious_id)),
_max_irq(_distr.max_irq())
{
/* disable device */
_distr.write<Distributor::Ctlr::Enable>(0);
/* configure every shared peripheral interrupt */
for (unsigned i = min_spi; i <= _max_irq; i++) {
_distr.write<Distributor::Icfgr::Edge_triggered>(0, i);
_distr.write<Distributor::Ipriorityr::Priority>(0, i);
_distr.write<Distributor::Icenabler::Clear_enable>(1, i);
}
/* enable device */
_distr.write<Distributor::Ctlr::Enable>(1);
}

8
repos/base-hw/src/bootstrap/spec/arndale/board.h
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@ -17,8 +17,12 @@
#include <hw/spec/arm/arndale_board.h> #include <hw/spec/arm/arndale_board.h>
#include <hw/spec/arm/lpae.h> #include <hw/spec/arm/lpae.h>
#include <spec/arm/cpu.h> #include <spec/arm/cpu.h>
#include <spec/arm/pic.h> #include <spec/arm/gicv2.h>
namespace Board { using namespace Hw::Arndale_board; } namespace Board {
using namespace Hw::Arndale_board;
static constexpr bool NON_SECURE = true;
}
#endif /* _SRC__BOOTSTRAP__SPEC__ARNDALE__BOARD_H_ */ #endif /* _SRC__BOOTSTRAP__SPEC__ARNDALE__BOARD_H_ */

2
repos/base-hw/src/bootstrap/spec/arndale/platform.cc
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@ -153,7 +153,7 @@ static inline void switch_to_supervisor_mode()
unsigned Bootstrap::Platform::enable_mmu() unsigned Bootstrap::Platform::enable_mmu()
{ {
static volatile bool primary_cpu = true; static volatile bool primary_cpu = true;
pic.init_cpu_local(); board.pic.init_cpu_local();
prepare_nonsecure_world(); prepare_nonsecure_world();
prepare_hypervisor((addr_t)core_pd->table_base); prepare_hypervisor((addr_t)core_pd->table_base);

4
repos/base-hw/src/bootstrap/spec/imx53_qsb/board.h
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@ -23,9 +23,9 @@
namespace Board { namespace Board {
using namespace Hw::Imx53_qsb_board; using namespace Hw::Imx53_qsb_board;
using Hw::Pic;
bool secure_irq(unsigned irq); bool secure_irq(unsigned irq);
} }
namespace Bootstrap { using Hw::Pic; }
#endif /* _SRC__BOOTSTRAP__SPEC__IMX53_QSB__BOARD_H_ */ #endif /* _SRC__BOOTSTRAP__SPEC__IMX53_QSB__BOARD_H_ */

4
repos/base-hw/src/bootstrap/spec/imx6q_sabrelite/board.h
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@ -18,13 +18,15 @@
#include <spec/arm/cortex_a9_actlr.h> #include <spec/arm/cortex_a9_actlr.h>
#include <spec/arm/cortex_a9_page_table.h> #include <spec/arm/cortex_a9_page_table.h>
#include <spec/arm/cpu.h> #include <spec/arm/cpu.h>
#include <spec/arm/pic.h> #include <spec/arm/gicv2.h>
namespace Board { namespace Board {
using namespace Hw::Imx6q_sabrelite_board; using namespace Hw::Imx6q_sabrelite_board;
struct L2_cache; struct L2_cache;
static constexpr bool NON_SECURE = false;
static volatile unsigned long initial_values[][2] { static volatile unsigned long initial_values[][2] {
// (IOMUX Controller) // (IOMUX Controller)
{ 0x20e0004, 0x48613005 }, { 0x20e0004, 0x48613005 },

4
repos/base-hw/src/bootstrap/spec/imx7d_sabre/board.h
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@ -17,10 +17,12 @@
#include <hw/spec/arm/imx7d_sabre_board.h> #include <hw/spec/arm/imx7d_sabre_board.h>
#include <hw/spec/arm/lpae.h> #include <hw/spec/arm/lpae.h>
#include <spec/arm/cpu.h> #include <spec/arm/cpu.h>
#include <spec/arm/pic.h> #include <spec/arm/gicv2.h>
namespace Board { namespace Board {
using namespace Hw::Imx7d_sabre_board; using namespace Hw::Imx7d_sabre_board;
static constexpr bool NON_SECURE = true;
} }
#endif /* _SRC__BOOTSTRAP__SPEC__IMX&_SABRELITE__BOARD_H_ */ #endif /* _SRC__BOOTSTRAP__SPEC__IMX&_SABRELITE__BOARD_H_ */

2
repos/base-hw/src/bootstrap/spec/imx7d_sabre/platform.cc
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@ -287,7 +287,7 @@ unsigned Bootstrap::Platform::enable_mmu()
{ {
static volatile bool primary_cpu = true; static volatile bool primary_cpu = true;
static unsigned long timer_freq = Cpu::Cntfrq::read(); static unsigned long timer_freq = Cpu::Cntfrq::read();
pic.init_cpu_local(); board.pic.init_cpu_local();
prepare_nonsecure_world(timer_freq); prepare_nonsecure_world(timer_freq);
prepare_hypervisor((addr_t)core_pd->table_base); prepare_hypervisor((addr_t)core_pd->table_base);

4
repos/base-hw/src/bootstrap/spec/nit6_solox/board.h
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@ -18,13 +18,15 @@
#include <spec/arm/cortex_a9_actlr.h> #include <spec/arm/cortex_a9_actlr.h>
#include <spec/arm/cortex_a9_page_table.h> #include <spec/arm/cortex_a9_page_table.h>
#include <spec/arm/cpu.h> #include <spec/arm/cpu.h>
#include <spec/arm/pic.h> #include <spec/arm/gicv2.h>
namespace Board { namespace Board {
using namespace Hw::Nit6_solox_board; using namespace Hw::Nit6_solox_board;
struct L2_cache; struct L2_cache;
static constexpr bool NON_SECURE = false;
static volatile unsigned long initial_values[][2] { static volatile unsigned long initial_values[][2] {
// (IOMUX Controller) // (IOMUX Controller)
{ 0x20E006C, 0x0}, { 0x20E006C, 0x0},

3
repos/base-hw/src/bootstrap/spec/odroid_xu/board.h
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@ -17,10 +17,11 @@
#include <hw/spec/arm/odroid_xu_board.h> #include <hw/spec/arm/odroid_xu_board.h>
#include <hw/spec/arm/lpae.h> #include <hw/spec/arm/lpae.h>
#include <spec/arm/cpu.h> #include <spec/arm/cpu.h>
#include <spec/arm/pic.h> #include <spec/arm/gicv2.h>
namespace Board { namespace Board {
using namespace Hw::Odroid_xu_board; using namespace Hw::Odroid_xu_board;
static constexpr bool NON_SECURE = false;
} }
#endif /* _SRC__BOOTSTRAP__SPEC__ODROID_XU__BOARD_H_ */ #endif /* _SRC__BOOTSTRAP__SPEC__ODROID_XU__BOARD_H_ */

2
repos/base-hw/src/bootstrap/spec/odroid_xu/platform.cc
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@ -25,7 +25,7 @@ Bootstrap::Platform::Board::Board()
unsigned Bootstrap::Platform::enable_mmu() unsigned Bootstrap::Platform::enable_mmu()
{ {
pic.init_cpu_local(); board.pic.init_cpu_local();
Cpu::Sctlr::init(); Cpu::Sctlr::init();
Cpu::Cpsr::init(); Cpu::Cpsr::init();
cpu.invalidate_data_cache(); cpu.invalidate_data_cache();

4
repos/base-hw/src/bootstrap/spec/panda/board.h
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@ -17,11 +17,13 @@
#include <hw/spec/arm/panda_board.h> #include <hw/spec/arm/panda_board.h>
#include <spec/arm/cortex_a9_page_table.h> #include <spec/arm/cortex_a9_page_table.h>
#include <spec/arm/cpu.h> #include <spec/arm/cpu.h>
#include <spec/arm/pic.h> #include <spec/arm/gicv2.h>
namespace Board { namespace Board {
using namespace Hw::Panda_board; using namespace Hw::Panda_board;
static constexpr bool NON_SECURE = false;
class L2_cache; class L2_cache;
} }

4
repos/base-hw/src/bootstrap/spec/pbxa9/board.h
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@ -19,10 +19,12 @@
#include <spec/arm/cortex_a9_actlr.h> #include <spec/arm/cortex_a9_actlr.h>
#include <spec/arm/cortex_a9_page_table.h> #include <spec/arm/cortex_a9_page_table.h>
#include <spec/arm/cpu.h> #include <spec/arm/cpu.h>
#include <spec/arm/pic.h> #include <spec/arm/gicv2.h>
namespace Board { namespace Board {
using namespace Hw::Pbxa9_board; using namespace Hw::Pbxa9_board;
static constexpr bool NON_SECURE = false;
} }
#endif /* _SRC__BOOTSTRAP__SPEC__PBXA9__BOARD_H_ */ #endif /* _SRC__BOOTSTRAP__SPEC__PBXA9__BOARD_H_ */

3
repos/base-hw/src/bootstrap/spec/riscv/board.h
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@ -18,8 +18,11 @@
namespace Board { namespace Board {
using namespace Hw::Riscv_board; using namespace Hw::Riscv_board;
struct Pic {};
} }
namespace Bootstrap { struct Cpu {}; }
template <typename E, unsigned B, unsigned S> template <typename E, unsigned B, unsigned S>
void Sv39::Level_x_translation_table<E, B, S>::_translation_added(addr_t, size_t) void Sv39::Level_x_translation_table<E, B, S>::_translation_added(addr_t, size_t)
{ } { }

4
repos/base-hw/src/bootstrap/spec/rpi/board.h
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@ -20,9 +20,9 @@
namespace Board { namespace Board {
using namespace Hw::Rpi_board; using namespace Hw::Rpi_board;
}
namespace Bootstrap { struct Pic {}; } struct Pic {};
}
constexpr unsigned Hw::Page_table::Descriptor_base::_device_tex() { constexpr unsigned Hw::Page_table::Descriptor_base::_device_tex() {

2
repos/base-hw/src/bootstrap/spec/rpi3/board.h
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@ -20,11 +20,11 @@
namespace Bootstrap { namespace Bootstrap {
using Cpu = Hw::Arm_64_cpu; using Cpu = Hw::Arm_64_cpu;
struct Pic {};
}; };
namespace Board { namespace Board {
using namespace Hw::Rpi3_board; using namespace Hw::Rpi3_board;
struct Pic {};
}; };
#endif /* _BOOTSTRAP__SPEC__RPI3__BOARD_H_ */ #endif /* _BOOTSTRAP__SPEC__RPI3__BOARD_H_ */

4
repos/base-hw/src/bootstrap/spec/usb_armory/board.h
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@ -20,11 +20,11 @@
#include <spec/arm/cortex_a8_page_table.h> #include <spec/arm/cortex_a8_page_table.h>
#include <spec/arm/cpu.h> #include <spec/arm/cpu.h>
namespace Bootstrap { using Hw::Pic; }
namespace Board { namespace Board {
using namespace Hw::Usb_armory_board; using namespace Hw::Usb_armory_board;
using Hw::Pic;
bool secure_irq(unsigned irq); bool secure_irq(unsigned irq);
} }

4
repos/base-hw/src/bootstrap/spec/wand_quad/board.h
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@ -18,13 +18,15 @@
#include <spec/arm/cortex_a9_actlr.h> #include <spec/arm/cortex_a9_actlr.h>
#include <spec/arm/cortex_a9_page_table.h> #include <spec/arm/cortex_a9_page_table.h>
#include <spec/arm/cpu.h> #include <spec/arm/cpu.h>
#include <spec/arm/pic.h> #include <spec/arm/gicv2.h>
namespace Board { namespace Board {
using namespace Hw::Wand_quad_board; using namespace Hw::Wand_quad_board;
struct L2_cache; struct L2_cache;
static constexpr bool NON_SECURE = false;
static volatile unsigned long initial_values[][2] { static volatile unsigned long initial_values[][2] {
// (IOMUX Controller) // (IOMUX Controller)
{ 0x20e0000, 0x1 }, { 0x20e0000, 0x1 },

2
repos/base-hw/src/bootstrap/spec/x86_64/board.h
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@ -20,12 +20,12 @@
#include <hw/spec/x86_64/x86_64.h> #include <hw/spec/x86_64/x86_64.h>
namespace Bootstrap { namespace Bootstrap {
struct Pic {};
using Cpu = Hw::X86_64_cpu; using Cpu = Hw::X86_64_cpu;
} }
namespace Board { namespace Board {
using namespace Hw::Pc_board; using namespace Hw::Pc_board;
struct Pic {};
} }
#endif /* _SRC__BOOTSTRAP__SPEC__X86_64__BOARD_H_ */ #endif /* _SRC__BOOTSTRAP__SPEC__X86_64__BOARD_H_ */

3
repos/base-hw/src/bootstrap/spec/zynq_qemu/board.h
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@ -18,10 +18,11 @@
#include <spec/arm/cortex_a9_actlr.h> #include <spec/arm/cortex_a9_actlr.h>
#include <spec/arm/cortex_a9_page_table.h> #include <spec/arm/cortex_a9_page_table.h>
#include <spec/arm/cpu.h> #include <spec/arm/cpu.h>
#include <spec/arm/pic.h> #include <spec/arm/gicv2.h>
namespace Board { namespace Board {
using namespace Hw::Zynq_qemu_board; using namespace Hw::Zynq_qemu_board;
static constexpr bool NON_SECURE = false;
} }
#endif /* _SRC__BOOTSTRAP__SPEC__ZYNQ__BOARD_H_ */ #endif /* _SRC__BOOTSTRAP__SPEC__ZYNQ__BOARD_H_ */

11
repos/base-hw/src/core/kernel/cpu.cc
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@ -18,7 +18,6 @@
#include <kernel/thread.h> #include <kernel/thread.h>
#include <kernel/irq.h> #include <kernel/irq.h>
#include <kernel/pd.h> #include <kernel/pd.h>
#include <pic.h>
#include <board.h> #include <board.h>
#include <hw/assert.h> #include <hw/assert.h>
#include <hw/boot_info.h> #include <hw/boot_info.h>
@ -56,7 +55,7 @@ void Cpu_job::_interrupt(unsigned const /* cpu_id */)
{ {
/* determine handling for specific interrupt */ /* determine handling for specific interrupt */
unsigned irq_id; unsigned irq_id;
if (pic().take_request(irq_id)) if (_cpu->pic().take_request(irq_id))
/* is the interrupt a cpu-local one */ /* is the interrupt a cpu-local one */
if (!_cpu->interrupt(irq_id)) { if (!_cpu->interrupt(irq_id)) {
@ -68,7 +67,7 @@ void Cpu_job::_interrupt(unsigned const /* cpu_id */)
} }
/* end interrupt request at controller */ /* end interrupt request at controller */
pic().finish_request(); _cpu->pic().finish_request();
} }
@ -158,7 +157,7 @@ addr_t Cpu::stack_start() {
return (addr_t)&kernel_stack + KERNEL_STACK_SIZE * (_id+1); } return (addr_t)&kernel_stack + KERNEL_STACK_SIZE * (_id+1); }
Cpu::Cpu(unsigned const id, Pic & pic, Cpu::Cpu(unsigned const id, Board::Pic & pic,
Inter_processor_work_list & global_work_list) Inter_processor_work_list & global_work_list)
: :
_id(id), _pic(pic), _timer(*this), _id(id), _pic(pic), _timer(*this),
@ -172,10 +171,10 @@ Cpu::Cpu(unsigned const id, Pic & pic,
** Cpu_pool ** ** Cpu_pool **
**************/ **************/
bool Cpu_pool::initialize(Pic & pic) bool Cpu_pool::initialize()
{ {
unsigned id = Cpu::executing_id(); unsigned id = Cpu::executing_id();
_cpus[id].construct(id, pic, _global_work_list); _cpus[id].construct(id, _pic, _global_work_list);
return --_initialized == 0; return --_initialized == 0;
} }

9
repos/base-hw/src/core/kernel/cpu.h
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@ -18,6 +18,7 @@
#include <util/reconstructible.h> #include <util/reconstructible.h>
/* core includes */ /* core includes */
#include <board.h>
#include <kernel/cpu_context.h> #include <kernel/cpu_context.h>
#include <kernel/irq.h> #include <kernel/irq.h>
#include <kernel/inter_processor_work.h> #include <kernel/inter_processor_work.h>
@ -111,7 +112,7 @@ class Kernel::Cpu : public Genode::Cpu, private Irq::Pool, private Timeout
unsigned const _id; unsigned const _id;
Pic &_pic; Board::Pic &_pic;
Timer _timer; Timer _timer;
Cpu_scheduler _scheduler; Cpu_scheduler _scheduler;
Idle_thread _idle; Idle_thread _idle;
@ -131,7 +132,7 @@ class Kernel::Cpu : public Genode::Cpu, private Irq::Pool, private Timeout
/** /**
* Construct object for CPU 'id' * Construct object for CPU 'id'
*/ */
Cpu(unsigned const id, Pic & pic, Cpu(unsigned const id, Board::Pic & pic,
Inter_processor_work_list & global_work_list); Inter_processor_work_list & global_work_list);
static inline unsigned primary_id() { return 0; } static inline unsigned primary_id() { return 0; }
@ -159,6 +160,7 @@ class Kernel::Cpu : public Genode::Cpu, private Irq::Pool, private Timeout
*/ */
Cpu_job& schedule(); Cpu_job& schedule();
Board::Pic & pic() { return _pic; }
Timer & timer() { return _timer; } Timer & timer() { return _timer; }
addr_t stack_start(); addr_t stack_start();
@ -189,6 +191,7 @@ class Kernel::Cpu_pool
{ {
private: private:
Board::Pic _pic {};
Inter_processor_work_list _global_work_list {}; Inter_processor_work_list _global_work_list {};
unsigned _count; unsigned _count;
unsigned _initialized { _count }; unsigned _initialized { _count };
@ -198,7 +201,7 @@ class Kernel::Cpu_pool
Cpu_pool(); Cpu_pool();
bool initialize(Pic & pic); bool initialize();
/** /**
* Return object of CPU 'id' * Return object of CPU 'id'

4
repos/base-hw/src/core/kernel/cpu_mp.cc
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@ -41,9 +41,9 @@ void Cpu::trigger_ip_interrupt()
/* check whether there is still an IPI send */ /* check whether there is still an IPI send */
if (_ipi_irq.pending) return; if (_ipi_irq.pending) return;
pic().send_ipi(_id); _pic.send_ipi(_id);
_ipi_irq.pending = true; _ipi_irq.pending = true;
} }
Cpu::Ipi::Ipi(Cpu & cpu) : Irq(Pic::IPI, cpu), cpu(cpu) { } Cpu::Ipi::Ipi(Cpu & cpu) : Irq(Board::Pic::IPI, cpu), cpu(cpu) { }

5
repos/base-hw/src/core/kernel/init.cc
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@ -18,7 +18,6 @@
#include <kernel/kernel.h> #include <kernel/kernel.h>
#include <kernel/lock.h> #include <kernel/lock.h>
#include <platform_pd.h> #include <platform_pd.h>
#include <pic.h>
#include <board.h> #include <board.h>
#include <platform_thread.h> #include <platform_thread.h>
@ -34,8 +33,6 @@ Pd &Kernel::core_pd() {
return unmanaged_singleton<Genode::Core_platform_pd>()->kernel_pd(); } return unmanaged_singleton<Genode::Core_platform_pd>()->kernel_pd(); }
Pic &Kernel::pic() { return *unmanaged_singleton<Pic>(); }
extern "C" void kernel_init(); extern "C" void kernel_init();
/** /**
@ -62,7 +59,7 @@ extern "C" void kernel_init()
lock_ready = true; lock_ready = true;
/* initialize current cpu */ /* initialize current cpu */
pool_ready = cpu_pool().initialize(pic()); pool_ready = cpu_pool().initialize();
}; };
/* wait until all cpus have initialized their corresponding cpu object */ /* wait until all cpus have initialized their corresponding cpu object */

7
repos/base-hw/src/core/kernel/irq.cc
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@ -15,13 +15,14 @@
#include <kernel/kernel.h> #include <kernel/kernel.h>
#include <kernel/cpu.h> #include <kernel/cpu.h>
#include <kernel/irq.h> #include <kernel/irq.h>
#include <pic.h>
void Kernel::Irq::disable() const { pic().mask(_irq_nr); } void Kernel::Irq::disable() const {
cpu_pool().executing_cpu().pic().mask(_irq_nr); }
void Kernel::Irq::enable() const { pic().unmask(_irq_nr, Cpu::executing_id()); } void Kernel::Irq::enable() const {
cpu_pool().executing_cpu().pic().unmask(_irq_nr, Cpu::executing_id()); }
Kernel::Irq::Pool &Kernel::User_irq::_pool() Kernel::Irq::Pool &Kernel::User_irq::_pool()

3
repos/base-hw/src/core/kernel/kernel.h
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@ -15,8 +15,6 @@
#ifndef _CORE__KERNEL__KERNEL_H_ #ifndef _CORE__KERNEL__KERNEL_H_
#define _CORE__KERNEL__KERNEL_H_ #define _CORE__KERNEL__KERNEL_H_
#include <pic.h>
/** /**
* Main routine of every kernel pass * Main routine of every kernel pass
*/ */
@ -28,7 +26,6 @@ namespace Kernel {
class Pd; class Pd;
Pd &core_pd(); Pd &core_pd();
Pic &pic();
} }
#endif /* _CORE__KERNEL__KERNEL_H_ */ #endif /* _CORE__KERNEL__KERNEL_H_ */

1
repos/base-hw/src/core/kernel/thread.cc
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@ -31,7 +31,6 @@
#include <kernel/log.h> #include <kernel/log.h>
#include <map_local.h> #include <map_local.h>
#include <platform_pd.h> #include <platform_pd.h>
#include <pic.h>
extern "C" void _core_start(void); extern "C" void _core_start(void);

5
repos/base-hw/src/core/platform.cc
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@ -24,7 +24,6 @@
#include <platform_pd.h> #include <platform_pd.h>
#include <hw/page_flags.h> #include <hw/page_flags.h>
#include <hw/util.h> #include <hw/util.h>
#include <pic.h>
#include <kernel/kernel.h> #include <kernel/kernel.h>
#include <translation_table.h> #include <translation_table.h>
#include <kernel/cpu.h> #include <kernel/cpu.h>
@ -163,14 +162,14 @@ Platform::Platform()
_init_io_port_alloc(); _init_io_port_alloc();
/* make all non-kernel interrupts available to the interrupt allocator */ /* make all non-kernel interrupts available to the interrupt allocator */
for (unsigned i = 0; i < Kernel::Pic::NR_OF_IRQ; i++) { for (unsigned i = 0; i < Board::Pic::NR_OF_IRQ; i++) {
bool kernel_resource = false; bool kernel_resource = false;
Kernel::cpu_pool().for_each_cpu([&] (Kernel::Cpu & cpu) { Kernel::cpu_pool().for_each_cpu([&] (Kernel::Cpu & cpu) {
if (i == cpu.timer().interrupt_id()) { if (i == cpu.timer().interrupt_id()) {
kernel_resource = true; kernel_resource = true;
} }
}); });
if (i == Pic::IPI) { if (i == Board::Pic::IPI) {
kernel_resource = true; kernel_resource = true;
} }
if (kernel_resource) { if (kernel_resource) {

22
repos/base-hw/src/core/spec/rpi/pic.cc → repos/base-hw/src/core/spec/arm/bcm2835_pic.cc
View File

@ -1,5 +1,5 @@
/* /*
* \brief Pic implementation specific to Rpi * \brief Pic implementation specific to Rpi 1
* \author Norman Feske * \author Norman Feske
* \author Stefan Kalkowski * \author Stefan Kalkowski
* \date 2016-01-07 * \date 2016-01-07
@ -12,11 +12,12 @@
* under the terms of the GNU Affero General Public License version 3. * under the terms of the GNU Affero General Public License version 3.
*/ */
#include <pic.h> #include <board.h>
#include <platform.h> #include <platform.h>
using namespace Genode;
bool Genode::Usb_dwc_otg::_need_trigger_sof(uint32_t host_frame, bool Board::Pic::Usb_dwc_otg::_need_trigger_sof(uint32_t host_frame,
uint32_t scheduled_frame) uint32_t scheduled_frame)
{ {
uint32_t const max_frame = 0x3fff; uint32_t const max_frame = 0x3fff;
@ -35,7 +36,8 @@ bool Genode::Usb_dwc_otg::_need_trigger_sof(uint32_t host_frame,
} }
Genode::Usb_dwc_otg::Usb_dwc_otg() : Mmio(Platform::mmio_to_virt(Board::USB_DWC_OTG_BASE)) Board::Pic::Usb_dwc_otg::Usb_dwc_otg()
: Mmio(Platform::mmio_to_virt(Board::USB_DWC_OTG_BASE))
{ {
write<Guid::Num>(0); write<Guid::Num>(0);
write<Guid::Num_valid>(false); write<Guid::Num_valid>(false);
@ -43,7 +45,7 @@ Genode::Usb_dwc_otg::Usb_dwc_otg() : Mmio(Platform::mmio_to_virt(Board::USB_DWC_
} }
bool Genode::Usb_dwc_otg::handle_sof() bool Board::Pic::Usb_dwc_otg::handle_sof()
{ {
if (!_is_sof()) if (!_is_sof())
return false; return false;
@ -68,11 +70,11 @@ bool Genode::Usb_dwc_otg::handle_sof()
} }
Genode::Pic::Pic() Board::Pic::Pic()
: Mmio(Platform::mmio_to_virt(Board::IRQ_CONTROLLER_BASE)) { mask(); } : Mmio(Platform::mmio_to_virt(Board::IRQ_CONTROLLER_BASE)) { mask(); }
bool Genode::Pic::take_request(unsigned &irq) bool Board::Pic::take_request(unsigned &irq)
{ {
/* read basic IRQ status mask */ /* read basic IRQ status mask */
uint32_t const p = read<Irq_pending_basic>(); uint32_t const p = read<Irq_pending_basic>();
@ -106,7 +108,7 @@ bool Genode::Pic::take_request(unsigned &irq)
} }
void Genode::Pic::mask() void Board::Pic::mask()
{ {
write<Irq_disable_basic>(~0); write<Irq_disable_basic>(~0);
write<Irq_disable_gpu_1>(~0); write<Irq_disable_gpu_1>(~0);
@ -114,7 +116,7 @@ void Genode::Pic::mask()
} }
void Genode::Pic::unmask(unsigned const i, unsigned) void Board::Pic::unmask(unsigned const i, unsigned)
{ {
if (i < 8) if (i < 8)
write<Irq_enable_basic>(1 << i); write<Irq_enable_basic>(1 << i);
@ -125,7 +127,7 @@ void Genode::Pic::unmask(unsigned const i, unsigned)
} }
void Genode::Pic::mask(unsigned const i) void Board::Pic::mask(unsigned const i)
{ {
if (i < 8) if (i < 8)
write<Irq_disable_basic>(1 << i); write<Irq_disable_basic>(1 << i);

88
repos/base-hw/src/core/spec/rpi/pic.h → repos/base-hw/src/core/spec/arm/bcm2835_pic.h
View File

@ -11,28 +11,48 @@
* under the terms of the GNU Affero General Public License version 3. * under the terms of the GNU Affero General Public License version 3.
*/ */
#ifndef _CORE__SPEC__RPI__PIC_H_ #ifndef _CORE__SPEC__ARM__BCM2835_PIC_H_
#define _CORE__SPEC__RPI__PIC_H_ #define _CORE__SPEC__ARM__BCM2835_PIC_H_
/* Genode includes */ /* Genode includes */
#include <util/mmio.h> #include <util/mmio.h>
/* core includes */ namespace Board { class Pic; }
#include <board.h>
namespace Genode
class Board::Pic : Genode::Mmio
{ {
/** public:
* Programmable interrupt controller for core
enum {
NR_OF_IRQ = 64,
/*
* dummy IPI value on non-SMP platform,
* only used in interrupt reservation within generic code
*/ */
class Pic; IPI,
};
class Usb_dwc_otg; private:
}
struct Irq_pending_basic : Register<0x0, 32>
{
struct Timer : Bitfield<0, 1> { };
struct Gpu : Bitfield<8, 2> { };
};
class Genode::Usb_dwc_otg : Mmio struct Irq_pending_gpu_1 : Register<0x04, 32> { };
{ struct Irq_pending_gpu_2 : Register<0x08, 32> { };
struct Irq_enable_gpu_1 : Register<0x10, 32> { };
struct Irq_enable_gpu_2 : Register<0x14, 32> { };
struct Irq_enable_basic : Register<0x18, 32> { };
struct Irq_disable_gpu_1 : Register<0x1c, 32> { };
struct Irq_disable_gpu_2 : Register<0x20, 32> { };
struct Irq_disable_basic : Register<0x24, 32> { };
class Usb_dwc_otg : Genode::Mmio
{
private: private:
struct Core_irq_status : Register<0x14, 32> struct Core_irq_status : Register<0x14, 32>
@ -65,54 +85,23 @@ class Genode::Usb_dwc_otg : Mmio
return read<Core_irq_status::Sof>(); return read<Core_irq_status::Sof>();
} }
static bool _need_trigger_sof(uint32_t host_frame, static bool _need_trigger_sof(Genode::uint32_t host_frame,
uint32_t scheduled_frame); Genode::uint32_t scheduled_frame);
public: public:
Usb_dwc_otg(); Usb_dwc_otg();
bool handle_sof(); bool handle_sof();
};
class Genode::Pic : Mmio
{
public:
enum {
NR_OF_IRQ = 64,
/*
* dummy IPI value on non-SMP platform,
* only used in interrupt reservation within generic code
*/
IPI,
}; };
private:
struct Irq_pending_basic : Register<0x0, 32>
{
struct Timer : Bitfield<0, 1> { };
struct Gpu : Bitfield<8, 2> { };
};
struct Irq_pending_gpu_1 : Register<0x04, 32> { };
struct Irq_pending_gpu_2 : Register<0x08, 32> { };
struct Irq_enable_gpu_1 : Register<0x10, 32> { };
struct Irq_enable_gpu_2 : Register<0x14, 32> { };
struct Irq_enable_basic : Register<0x18, 32> { };
struct Irq_disable_gpu_1 : Register<0x1c, 32> { };
struct Irq_disable_gpu_2 : Register<0x20, 32> { };
struct Irq_disable_basic : Register<0x24, 32> { };
Usb_dwc_otg _usb { }; Usb_dwc_otg _usb { };
/** /**
* Return true if specified interrupt is pending * Return true if specified interrupt is pending
*/ */
static bool _is_pending(unsigned i, uint32_t p1, uint32_t p2) static bool _is_pending(unsigned i, Genode::uint32_t p1,
Genode::uint32_t p2)
{ {
return i < 32 ? (p1 & (1 << i)) : (p2 & (1 << (i - 32))); return i < 32 ? (p1 & (1 << i)) : (p2 & (1 << (i - 32)));
} }
@ -121,7 +110,6 @@ class Genode::Pic : Mmio
Pic(); Pic();
void init_cpu_local() { }
bool take_request(unsigned &irq); bool take_request(unsigned &irq);
void finish_request() { } void finish_request() { }
void mask(); void mask();
@ -131,6 +119,4 @@ class Genode::Pic : Mmio
static constexpr bool fast_interrupts() { return false; } static constexpr bool fast_interrupts() { return false; }
}; };
namespace Kernel { using Genode::Pic; } #endif /* _CORE__SPEC__ARM__BCM2835_PIC_H_ */
#endif /* _CORE__SPEC__RPI__PIC_H_ */

14
repos/base-hw/src/core/spec/rpi3/pic.cc → repos/base-hw/src/core/spec/arm/bcm2837_pic.cc
View File

@ -11,15 +11,15 @@
* under the terms of the GNU Affero General Public License version 3. * under the terms of the GNU Affero General Public License version 3.
*/ */
#include <pic.h> #include <board.h>
#include <platform.h> #include <platform.h>
Genode::Pic::Pic() Board::Pic::Pic()
: Mmio(Platform::mmio_to_virt(Board::LOCAL_IRQ_CONTROLLER_BASE)) { } : Genode::Mmio(Genode::Platform::mmio_to_virt(Board::LOCAL_IRQ_CONTROLLER_BASE)) { }
bool Genode::Pic::take_request(unsigned & irq) bool Board::Pic::take_request(unsigned & irq)
{ {
Core0_irq_source::access_t src = read<Core0_irq_source>(); Core0_irq_source::access_t src = read<Core0_irq_source>();
if ((1 << TIMER_IRQ) & src) { if ((1 << TIMER_IRQ) & src) {
@ -30,10 +30,10 @@ bool Genode::Pic::take_request(unsigned & irq)
} }
void Genode::Pic::mask() { } void Board::Pic::mask() { }
void Genode::Pic::unmask(unsigned const i, unsigned cpu) void Board::Pic::unmask(unsigned const i, unsigned cpu)
{ {
if (cpu > 0) if (cpu > 0)
Genode::raw("multi-core irq controller not implemented yet"); Genode::raw("multi-core irq controller not implemented yet");
@ -47,7 +47,7 @@ void Genode::Pic::unmask(unsigned const i, unsigned cpu)
} }
void Genode::Pic::mask(unsigned const i) void Board::Pic::mask(unsigned const i)
{ {
if (i == TIMER_IRQ) { if (i == TIMER_IRQ) {
write<Core0_timer_irq_control::Cnt_p_ns_irq>(0); write<Core0_timer_irq_control::Cnt_p_ns_irq>(0);

12
repos/base-hw/src/core/spec/rpi3/pic.h → repos/base-hw/src/core/spec/arm/bcm2837_pic.h
View File

@ -11,16 +11,14 @@
* under the terms of the GNU Affero General Public License version 3. * under the terms of the GNU Affero General Public License version 3.
*/ */
#ifndef _CORE__SPEC__RPI3__PIC_H_ #ifndef _CORE__SPEC__ARM__BCM2837_PIC_H_
#define _CORE__SPEC__RPI3__PIC_H_ #define _CORE__SPEC__ARM__BCM2837_PIC_H_
#include <util/mmio.h> #include <util/mmio.h>
#include <board.h>
namespace Genode { class Pic; } namespace Board { class Pic; }
namespace Kernel { using Pic = Genode::Pic; }
class Genode::Pic : Mmio class Board::Pic : Genode::Mmio
{ {
public: public:
@ -66,4 +64,4 @@ class Genode::Pic : Mmio
static constexpr bool fast_interrupts() { return false; } static constexpr bool fast_interrupts() { return false; }
}; };
#endif /* _CORE__SPEC__RPI3__PIC_H_ */ #endif /* _CORE__SPEC__ARM__BCM2837_PIC_H_ */

2
repos/base-hw/src/core/spec/arm/cpu.cc
View File

@ -26,7 +26,7 @@ Arm_cpu::Context::Context(bool privileged)
Psr::access_t v = 0; Psr::access_t v = 0;
Psr::M::set(v, privileged ? Psr::M::SYS : Psr::M::USR); Psr::M::set(v, privileged ? Psr::M::SYS : Psr::M::USR);
if (Genode::Pic::fast_interrupts()) Psr::I::set(v, 1); if (Board::Pic::fast_interrupts()) Psr::I::set(v, 1);
else Psr::F::set(v, 1); else Psr::F::set(v, 1);
Psr::A::set(v, 1); Psr::A::set(v, 1);
cpsr = v; cpsr = v;

5
repos/base-hw/src/core/spec/arm_gic/pic.cc → repos/base-hw/src/core/spec/arm/gicv2.cc
View File

@ -12,13 +12,12 @@
*/ */
/* core includes */ /* core includes */
#include <board.h> #include <hw/spec/arm/gicv2.h>
#include <pic.h>
#include <platform.h> #include <platform.h>
using namespace Genode; using namespace Genode;
Hw::Pic::Pic() Hw::Gicv2::Gicv2()
: _distr(Platform::mmio_to_virt(Board::Cpu_mmio::IRQ_CONTROLLER_DISTR_BASE)), : _distr(Platform::mmio_to_virt(Board::Cpu_mmio::IRQ_CONTROLLER_DISTR_BASE)),
_cpui (Platform::mmio_to_virt(Board::Cpu_mmio::IRQ_CONTROLLER_CPU_BASE)), _cpui (Platform::mmio_to_virt(Board::Cpu_mmio::IRQ_CONTROLLER_CPU_BASE)),
_last_iar(Cpu_interface::Iar::Irq_id::bits(spurious_id)), _last_iar(Cpu_interface::Iar::Irq_id::bits(spurious_id)),

3
repos/base-hw/src/core/spec/imx53/pic.cc → repos/base-hw/src/core/spec/arm/imx_tzic.cc
View File

@ -1,5 +1,5 @@
/* /*
* \brief Programmable interrupt controller for core * \brief Freescale TrustZone aware interrupt controller for core
* \author Stefan Kalkowski * \author Stefan Kalkowski
* \date 2012-10-24 * \date 2012-10-24
*/ */
@ -13,7 +13,6 @@
/* core includes */ /* core includes */
#include <board.h> #include <board.h>
#include <pic.h>
#include <platform.h> #include <platform.h>
using namespace Genode; using namespace Genode;

57
repos/base-hw/src/core/spec/arm_gic/pic.h
View File

@ -1,57 +0,0 @@
/*
* \brief Programmable interrupt controller for core
* \author Martin stein
* \author Stefan Kalkowski
* \date 2011-10-26
*/
/*
* Copyright (C) 2011-2017 Genode Labs GmbH
*
* This file is part of the Genode OS framework, which is distributed
* under the terms of the GNU Affero General Public License version 3.
*/
#ifndef _CORE__SPEC__ARM_GIC__PIC_H_
#define _CORE__SPEC__ARM_GIC__PIC_H_
#include <hw/spec/arm/pic.h>
namespace Genode { class Pic; }
namespace Kernel { using Pic = Genode::Pic; }
class Genode::Pic : public Hw::Pic
{
public:
enum { IPI = 1 };
/**
* Raise inter-processor IRQ of the CPU with kernel name 'cpu_id'
*/
void send_ipi(unsigned const cpu_id)
{
using Sgir = Distributor::Sgir;
Sgir::access_t sgir = 0;
Sgir::Sgi_int_id::set(sgir, IPI);
Sgir::Cpu_target_list::set(sgir, 1 << cpu_id);
_distr.write<Sgir>(sgir);
}
/**
* Raise inter-processor interrupt on all other cores
*/
void send_ipi()
{
using Sgir = Distributor::Sgir;
Sgir::access_t sgir = 0;
Sgir::Sgi_int_id::set(sgir, IPI);
Sgir::Target_list_filter::set(sgir,
Sgir::Target_list_filter::ALL_OTHER);
_distr.write<Sgir>(sgir);
}
static constexpr bool fast_interrupts() { return false; }
};
#endif /* _CORE__SPEC__ARM_GIC__PIC_H_ */

4
repos/base-hw/src/core/spec/arm_v7/trustzone/kernel/vm.cc
View File

@ -62,10 +62,10 @@ void Vm::proceed(Cpu & cpu)
{ {
unsigned const irq = _state->irq_injection; unsigned const irq = _state->irq_injection;
if (irq) { if (irq) {
if (pic().secure(irq)) { if (cpu.pic().secure(irq)) {
Genode::raw("Refuse to inject secure IRQ into VM"); Genode::raw("Refuse to inject secure IRQ into VM");
} else { } else {
pic().trigger(irq); cpu.pic().trigger(irq);
_state->irq_injection = 0; _state->irq_injection = 0;
} }
} }

3
repos/base-hw/src/core/spec/arndale/board.h
View File

@ -14,11 +14,14 @@
#ifndef _CORE__SPEC__ARNDALE__BOARD_H_ #ifndef _CORE__SPEC__ARNDALE__BOARD_H_
#define _CORE__SPEC__ARNDALE__BOARD_H_ #define _CORE__SPEC__ARNDALE__BOARD_H_
#include <hw/spec/arm/gicv2.h>
#include <hw/spec/arm/arndale_board.h> #include <hw/spec/arm/arndale_board.h>
namespace Board { namespace Board {
using namespace Hw::Arndale_board; using namespace Hw::Arndale_board;
using Pic = Hw::Gicv2;
static constexpr bool SMP = true; static constexpr bool SMP = true;
} }

48
repos/base-hw/src/core/spec/imx53/pic.h
View File

@ -1,48 +0,0 @@
/*
* \brief Programmable interrupt controller for core
* \author Stefan Kalkowski
* \date 2012-10-24
*/
/*
* Copyright (C) 2012-2017 Genode Labs GmbH
*
* This file is part of the Genode OS framework, which is distributed
* under the terms of the GNU Affero General Public License version 3.
*/
#ifndef _CORE__SPEC__IMX53__PIC_H_
#define _CORE__SPEC__IMX53__PIC_H_
#include <hw/spec/arm/imx_tzic.h>
namespace Genode { class Pic; }
class Genode::Pic : public Hw::Pic
{
public:
enum {
/*
* FIXME: dummy ipi value on non-SMP platform, should be removed
* when SMP is an aspect of CPUs only compiled where necessary
*/
IPI = 0,
};
/*
* Trigger interrupt 'i' from software if possible
*/
void trigger(unsigned const i) {
write<Swint>(Swint::Intid::bits(i)); }
bool secure(unsigned i) {
return !read<Intsec::Nonsecure>(i); }
static constexpr bool fast_interrupts() { return true; }
};
namespace Kernel { using Pic = Genode::Pic; }
#endif /* _CORE__SPEC__IMX53__PIC_H_ */

3
repos/base-hw/src/core/spec/imx53_qsb/board.h
View File

@ -15,11 +15,12 @@
#ifndef _CORE__SPEC__IMX53_QSB__BOARD_H_ #ifndef _CORE__SPEC__IMX53_QSB__BOARD_H_
#define _CORE__SPEC__IMX53_QSB__BOARD_H_ #define _CORE__SPEC__IMX53_QSB__BOARD_H_
#include <hw/spec/arm/imx_tzic.h>
#include <hw/spec/arm/imx53_qsb_board.h> #include <hw/spec/arm/imx53_qsb_board.h>
namespace Board { namespace Board {
using namespace Hw::Imx53_qsb_board; using namespace Hw::Imx53_qsb_board;
using Hw::Pic;
static constexpr bool SMP = false; static constexpr bool SMP = false;
} }

2
repos/base-hw/src/core/spec/imx6q_sabrelite/board.h
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@ -14,12 +14,14 @@
#ifndef _CORE__SPEC__IMX6Q_SABRELITE__BOARD_H_ #ifndef _CORE__SPEC__IMX6Q_SABRELITE__BOARD_H_
#define _CORE__SPEC__IMX6Q_SABRELITE__BOARD_H_ #define _CORE__SPEC__IMX6Q_SABRELITE__BOARD_H_
#include <hw/spec/arm/gicv2.h>
#include <hw/spec/arm/imx6q_sabrelite_board.h> #include <hw/spec/arm/imx6q_sabrelite_board.h>
namespace Board { namespace Board {
using namespace Hw::Imx6q_sabrelite_board; using namespace Hw::Imx6q_sabrelite_board;
using Pic = Hw::Gicv2;
using L2_cache = Hw::Pl310; using L2_cache = Hw::Pl310;
static constexpr bool SMP = true; static constexpr bool SMP = true;

3
repos/base-hw/src/core/spec/imx7d_sabre/board.h
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@ -14,11 +14,14 @@
#ifndef _CORE__SPEC__IMX7D_SABRE__BOARD_H_ #ifndef _CORE__SPEC__IMX7D_SABRE__BOARD_H_
#define _CORE__SPEC__IMX7D_SABRE__BOARD_H_ #define _CORE__SPEC__IMX7D_SABRE__BOARD_H_
#include <hw/spec/arm/gicv2.h>
#include <hw/spec/arm/imx7d_sabre_board.h> #include <hw/spec/arm/imx7d_sabre_board.h>
namespace Board { namespace Board {
using namespace Hw::Imx7d_sabre_board; using namespace Hw::Imx7d_sabre_board;
using Pic = Hw::Gicv2;
static constexpr bool SMP = true; static constexpr bool SMP = true;
} }

2
repos/base-hw/src/core/spec/nit6_solox/board.h
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@ -14,11 +14,13 @@
#ifndef _CORE__SPEC__NIT6_SOLOX__BOARD_H_ #ifndef _CORE__SPEC__NIT6_SOLOX__BOARD_H_
#define _CORE__SPEC__NIT6_SOLOX__BOARD_H_ #define _CORE__SPEC__NIT6_SOLOX__BOARD_H_
#include <hw/spec/arm/gicv2.h>
#include <hw/spec/arm/nit6_solox_board.h> #include <hw/spec/arm/nit6_solox_board.h>
namespace Board { namespace Board {
using namespace Hw::Nit6_solox_board; using namespace Hw::Nit6_solox_board;
using Pic = Hw::Gicv2;
using L2_cache = Hw::Pl310; using L2_cache = Hw::Pl310;
static constexpr bool SMP = true; static constexpr bool SMP = true;

3
repos/base-hw/src/core/spec/odroid_xu/board.h
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@ -14,11 +14,14 @@
#ifndef _CORE__SPEC__ODROID_XU__BOARD_H_ #ifndef _CORE__SPEC__ODROID_XU__BOARD_H_
#define _CORE__SPEC__ODROID_XU__BOARD_H_ #define _CORE__SPEC__ODROID_XU__BOARD_H_
#include <hw/spec/arm/gicv2.h>
#include <hw/spec/arm/odroid_xu_board.h> #include <hw/spec/arm/odroid_xu_board.h>
namespace Board { namespace Board {
using namespace Hw::Odroid_xu_board; using namespace Hw::Odroid_xu_board;
using Pic = Hw::Gicv2;
static constexpr bool SMP = true; static constexpr bool SMP = true;
} }

3
repos/base-hw/src/core/spec/panda/board.h
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@ -15,11 +15,14 @@
#ifndef _CORE__SPEC__PANDA__BOARD_H_ #ifndef _CORE__SPEC__PANDA__BOARD_H_
#define _CORE__SPEC__PANDA__BOARD_H_ #define _CORE__SPEC__PANDA__BOARD_H_
#include <hw/spec/arm/gicv2.h>
#include <hw/spec/arm/panda_board.h> #include <hw/spec/arm/panda_board.h>
namespace Board { namespace Board {
using namespace Hw::Panda_board; using namespace Hw::Panda_board;
using Pic = Hw::Gicv2;
static constexpr bool SMP = true; static constexpr bool SMP = true;
class L2_cache : public Hw::Pl310 class L2_cache : public Hw::Pl310

3
repos/base-hw/src/core/spec/pbxa9/board.h
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@ -14,11 +14,14 @@
#ifndef _CORE__SPEC__PBXA9__BOARD_H_ #ifndef _CORE__SPEC__PBXA9__BOARD_H_
#define _CORE__SPEC__PBXA9__BOARD_H_ #define _CORE__SPEC__PBXA9__BOARD_H_
#include <hw/spec/arm/gicv2.h>
#include <hw/spec/arm/pbxa9_board.h> #include <hw/spec/arm/pbxa9_board.h>
namespace Board { namespace Board {
using namespace Hw::Pbxa9_board; using namespace Hw::Pbxa9_board;
using Pic = Hw::Gicv2;
static constexpr bool SMP = true; static constexpr bool SMP = true;
L2_cache & l2_cache(); L2_cache & l2_cache();

5
repos/base-hw/src/core/spec/riscv/board.h
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@ -15,9 +15,8 @@
#define _CORE__SPEC__RISCV__BOARD_H_ #define _CORE__SPEC__RISCV__BOARD_H_
#include <hw/spec/riscv/board.h> #include <hw/spec/riscv/board.h>
#include <spec/riscv/pic.h>
namespace Board { namespace Board { using namespace Hw::Riscv_board; }
using namespace Hw::Riscv_board;
}
#endif /* _CORE__SPEC__RISCV__BOARD_H_ */ #endif /* _CORE__SPEC__RISCV__BOARD_H_ */

6
repos/base-hw/src/core/spec/riscv/pic.h
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@ -16,12 +16,12 @@
#ifndef _CORE__SPEC__RISCV__PIC_H_ #ifndef _CORE__SPEC__RISCV__PIC_H_
#define _CORE__SPEC__RISCV__PIC_H_ #define _CORE__SPEC__RISCV__PIC_H_
namespace Genode { class Pic; } namespace Board { class Pic; }
/** /**
* Dummy PIC driver for core * Dummy PIC driver for core
*/ */
class Genode::Pic class Board::Pic
{ {
public: public:
@ -41,6 +41,4 @@ class Genode::Pic
void finish_request() { } void finish_request() { }
}; };
namespace Kernel { class Pic : public Genode::Pic { }; }
#endif /* _CORE__SPEC__RISCV__PIC_H_ */ #endif /* _CORE__SPEC__RISCV__PIC_H_ */

1
repos/base-hw/src/core/spec/rpi/board.h
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@ -16,6 +16,7 @@
#define _CORE__SPEC__RPI__BOARD_H_ #define _CORE__SPEC__RPI__BOARD_H_
#include <hw/spec/arm/rpi_board.h> #include <hw/spec/arm/rpi_board.h>
#include <spec/arm/bcm2835_pic.h>
namespace Board { namespace Board {
using namespace Hw::Rpi_board; using namespace Hw::Rpi_board;

1
repos/base-hw/src/core/spec/rpi3/board.h
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@ -15,6 +15,7 @@
#define _CORE__SPEC__RPI3__BOARD_H_ #define _CORE__SPEC__RPI3__BOARD_H_
#include <hw/spec/arm_64/rpi3_board.h> #include <hw/spec/arm_64/rpi3_board.h>
#include <spec/arm/bcm2837_pic.h>
namespace Board { namespace Board {
using namespace Hw::Rpi3_board; using namespace Hw::Rpi3_board;

2
repos/base-hw/src/core/spec/rpi3/timer.cc
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@ -18,7 +18,7 @@
using namespace Kernel; using namespace Kernel;
unsigned Timer::interrupt_id() const { return Genode::Pic::TIMER_IRQ; } unsigned Timer::interrupt_id() const { return Board::Pic::TIMER_IRQ; }
unsigned long Timer_driver::_freq() { return Genode::Cpu::Cntfrq_el0::read(); } unsigned long Timer_driver::_freq() { return Genode::Cpu::Cntfrq_el0::read(); }

3
repos/base-hw/src/core/spec/usb_armory/board.h
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@ -15,11 +15,14 @@
#ifndef _CORE__SPEC__USB_ARMORY__BOARD_H_ #ifndef _CORE__SPEC__USB_ARMORY__BOARD_H_
#define _CORE__SPEC__USB_ARMORY__BOARD_H_ #define _CORE__SPEC__USB_ARMORY__BOARD_H_
#include <hw/spec/arm/imx_tzic.h>
#include <hw/spec/arm/usb_armory_board.h> #include <hw/spec/arm/usb_armory_board.h>
namespace Board { namespace Board {
using namespace Hw::Usb_armory_board; using namespace Hw::Usb_armory_board;
using Hw::Pic;
static constexpr bool SMP = false; static constexpr bool SMP = false;
} }

2
repos/base-hw/src/core/spec/wand_quad/board.h
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@ -15,12 +15,14 @@
#ifndef _CORE__SPEC__WAND_QUAD__BOARD_H_ #ifndef _CORE__SPEC__WAND_QUAD__BOARD_H_
#define _CORE__SPEC__WAND_QUAD__BOARD_H_ #define _CORE__SPEC__WAND_QUAD__BOARD_H_
#include <hw/spec/arm/gicv2.h>
#include <hw/spec/arm/wand_quad_board.h> #include <hw/spec/arm/wand_quad_board.h>
namespace Board { namespace Board {
using namespace Hw::Wand_quad_board; using namespace Hw::Wand_quad_board;
using L2_cache = Hw::Pl310; using L2_cache = Hw::Pl310;
using Pic = Hw::Gicv2;
static constexpr bool SMP = true; static constexpr bool SMP = true;

1
repos/base-hw/src/core/spec/x86_64/board.h
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@ -15,6 +15,7 @@
#define _CORE__SPEC__X86_64__BOARD_H_ #define _CORE__SPEC__X86_64__BOARD_H_
#include <hw/spec/x86_64/pc_board.h> #include <hw/spec/x86_64/pc_board.h>
#include <spec/x86_64/pic.h>
namespace Board { namespace Board {
using namespace Hw::Pc_board; using namespace Hw::Pc_board;

1
repos/base-hw/src/core/spec/x86_64/muen/board.h
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@ -15,6 +15,7 @@
#define _CORE__SPEC__X86_64__MUEN__BOARD_H_ #define _CORE__SPEC__X86_64__MUEN__BOARD_H_
#include <hw/spec/x86_64/pc_board.h> #include <hw/spec/x86_64/pc_board.h>
#include <spec/x86_64/muen/pic.h>
namespace Board { namespace Board {
using namespace Hw::Pc_board; using namespace Hw::Pc_board;

3
repos/base-hw/src/core/spec/x86_64/muen/kernel/thread_exception.cc
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@ -15,7 +15,6 @@
/* core includes */ /* core includes */
#include <kernel/cpu.h> #include <kernel/cpu.h>
#include <kernel/thread.h> #include <kernel/thread.h>
#include <pic.h>
using namespace Kernel; using namespace Kernel;
@ -35,7 +34,7 @@ void Thread::exception(Cpu & cpu)
} }
if (regs->trapno >= Cpu::Context::INTERRUPTS_START && if (regs->trapno >= Cpu::Context::INTERRUPTS_START &&
regs->trapno <= Cpu::Context::INTERRUPTS_END) { regs->trapno <= Cpu::Context::INTERRUPTS_END) {
pic().irq_occurred(regs->trapno); cpu.pic().irq_occurred(regs->trapno);
_interrupt(cpu.id()); _interrupt(cpu.id());
return; return;
} }

3
repos/base-hw/src/core/spec/x86_64/muen/kernel/vm.cc
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@ -18,7 +18,6 @@
#include <kernel/cpu.h> #include <kernel/cpu.h>
#include <kernel/vm.h> #include <kernel/vm.h>
#include <kernel/vm_state.h> #include <kernel/vm_state.h>
#include <pic.h>
Kernel::Vm::Vm(void * const state, Kernel::Signal_context * const context, Kernel::Vm::Vm(void * const state, Kernel::Signal_context * const context,
void * const) void * const)
@ -44,7 +43,7 @@ void Kernel::Vm::exception(Cpu & cpu)
if (_state->trapno >= Genode::Cpu_state::INTERRUPTS_START && if (_state->trapno >= Genode::Cpu_state::INTERRUPTS_START &&
_state->trapno <= Genode::Cpu_state::INTERRUPTS_END) { _state->trapno <= Genode::Cpu_state::INTERRUPTS_END) {
pic().irq_occurred(_state->trapno); cpu.pic().irq_occurred(_state->trapno);
_interrupt(cpu.id()); _interrupt(cpu.id());
_context->submit(1); _context->submit(1);
return; return;

6
repos/base-hw/src/core/spec/x86_64/muen/pic.h
View File

@ -14,7 +14,7 @@
#ifndef _CORE__SPEC__X86_64__MUEN__PIC_H_ #ifndef _CORE__SPEC__X86_64__MUEN__PIC_H_
#define _CORE__SPEC__X86_64__MUEN__PIC_H_ #define _CORE__SPEC__X86_64__MUEN__PIC_H_
namespace Genode namespace Board
{ {
/** /**
* Programmable interrupt controller for core * Programmable interrupt controller for core
@ -22,7 +22,7 @@ namespace Genode
class Pic; class Pic;
} }
class Genode::Pic class Board::Pic
{ {
public: public:
@ -68,6 +68,4 @@ class Genode::Pic
bool isr[NR_OF_IRQ] = {false}; bool isr[NR_OF_IRQ] = {false};
}; };
namespace Kernel { class Pic : public Genode::Pic { }; }
#endif /* _CORE__SPEC__X86_64__MUEN__PIC_H_ */ #endif /* _CORE__SPEC__X86_64__MUEN__PIC_H_ */

4
repos/base-hw/src/core/spec/x86_64/pic.cc
View File

@ -19,10 +19,10 @@
/* core includes */ /* core includes */
#include <port_io.h> #include <port_io.h>
#include <pic.h>
#include <platform.h> #include <platform.h>
using namespace Genode; using namespace Genode;
using namespace Board;
uint8_t Pic::lapic_ids[NR_OF_CPUS]; uint8_t Pic::lapic_ids[NR_OF_CPUS];
@ -123,6 +123,8 @@ void Pic::send_ipi(unsigned const cpu_id) {
Ioapic::Irq_mode Ioapic::_irq_mode[IRQ_COUNT]; Ioapic::Irq_mode Ioapic::_irq_mode[IRQ_COUNT];
enum { REMAP_BASE = Board::VECTOR_REMAP_BASE };
void Ioapic::setup_irq_mode(unsigned irq_number, unsigned trigger, void Ioapic::setup_irq_mode(unsigned irq_number, unsigned trigger,
unsigned polarity) unsigned polarity)
{ {

14
repos/base-hw/src/core/spec/x86_64/pic.h
View File

@ -21,7 +21,7 @@
/* core includes */ /* core includes */
#include <board.h> #include <board.h>
namespace Genode namespace Board
{ {
/* /*
* Redirection table entry * Redirection table entry
@ -41,19 +41,17 @@ namespace Genode
enum { IRQ_COUNT = 256 }; enum { IRQ_COUNT = 256 };
} }
struct Genode::Irte : Register<64> struct Board::Irte : Genode::Register<64>
{ {
struct Pol : Bitfield<13, 1> { }; struct Pol : Bitfield<13, 1> { };
struct Trg : Bitfield<15, 1> { }; struct Trg : Bitfield<15, 1> { };
struct Mask : Bitfield<16, 1> { }; struct Mask : Bitfield<16, 1> { };
}; };
class Genode::Ioapic : public Mmio class Board::Ioapic : public Genode::Mmio
{ {
private: private:
enum { REMAP_BASE = Board::VECTOR_REMAP_BASE };
/* Number of Redirection Table entries */ /* Number of Redirection Table entries */
unsigned _irte_count = 0; unsigned _irte_count = 0;
@ -135,7 +133,7 @@ class Genode::Ioapic : public Mmio
}; };
}; };
class Genode::Pic : public Mmio class Board::Pic : public Genode::Mmio
{ {
private: private:
@ -180,7 +178,7 @@ class Genode::Pic : public Mmio
/** /**
* Mapping of our logical boot CPUs to the local APIC IDs * Mapping of our logical boot CPUs to the local APIC IDs
*/ */
static uint8_t lapic_ids[NR_OF_CPUS]; static Genode::uint8_t lapic_ids[NR_OF_CPUS];
public: public:
@ -217,6 +215,4 @@ class Genode::Pic : public Mmio
void send_ipi(unsigned const); void send_ipi(unsigned const);
}; };
namespace Kernel { using Genode::Pic; }
#endif /* _CORE__SPEC__X86_64__PIC_H_ */ #endif /* _CORE__SPEC__X86_64__PIC_H_ */

10
repos/base-hw/src/core/spec/x86_64/platform_support.cc
View File

@ -13,7 +13,7 @@
#include <bios_data_area.h> #include <bios_data_area.h>
#include <platform.h> #include <platform.h>
#include <kernel/kernel.h> #include <kernel/cpu.h>
#include <map_local.h> #include <map_local.h>
using namespace Genode; using namespace Genode;
@ -60,8 +60,12 @@ void Platform::_init_additional_platform_info(Xml_generator &xml)
void Platform::setup_irq_mode(unsigned irq_number, unsigned trigger, void Platform::setup_irq_mode(unsigned irq_number, unsigned trigger,
unsigned polarity) { unsigned polarity)
Kernel::pic().ioapic.setup_irq_mode(irq_number, trigger, polarity); } {
Kernel::cpu_pool().executing_cpu().pic().ioapic.setup_irq_mode(irq_number,
trigger,
polarity);
}
bool Platform::get_msi_params(addr_t, addr_t &, addr_t &, unsigned &) { bool Platform::get_msi_params(addr_t, addr_t &, addr_t &, unsigned &) {

3
repos/base-hw/src/core/spec/zynq_qemu/board.h
View File

@ -16,11 +16,14 @@
#ifndef _CORE__SPEC__ZYNQ_QEMU__BOARD_H_ #ifndef _CORE__SPEC__ZYNQ_QEMU__BOARD_H_
#define _CORE__SPEC__ZYNQ_QEMU__BOARD_H_ #define _CORE__SPEC__ZYNQ_QEMU__BOARD_H_
#include <hw/spec/arm/gicv2.h>
#include <hw/spec/arm/zynq_qemu_board.h> #include <hw/spec/arm/zynq_qemu_board.h>
namespace Board { namespace Board {
using namespace Hw::Zynq_qemu_board; using namespace Hw::Zynq_qemu_board;
using Pic = Hw::Gicv2;
static constexpr bool SMP = true; static constexpr bool SMP = true;
L2_cache & l2_cache(); L2_cache & l2_cache();

32
repos/base-hw/src/include/hw/spec/arm/pic.h → repos/base-hw/src/include/hw/spec/arm/gicv2.h
View File

@ -1,25 +1,25 @@
/* /*
* \brief Programmable interrupt controller for core * \brief ARM generic interrupt controller v2
* \author Martin stein * \author Martin stein
* \author Stefan Kalkowski * \author Stefan Kalkowski
* \date 2011-10-26 * \date 2011-10-26
*/ */
/* /*
* Copyright (C) 2011-2013 Genode Labs GmbH * Copyright (C) 2011-2019 Genode Labs GmbH
* *
* This file is part of the Genode OS framework, which is distributed * This file is part of the Genode OS framework, which is distributed
* under the terms of the GNU Affero General Public License version 3. * under the terms of the GNU Affero General Public License version 3.
*/ */
#ifndef _SRC__LIB__HW__SPEC__ARM__PIC_H_ #ifndef _SRC__LIB__HW__SPEC__ARM__GICv2_H_
#define _SRC__LIB__HW__SPEC__ARM__PIC_H_ #define _SRC__LIB__HW__SPEC__ARM__GICv2_H_
#include <util/mmio.h> #include <util/mmio.h>
namespace Hw { class Pic; } namespace Hw { class Gicv2; }
class Hw::Pic class Hw::Gicv2
{ {
protected: protected:
@ -176,9 +176,9 @@ class Hw::Pic
public: public:
enum { NR_OF_IRQ = Distributor::nr_of_irq }; enum { IPI = 1, NR_OF_IRQ = Distributor::nr_of_irq };
Pic(); Gicv2();
/** /**
* Try to take an IRQ and return wether it was successful * Try to take an IRQ and return wether it was successful
@ -219,6 +219,20 @@ class Hw::Pic
*/ */
void mask(unsigned const irq_id) { void mask(unsigned const irq_id) {
_distr.write<Distributor::Icenabler::Clear_enable>(1, irq_id); } _distr.write<Distributor::Icenabler::Clear_enable>(1, irq_id); }
/**
* Raise inter-processor IRQ of the CPU with kernel name 'cpu_id'
*/
void send_ipi(unsigned const cpu_id)
{
using Sgir = Distributor::Sgir;
Sgir::access_t sgir = 0;
Sgir::Sgi_int_id::set(sgir, IPI);
Sgir::Cpu_target_list::set(sgir, 1 << cpu_id);
_distr.write<Sgir>(sgir);
}
static constexpr bool fast_interrupts() { return false; }
}; };
#endif /* _SRC__LIB__HW__SPEC__ARM__PIC_H_ */ #endif /* _SRC__LIB__HW__SPEC__ARM__GICv2_H_ */

13
repos/base-hw/src/include/hw/spec/arm/imx_tzic.h
View File

@ -85,6 +85,8 @@ class Hw::Pic : public Genode::Mmio
public: public:
enum { IPI = 0xffff };
Pic(); Pic();
/** /**
@ -113,6 +115,17 @@ class Hw::Pic : public Genode::Mmio
*/ */
void mask(unsigned const i) { void mask(unsigned const i) {
if (_valid(i)) { write<Enclear::Clear_enable>(1, i); } } if (_valid(i)) { write<Enclear::Clear_enable>(1, i); } }
/*
* Trigger interrupt 'i' from software if possible
*/
void trigger(unsigned const i) {
write<Swint>(Swint::Intid::bits(i)); }
bool secure(unsigned i) {
return !read<Intsec::Nonsecure>(i); }
static constexpr bool fast_interrupts() { return true; }
}; };
#endif /* _SRC__LIB__HW__SPEC__ARM__IMX_TZIC_H_ */ #endif /* _SRC__LIB__HW__SPEC__ARM__IMX_TZIC_H_ */

5
repos/base-hw/src/include/hw/spec/riscv/board.h
View File

@ -19,11 +19,6 @@
#include <hw/spec/riscv/uart.h> #include <hw/spec/riscv/uart.h>
#include <drivers/defs/riscv.h> #include <drivers/defs/riscv.h>
namespace Bootstrap {
struct Cpu {};
struct Pic {};
}
namespace Hw::Riscv_board { namespace Hw::Riscv_board {
using namespace Riscv; using namespace Riscv;