vmm_arm: support for i.MX7 Dual SABRE board

Fix #3285
This commit is contained in:
Stefan Kalkowski 2019-04-10 12:43:17 +02:00 committed by Christian Helmuth
parent 0e94d7410d
commit 7a45867841
6 changed files with 50 additions and 21 deletions

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@ -0,0 +1,30 @@
/*
* \brief Definitions for Armv7
* \author Stefan Kalkowski
* \date 2019-04-10
*/
/*
* Copyright (C) 2019 Genode Labs GmbH
*
* This file is part of the Genode OS framework, which is distributed
* under the terms of the GNU Affero General Public License version 3.
*/
#ifndef _INCLUDE__DRIVERS__DEFS__ARM_V7_H_
#define _INCLUDE__DRIVERS__DEFS__ARM_V7_H_
namespace Arm_v7 {
enum Interrupts {
/******************************
** Virtualization extension **
******************************/
VT_MAINTAINANCE_IRQ = 25,
VT_TIMER_IRQ = 27,
};
};
#endif /* _INCLUDE__DRIVERS__DEFS__ARM_V7_H_ */

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@ -11,10 +11,15 @@
* under the terms of the GNU Affero General Public License version 3.
*/
#include <drivers/defs/arm_v7.h>
#ifndef _INCLUDE__DRIVERS__DEFS__EXYNOS5_H_
#define _INCLUDE__DRIVERS__DEFS__EXYNOS5_H_
namespace Exynos5 {
using namespace Arm_v7;
enum {
/* normal RAM */
RAM_0_BASE = 0x40000000,
@ -32,10 +37,6 @@ namespace Exynos5 {
IRQ_CONTROLLER_VT_CPU_BASE = 0x10486000,
IRQ_CONTROLLER_VT_CPU_SIZE = 0x1000,
/* virtual interrupts */
VT_MAINTAINANCE_IRQ = 25,
VT_TIMER_IRQ = 27,
/* UART */
UART_2_MMIO_BASE = 0x12C20000,
UART_2_MMIO_SIZE = 0x1000,

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@ -14,8 +14,12 @@
#ifndef _INCLUDE__DRIVERS__DEFS__IMX7D_SABRE_H_
#define _INCLUDE__DRIVERS__DEFS__IMX7D_SABRE_H_
#include <drivers/defs/arm_v7.h>
namespace Imx7d_sabre {
using namespace Arm_v7;
enum {
RAM_0_BASE = 0x80000000UL,
RAM_0_SIZE = 0x40000000UL,
@ -35,9 +39,6 @@ namespace Imx7d_sabre {
TIMER_CLOCK = 1000000000UL,
CACHE_LINE_SIZE_LOG2 = 6,
VT_MAINTAINANCE_IRQ,
VT_TIMER_IRQ,
};
}

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@ -5,11 +5,14 @@
#
assert_spec hw
assert_spec arndale
if { ![have_spec imx7d_sabre] && ![have_spec arndale] } {
puts "Run script is not supported on this platform"
exit 0
}
set build_components {
core init timer
drivers/platform
server/terminal_crosslink
test/terminal_expect_send
server/vmm
@ -33,11 +36,6 @@ install_config {
<any-service><parent/><any-child/></any-service>
</default-route>
<default caps="100"/>
<start name="platform_drv">
<resource name="RAM" quantum="1M"/>
<provides><service name="Regulator"/></provides>
<config/>
</start>
<start name="timer">
<resource name="RAM" quantum="1M"/>
<provides><service name="Timer"/></provides>
@ -91,7 +89,6 @@ if {![file exists bin/dtb]} {
set boot_modules {
core ld.lib.so init
platform_drv
timer
terminal_crosslink
test-terminal_expect_send

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@ -19,7 +19,7 @@
#include <base/heap.h>
#include <base/log.h>
#include <cpu/cpu_state.h>
#include <drivers/defs/exynos5.h>
#include <drivers/defs/arm_v7.h>
#include <os/ring_buffer.h>
#include <terminal_session/connection.h>
#include <timer_session/connection.h>
@ -648,7 +648,7 @@ class Vmm
enum Irqs {
SGI_MAX = 15,
TIMER = Exynos5::VT_TIMER_IRQ,
TIMER = Arm_v7::VT_TIMER_IRQ,
MAX_IRQ = 256,
};
@ -887,7 +887,7 @@ class Vmm
void irq_occured()
{
switch(_vm.state().gic_irq) {
case Exynos5::VT_MAINTAINANCE_IRQ:
case Arm_v7::VT_MAINTAINANCE_IRQ:
_handle_eoi();
return;
case TIMER:
@ -913,7 +913,7 @@ class Vmm
{
_vm.state().timer_ctrl = 5;
_vm.state().timer_val = 0xffffffff;
_gic.inject_irq(Exynos5::VT_TIMER_IRQ);
_gic.inject_irq(Arm_v7::VT_TIMER_IRQ);
}
public:
@ -930,7 +930,7 @@ class Vmm
_gic(gic)
{
_timer.sigh(_handler);
_gic.register_irq(Exynos5::VT_TIMER_IRQ, this, true);
_gic.register_irq(Arm_v7::VT_TIMER_IRQ, this, true);
}
void schedule_timeout()

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@ -1,5 +1,5 @@
TARGET = vmm
REQUIRES = arndale hw
REQUIRES = hw arm_v7
LIBS = base
SRC_CC = main.cc
INC_DIR += $(PRG_DIR)