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repos/base/include/drivers/defs/arm_v7.h
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30
repos/base/include/drivers/defs/arm_v7.h
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/*
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* \brief Definitions for Armv7
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* \author Stefan Kalkowski
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* \date 2019-04-10
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*/
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/*
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* Copyright (C) 2019 Genode Labs GmbH
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*
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* This file is part of the Genode OS framework, which is distributed
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* under the terms of the GNU Affero General Public License version 3.
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*/
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#ifndef _INCLUDE__DRIVERS__DEFS__ARM_V7_H_
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#define _INCLUDE__DRIVERS__DEFS__ARM_V7_H_
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namespace Arm_v7 {
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enum Interrupts {
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/******************************
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** Virtualization extension **
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******************************/
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VT_MAINTAINANCE_IRQ = 25,
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VT_TIMER_IRQ = 27,
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};
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};
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#endif /* _INCLUDE__DRIVERS__DEFS__ARM_V7_H_ */
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@ -11,10 +11,15 @@
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* under the terms of the GNU Affero General Public License version 3.
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* under the terms of the GNU Affero General Public License version 3.
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*/
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*/
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#include <drivers/defs/arm_v7.h>
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#ifndef _INCLUDE__DRIVERS__DEFS__EXYNOS5_H_
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#ifndef _INCLUDE__DRIVERS__DEFS__EXYNOS5_H_
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#define _INCLUDE__DRIVERS__DEFS__EXYNOS5_H_
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#define _INCLUDE__DRIVERS__DEFS__EXYNOS5_H_
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namespace Exynos5 {
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namespace Exynos5 {
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using namespace Arm_v7;
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enum {
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enum {
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/* normal RAM */
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/* normal RAM */
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RAM_0_BASE = 0x40000000,
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RAM_0_BASE = 0x40000000,
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@ -32,10 +37,6 @@ namespace Exynos5 {
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IRQ_CONTROLLER_VT_CPU_BASE = 0x10486000,
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IRQ_CONTROLLER_VT_CPU_BASE = 0x10486000,
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IRQ_CONTROLLER_VT_CPU_SIZE = 0x1000,
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IRQ_CONTROLLER_VT_CPU_SIZE = 0x1000,
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/* virtual interrupts */
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VT_MAINTAINANCE_IRQ = 25,
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VT_TIMER_IRQ = 27,
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/* UART */
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/* UART */
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UART_2_MMIO_BASE = 0x12C20000,
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UART_2_MMIO_BASE = 0x12C20000,
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UART_2_MMIO_SIZE = 0x1000,
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UART_2_MMIO_SIZE = 0x1000,
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@ -14,8 +14,12 @@
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#ifndef _INCLUDE__DRIVERS__DEFS__IMX7D_SABRE_H_
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#ifndef _INCLUDE__DRIVERS__DEFS__IMX7D_SABRE_H_
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#define _INCLUDE__DRIVERS__DEFS__IMX7D_SABRE_H_
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#define _INCLUDE__DRIVERS__DEFS__IMX7D_SABRE_H_
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#include <drivers/defs/arm_v7.h>
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namespace Imx7d_sabre {
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namespace Imx7d_sabre {
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using namespace Arm_v7;
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enum {
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enum {
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RAM_0_BASE = 0x80000000UL,
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RAM_0_BASE = 0x80000000UL,
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RAM_0_SIZE = 0x40000000UL,
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RAM_0_SIZE = 0x40000000UL,
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@ -35,9 +39,6 @@ namespace Imx7d_sabre {
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TIMER_CLOCK = 1000000000UL,
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TIMER_CLOCK = 1000000000UL,
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CACHE_LINE_SIZE_LOG2 = 6,
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CACHE_LINE_SIZE_LOG2 = 6,
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VT_MAINTAINANCE_IRQ,
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VT_TIMER_IRQ,
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};
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};
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}
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}
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@ -5,11 +5,14 @@
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#
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#
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assert_spec hw
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assert_spec hw
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assert_spec arndale
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if { ![have_spec imx7d_sabre] && ![have_spec arndale] } {
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puts "Run script is not supported on this platform"
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exit 0
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}
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set build_components {
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set build_components {
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core init timer
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core init timer
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drivers/platform
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server/terminal_crosslink
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server/terminal_crosslink
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test/terminal_expect_send
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test/terminal_expect_send
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server/vmm
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server/vmm
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@ -33,11 +36,6 @@ install_config {
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<any-service><parent/><any-child/></any-service>
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<any-service><parent/><any-child/></any-service>
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</default-route>
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</default-route>
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<default caps="100"/>
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<default caps="100"/>
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<start name="platform_drv">
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<resource name="RAM" quantum="1M"/>
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<provides><service name="Regulator"/></provides>
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<config/>
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</start>
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<start name="timer">
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<start name="timer">
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<resource name="RAM" quantum="1M"/>
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<resource name="RAM" quantum="1M"/>
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<provides><service name="Timer"/></provides>
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<provides><service name="Timer"/></provides>
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@ -91,7 +89,6 @@ if {![file exists bin/dtb]} {
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set boot_modules {
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set boot_modules {
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core ld.lib.so init
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core ld.lib.so init
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platform_drv
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timer
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timer
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terminal_crosslink
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terminal_crosslink
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test-terminal_expect_send
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test-terminal_expect_send
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#include <base/heap.h>
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#include <base/heap.h>
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#include <base/log.h>
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#include <base/log.h>
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#include <cpu/cpu_state.h>
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#include <cpu/cpu_state.h>
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#include <drivers/defs/exynos5.h>
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#include <drivers/defs/arm_v7.h>
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#include <os/ring_buffer.h>
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#include <os/ring_buffer.h>
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#include <terminal_session/connection.h>
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#include <terminal_session/connection.h>
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#include <timer_session/connection.h>
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#include <timer_session/connection.h>
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@ -648,7 +648,7 @@ class Vmm
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enum Irqs {
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enum Irqs {
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SGI_MAX = 15,
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SGI_MAX = 15,
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TIMER = Exynos5::VT_TIMER_IRQ,
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TIMER = Arm_v7::VT_TIMER_IRQ,
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MAX_IRQ = 256,
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MAX_IRQ = 256,
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};
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};
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@ -887,7 +887,7 @@ class Vmm
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void irq_occured()
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void irq_occured()
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{
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{
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switch(_vm.state().gic_irq) {
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switch(_vm.state().gic_irq) {
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case Exynos5::VT_MAINTAINANCE_IRQ:
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case Arm_v7::VT_MAINTAINANCE_IRQ:
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_handle_eoi();
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_handle_eoi();
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return;
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return;
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case TIMER:
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case TIMER:
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{
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{
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_vm.state().timer_ctrl = 5;
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_vm.state().timer_ctrl = 5;
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_vm.state().timer_val = 0xffffffff;
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_vm.state().timer_val = 0xffffffff;
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_gic.inject_irq(Exynos5::VT_TIMER_IRQ);
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_gic.inject_irq(Arm_v7::VT_TIMER_IRQ);
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}
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}
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public:
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public:
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_gic(gic)
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_gic(gic)
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{
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{
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_timer.sigh(_handler);
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_timer.sigh(_handler);
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_gic.register_irq(Exynos5::VT_TIMER_IRQ, this, true);
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_gic.register_irq(Arm_v7::VT_TIMER_IRQ, this, true);
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}
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}
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void schedule_timeout()
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void schedule_timeout()
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TARGET = vmm
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TARGET = vmm
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REQUIRES = arndale hw
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REQUIRES = hw arm_v7
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LIBS = base
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LIBS = base
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SRC_CC = main.cc
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SRC_CC = main.cc
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INC_DIR += $(PRG_DIR)
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INC_DIR += $(PRG_DIR)
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