mirror of
https://github.com/genodelabs/genode.git
synced 2024-12-18 21:27:56 +00:00
Sebastian Sumpf
Norman Feske
parent
0fc2db50f0
commit
75509d77b5
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riscv
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0x80200000
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INC_DIR += $(REP_DIR)/src/bootstrap/board/riscv_qemu
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SRC_CC += bootstrap/spec/riscv/platform.cc
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SRC_S += bootstrap/spec/riscv/crt0.s
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SRC_CC += lib/base/riscv/kernel/interface.cc
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SRC_CC += spec/64bit/memory_map.cc
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vpath spec/64bit/memory_map.cc $(REP_DIR)/src/lib/hw
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include $(REP_DIR)/lib/mk/bootstrap-hw.inc
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REP_INC_DIR += src/core/spec/riscv src/core/board/riscv_qemu
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CC_OPT += -fno-delete-null-pointer-checks
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# add C++ sources
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SRC_CC += platform_services.cc
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SRC_CC += kernel/vm_thread_off.cc
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SRC_CC += kernel/cpu_up.cc
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SRC_CC += kernel/lock.cc
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SRC_CC += spec/riscv/kernel/thread.cc
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SRC_CC += spec/riscv/kernel/cpu.cc
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SRC_CC += spec/riscv/kernel/interface.cc
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SRC_CC += spec/riscv/kernel/pd.cc
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SRC_CC += spec/riscv/cpu.cc
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SRC_CC += spec/riscv/pic.cc
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SRC_CC += spec/riscv/platform_support.cc
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SRC_CC += spec/riscv/timer.cc
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SRC_CC += spec/64bit/memory_map.cc
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#add assembly sources
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SRC_S += spec/riscv/exception_vector.s
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SRC_S += spec/riscv/crt0.s
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vpath spec/64bit/memory_map.cc $(call select_from_repositories,src/lib/hw)
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# include less specific configuration
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include $(call select_from_repositories,lib/mk/core-hw.inc)
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include $(GENODE_DIR)/repos/base-hw/recipes/src/base-hw_content.inc
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2021-11-29 065c3a960169cb275938c657083d377e8a86ad35
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base-hw
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base
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/*
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* \brief RISC-V Qemu specific board definitions
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* \author Stefan Kalkowski
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* \date 2017-02-20
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*/
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/*
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* Copyright (C) 2017 Genode Labs GmbH
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*
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* This file is part of the Genode OS framework, which is distributed
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* under the terms of the GNU Affero General Public License version 3.
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*/
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#ifndef _SRC__BOOTSTRAP__SPEC__RISCV_QEMU__BOARD_H_
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#define _SRC__BOOTSTRAP__SPEC__RISCV_QEMU__BOARD_H_
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#include <hw/spec/riscv/qemu_board.h>
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namespace Board { using namespace Hw::Riscv_board; }
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template <typename E, unsigned B, unsigned S>
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void Sv39::Level_x_translation_table<E, B, S>::_translation_added(addr_t, size_t)
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{ }
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#endif /* _SRC__BOOTSTRAP__SPEC__RISCV_QEMU__BOARD_H_ */
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@ -1,27 +0,0 @@
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/*
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* \brief Board spcecification
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* \author Sebastian Sumpf
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* \date 2015-06-02
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*/
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/*
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* Copyright (C) 2015-2017 Genode Labs GmbH
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*
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* This file is part of the Genode OS framework, which is distributed
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* under the terms of the GNU Affero General Public License version 3.
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*/
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#ifndef _CORE__SPEC__RISCV_QEMU__BOARD_H_
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#define _CORE__SPEC__RISCV_QEMU__BOARD_H_
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/* base-hw internal includes */
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#include <hw/spec/riscv/qemu_board.h>
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/* base-hw Core includes */
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#include <spec/riscv/pic.h>
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#include <spec/riscv/cpu.h>
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#include <spec/riscv/timer.h>
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namespace Board { using namespace Hw::Riscv_board; }
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#endif /* _CORE__SPEC__RISCV_QEMU__BOARD_H_ */
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/**
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* \brief Platform-level interrupt controller layout (PLIC)
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* \author Sebastian Sumpf
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* \date 2021-03-05
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*/
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/*
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* Copyright (C) 2021 Genode Labs GmbH
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*
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* This file is part of the Genode OS framework, which is distributed
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* under the terms of the GNU Affero General Public License version 3.
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*/
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#ifndef _CORE__SPEC__RISCV_QEMU__PLIC_H_
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#define _CORE__SPEC__RISCV_QEMU__PLIC_H_
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namespace Board { class Plic; }
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struct Board::Plic : Genode::Mmio
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{
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enum { NR_OF_IRQ = 32 };
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struct Enable : Register_array<0x80, 32, 32, 1> { };
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struct Id : Register<0x1ff004, 32> { };
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Plic(Genode::addr_t const base)
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:
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Mmio(base) { }
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void enable(unsigned value, unsigned irq)
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{
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write<Enable>(value, irq);
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}
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void el(unsigned, unsigned) { }
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};
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#endif /* _CORE__SPEC__RISCV_QEMU__PLIC_H_ */
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#include <base/stdint.h>
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#include <kernel/types.h>
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/* base-hw internal includes */
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#include <hw/spec/riscv/qemu_board.h>
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namespace Board { class Timer; }
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@ -413,7 +413,7 @@ namespace Hw {
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{
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enum {
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TABLE_LEVEL_X_SIZE_LOG2 = Sv39::SIZE_LOG2_4K,
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CORE_VM_AREA_SIZE = 128 * 1024 * 1024,
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CORE_VM_AREA_SIZE = 512 * 1024 * 1024,
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CORE_TRANS_TABLE_COUNT =
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_count(CORE_VM_AREA_SIZE, Sv39::SIZE_LOG2_1G) +
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_count(CORE_VM_AREA_SIZE, Sv39::SIZE_LOG2_2M),
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/*
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* \brief RISC-V Qemu specific board definitions
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* \author Sebastian Sumpf
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* \author Stefan Kalkowski
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* \date 2021-02-09
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*/
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/*
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* Copyright (C) 2021 Genode Labs GmbH
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*
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* This file is part of the Genode OS framework, which is distributed
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* under the terms of the GNU Affero General Public License version 3.
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*/
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#ifndef _SRC__INCLUDE__HW__SPEC__RISCV__QEMU_BOARD_H_
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#define _SRC__INCLUDE__HW__SPEC__RISCV__QEMU_BOARD_H_
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#include <hw/spec/riscv/boot_info.h>
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#include <hw/spec/riscv/page_table.h>
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#include <hw/spec/riscv/sbi.h>
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namespace Hw::Riscv_board {
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enum {
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RAM_BASE = 0x80020000,
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RAM_SIZE = 0x7fe0000,
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TIMER_HZ = 10000000,
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PLIC_BASE = 0xc002000,
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PLIC_SIZE = 0x200000,
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};
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enum { UART_BASE, UART_CLOCK };
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struct Serial : Hw::Riscv_uart
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{
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Serial(Genode::addr_t, Genode::size_t, unsigned) { }
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};
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}
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#endif /* _SRC__INCLUDE__HW__SPEC__RISCV__QEMU_BOARD_H_ */
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-m 128 -machine virt -cpu rv64,priv_spec=v1.10.0
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-bios default
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5
tool/builddir/build.conf/repos_riscv
Normal file
5
tool/builddir/build.conf/repos_riscv
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#
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# Board support for RISC-V Qemu / MiG-V
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#
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#REPOSITORIES += $(GENODE_DIR)/repos/riscv
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@ -91,7 +91,7 @@ BUILD_CONF_ARM_V7 := run_arm_v7 run_boot_dir repos repos_arm_v7
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BUILD_CONF(arm_v6) := $(BUILD_CONF_ARM_V6)
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BUILD_CONF(arm_v7a) := $(BUILD_CONF_ARM_V7)
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BUILD_CONF(arm_v8a) := run_arm_v8 run_boot_dir repos repos_arm_v8
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BUILD_CONF(riscv) := run_riscv run_boot_dir repos
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BUILD_CONF(riscv) := run_riscv run_boot_dir repos repos_riscv
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BUILD_CONF(x86_32) := run_x86_32 $(BUILD_CONF_X86)
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BUILD_CONF(x86_64) := run_x86_64 $(BUILD_CONF_X86)
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BUILD_CONF(linux) := run_kernel_linux repos
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