mirror of
https://github.com/genodelabs/genode.git
synced 2024-12-18 13:26:27 +00:00
parent
a07b5937d9
commit
75266e467d
@ -1 +1 @@
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4f4c05a80b5767a0132c333a352fada6ba8965a8
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f425c0058d023cabfa555a0605982e935c582902
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66
repos/ports/src/virtualbox6/patches/avx.patch
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66
repos/ports/src/virtualbox6/patches/avx.patch
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@ -0,0 +1,66 @@
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--- a/src/virtualbox6/src/VBox/VMM/VMMR3/CPUMR3CpuId.cpp
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+++ b/src/virtualbox6/src/VBox/VMM/VMMR3/CPUMR3CpuId.cpp
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@@ -2470,6 +2470,8 @@
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pCpum->GuestFeatures.cbMaxExtendedState),
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VERR_CPUM_IPE_1);
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pVCpu0->cpum.s.Guest.aoffXState[iComponent] = pSubLeaf->uEbx;
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+ /* store uEax to later on detect compact mode */
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+// pVCpu0->cpum.s.Guest.aoffXState[iComponent] = pSubLeaf->uEax;
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}
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/* Copy the CPU #0 data to the other CPUs. */
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@@ -3558,6 +3560,8 @@
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VERR_CPUM_IPE_2);
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continue;
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case 1:
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+ /* permit compact AVX mode, Intel: 13.2 ENUMERATION OF CPU SUPPORT FOR XSAVE INSTRUCTIONS AND XSAVE- SUPPORTED FEATURES */
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+// pCurLeaf->uEax &= 1 | 2;
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pCurLeaf->uEax &= 0;
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pCurLeaf->uEcx &= 0;
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pCurLeaf->uEdx &= 0;
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@@ -4285,7 +4289,8 @@
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rc = cpumR3CpuIdReadIsaExtCfgLegacy(pVM, pIsaExts, pCpumCfg, "SSE4.2", &pConfig->enmSse42, true);
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AssertLogRelRCReturn(rc, rc);
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- bool const fMayHaveXSave = fNestedPagingAndFullGuestExec
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+ bool const fEnforceHWusage = true;
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+ bool const fMayHaveXSave = fEnforceHWusage
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&& pVM->cpum.s.HostFeatures.fXSaveRstor
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&& pVM->cpum.s.HostFeatures.fOpSysXSaveRstor;
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uint64_t const fXStateHostMask = pVM->cpum.s.fXStateHostMask;
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@@ -4296,7 +4301,7 @@
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* unrestricted guest execution mode. Not possible to force this one without
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* host support at the moment.
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*/
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- rc = cpumR3CpuIdReadIsaExtCfgEx(pVM, pIsaExts, "XSAVE", &pConfig->enmXSave, fNestedPagingAndFullGuestExec,
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+ rc = cpumR3CpuIdReadIsaExtCfgEx(pVM, pIsaExts, "XSAVE", &pConfig->enmXSave, fEnforceHWusage,
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fMayHaveXSave /*fAllowed*/);
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AssertLogRelRCReturn(rc, rc);
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@@ -4305,7 +4310,7 @@
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* XSAVE is exposed too. For the time being the default is to only expose this
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* to VMs with nested paging and AMD-V or unrestricted guest execution mode.
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*/
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- rc = cpumR3CpuIdReadIsaExtCfgEx(pVM, pIsaExts, "AVX", &pConfig->enmAvx, fNestedPagingAndFullGuestExec,
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+ rc = cpumR3CpuIdReadIsaExtCfgEx(pVM, pIsaExts, "AVX", &pConfig->enmAvx, fEnforceHWusage,
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fMayHaveXSave && pConfig->enmXSave && (fXStateHostMask & XSAVE_C_YMM) /*fAllowed*/);
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AssertLogRelRCReturn(rc, rc);
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@@ -4314,7 +4319,7 @@
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* XSAVE is exposed too. For the time being the default is to only expose this
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* to VMs with nested paging and AMD-V or unrestricted guest execution mode.
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*/
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- rc = cpumR3CpuIdReadIsaExtCfgEx(pVM, pIsaExts, "AVX2", &pConfig->enmAvx2, fNestedPagingAndFullGuestExec /* temporarily */,
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+ rc = cpumR3CpuIdReadIsaExtCfgEx(pVM, pIsaExts, "AVX2", &pConfig->enmAvx2, fEnforceHWusage /* temporarily */,
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fMayHaveXSave && pConfig->enmXSave && (fXStateHostMask & XSAVE_C_YMM) /*fAllowed*/);
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AssertLogRelRCReturn(rc, rc);
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@@ -4425,7 +4430,7 @@
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* being the default is to only do this for VMs with nested paging and AMD-V or
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* unrestricted guest mode.
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*/
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- rc = cpumR3CpuIdReadIsaExtCfg(pVM, pIsaExts, "SSE4A", &pConfig->enmSse4A, fNestedPagingAndFullGuestExec);
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+ rc = cpumR3CpuIdReadIsaExtCfg(pVM, pIsaExts, "SSE4A", &pConfig->enmSse4A, fEnforceHWusage);
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AssertLogRelRCReturn(rc, rc);
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/** @cfgm{/CPUM/IsaExts/MISALNSSE, isaextcfg, depends}
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@ -14,3 +14,4 @@ pgmphys.patch
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sup_ioctl_query_func_size.patch
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disk_geometry.patch
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stack_size.patch
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avx.patch
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@ -265,12 +265,27 @@ template <typename VIRT> void Sup::Vcpu_impl<VIRT>::_transfer_state_to_vcpu(CPUM
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state.tpr_threshold.charge(pending_priority);
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}
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/* export FPU state */
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/* export FPU state - start */
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state.xcr0.charge(ctx.aXcr[0]);
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{
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::uint64_t ia32_xss = 0;
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auto const rc = CPUMQueryGuestMsr(&_vmcpu, 0xDA0 /* MSR_IA32_XSS */,
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&ia32_xss);
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if (rc == VINF_SUCCESS)
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state.xss.charge(ia32_xss);
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}
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_state->ref.fpu.charge([&](Vcpu_state::Fpu::State &fpu) {
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static_assert(sizeof(*ctx.pXStateR3) >= sizeof(fpu._buffer));
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::memcpy(fpu._buffer, ctx.pXStateR3, sizeof(X86FXSTATE));
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return sizeof(X86FXSTATE);
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unsigned fpu_size = min(_vm.cpum.s.HostFeatures.cbMaxExtendedState,
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sizeof(fpu._buffer));
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::memcpy(fpu._buffer, ctx.pXStateR3, fpu_size);
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return fpu_size;
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});
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/* export FPU state - end */
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{
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::uint64_t tsc_aux = 0;
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@ -413,13 +428,21 @@ template <typename VIRT> void Sup::Vcpu_impl<VIRT>::_transfer_state_to_vbox(CPUM
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APICSetTpr(pVCpu, tpr);
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/* import FPU state */
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/* import FPU state - start */
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_state->ref.fpu.with_state([&](Vcpu_state::Fpu::State const &fpu) {
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static_assert(sizeof(*ctx.pXStateR3) >= sizeof(fpu._buffer));
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::memcpy(ctx.pXStateR3, fpu._buffer, sizeof(X86FXSTATE));
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unsigned fpu_size = min(_vm.cpum.s.HostFeatures.cbMaxExtendedState,
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sizeof(fpu._buffer));
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::memcpy(ctx.pXStateR3, fpu._buffer, fpu_size);
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return true;
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});
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CPUMSetGuestMsr (pVCpu, 0xDA0 /* MSR_IA32_XSS */, state.xss.value());
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CPUMSetGuestXcr0(pVCpu, state.xcr0.value());
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/* import FPU state - end */
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/* do SVM/VMX-specific transfers */
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VIRT::transfer_state_to_vbox(state, _vmcpu, ctx);
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}
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@ -77,6 +77,7 @@ Genode::Vm_connection::Exit_config const Sup::Svm::exit_config { /* ... */ };
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| SVM_CTRL_INTERCEPT_WBINVD
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| SVM_CTRL_INTERCEPT_MONITOR
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| SVM_CTRL_INTERCEPT_RDTSCP
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| SVM_CTRL_INTERCEPT_XSETBV
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| SVM_CTRL_INTERCEPT_MWAIT;
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unsigned Sup::Svm::ctrl_primary()
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@ -81,6 +81,7 @@ unsigned Sup::Vmx::ctrl_secondary()
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| VMX_PROC_CTLS2_RDTSCP
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| VMX_PROC_CTLS2_EPT
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| VMX_PROC_CTLS2_INVPCID
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| VMX_PROC_CTLS2_XSAVES_XRSTORS
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;
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}
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