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ahci: remove Exynos5 support
Exynos5 support has ceased on Genode issue #3636
This commit is contained in:
Sebastian Sumpf
Norman Feske
parent
de24035066
commit
73f2c7043c
@ -1,400 +0,0 @@
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/*
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* \brief Driver for Exynos-5250 soc
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* \author Martin Stein
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* \author Sebastian Sumpf
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* \date 2015-05-04
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*/
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/*
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* Copyright (C) 2017 Genode Labs GmbH
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*
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* This file is part of the Genode OS framework, which is distributed
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* under the terms of the GNU Affero General Public License version 3.
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*/
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#include <drivers/defs/exynos5.h>
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#include <irq_session/connection.h>
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#include <regulator/consts.h>
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#include <regulator_session/connection.h>
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#include <ahci.h>
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using namespace Genode;
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/**
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* I2C master interface
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*/
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struct I2c_interface : Attached_mmio
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{
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enum { TX_DELAY_US = 1 };
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/********************************
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** MMIO structure description **
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********************************/
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struct Start_msg : Genode::Register<8>
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{
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struct Addr : Bitfield<1, 7> { };
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};
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struct Con : Register<0x0, 8>
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{
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struct Tx_prescaler : Bitfield<0, 4> { };
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struct Irq_pending : Bitfield<4, 1> { };
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struct Irq_en : Bitfield<5, 1> { };
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struct Clk_sel : Bitfield<6, 1> { };
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struct Ack_en : Bitfield<7, 1> { };
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};
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struct Stat : Register<0x4, 8>
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{
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struct Last_bit : Bitfield<0, 1> { };
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struct Arbitr : Bitfield<3, 1> { };
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struct Txrx_en : Bitfield<4, 1> { };
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struct Busy : Bitfield<5, 1> { };
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struct Mode : Bitfield<6, 2> { };
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};
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struct Add : Register<0x8, 8>
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{
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struct Slave_addr : Bitfield<0, 8> { };
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};
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struct Ds : Register<0xc, 8> { };
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struct Lc : Register<0x10, 8>
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{
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struct Sda_out_delay : Bitfield<0, 2> { };
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struct Filter_en : Bitfield<2, 1> { };
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};
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Mmio::Delayer &delayer;
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/* single-word message that starts a multi-word message transfer */
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Start_msg::access_t const start_msg;
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/**
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* Constructor
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*
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* \param base physical MMIO base
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* \param slave_addr ID of the targeted slave
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*/
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I2c_interface(Genode::Env &env,
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addr_t base, unsigned slave_addr, Mmio::Delayer &delayer)
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: Attached_mmio(env, base, 0x10000), delayer(delayer),
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start_msg(Start_msg::Addr::bits(slave_addr))
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{ }
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/**
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* Wether acknowledgment for last transaction can be received
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*/
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bool ack_received()
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{
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for (unsigned i = 0; i < 3; i++) {
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if (read<Con::Irq_pending>() && !read<Stat::Last_bit>()) return 1;
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delayer.usleep(TX_DELAY_US);
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}
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Genode::error("I2C ack not received");
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return 0;
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}
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/**
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* Wether arbitration errors occured during the last transaction
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*/
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bool arbitration_error()
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{
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if (read<Stat::Arbitr>()) {
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Genode::error("I2C arbitration failed");
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return 1;
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}
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return 0;
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}
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/**
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* Let I2C master send a message to I2C slave
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*
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* \param msg message base
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* \param msg_size message size
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*
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* \retval 0 call was successful
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* \retval <0 call failed, error code
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*/
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int send(uint8_t * msg, size_t msg_size)
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{
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/* initiate message transfer */
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try {
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wait_for(delayer, Stat::Busy::Equal(0));
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} catch (Polling_timeout) {
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Genode::error("I2C busy");
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return -1;
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}
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Stat::access_t stat = read<Stat>();
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Stat::Txrx_en::set(stat, 1);
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Stat::Mode::set(stat, 3);
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write<Stat>(stat);
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write<Ds>(start_msg);
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delayer.usleep(1000);
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write<Con::Tx_prescaler>(11);
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write<Stat::Busy>(1);
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/* transmit message payload */
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for (unsigned i = 0; i < msg_size; i++) {
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if (!ack_received()) return -1;
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write<Ds>(msg[i]);
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delayer.usleep(TX_DELAY_US);
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write<Con::Irq_pending>(0);
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if (arbitration_error()) return -1;
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}
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/* end message transfer */
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if (!ack_received()) return -1;
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write<Stat::Busy>(0);
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write<Con::Irq_en>(0);
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write<Con::Irq_pending>(0); /* FIXME fixup */
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if (arbitration_error()) return -1;
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try {
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wait_for(delayer, Stat::Busy::Equal(0));
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} catch (Polling_timeout) {
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Genode::error("I2C end transfer failed");
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return -1;
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}
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return 0;
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}
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};
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/**
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* I2C control interface of SATA PHY-layer controller
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*/
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struct I2c_sataphy : I2c_interface
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{
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enum { SLAVE_ADDR = 0x38 };
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/**
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* Constructor
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*/
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I2c_sataphy(Genode::Env &env, Mmio::Delayer &delayer)
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: I2c_interface(env, 0x121d0000, SLAVE_ADDR, delayer)
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{ }
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/**
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* Enable the 40-pin interface of the SATA PHY controller
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*
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* \retval 0 call was successful
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* \retval <0 call failed, error code
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*/
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int enable_40_pins()
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{
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/*
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* I2C message
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*
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* first byte: set address
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* second byte: set data
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*/
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static uint8_t msg[] = { 0x3a, 0x0b };
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enum { MSG_SIZE = sizeof(msg)/sizeof(msg[0]) };
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/* send messaage */
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if (send(msg, MSG_SIZE)) return -1;
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if (verbose) Genode::log("SATA PHY 40-pin interface enabled");
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return 0;
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}
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/**
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* Get I2C interface ready for transmissions
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*/
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void init()
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{
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write<Add::Slave_addr>(SLAVE_ADDR);
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Con::access_t con = read<Con>();
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Con::Irq_en::set(con, 1);
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Con::Ack_en::set(con, 1);
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Con::Clk_sel::set(con, 1);
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Con::Tx_prescaler::set(con, 9);
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write<Con>(con);
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Lc::access_t lc = 0;
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Lc::Sda_out_delay::set(lc, 3);
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Lc::Filter_en::set(lc, 1);
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write<Lc>(lc);
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}
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};
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/**
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* Classical control interface of SATA PHY-layer controller
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*/
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struct Sata_phy_ctrl : Attached_mmio
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{
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Mmio::Delayer &delayer;
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I2c_sataphy i2c_sataphy;
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/********************************
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** MMIO structure description **
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********************************/
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struct Reset : Register<0x4, 32>
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{
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struct Global : Bitfield<1, 1> { };
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struct Non_link : Bitfield<0, 8> { };
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struct Link : Bitfield<16, 4> { };
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};
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struct Mode0 : Register<0x10, 32>
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{
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struct P0_phy_spdmode : Bitfield<0, 2> { };
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};
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struct Ctrl0 : Register<0x14, 32>
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{
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struct P0_phy_calibrated : Bitfield<8, 1> { };
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struct P0_phy_calibrated_sel : Bitfield<9, 1> { };
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};
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struct Phctrlm : Register<0xe0, 32>
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{
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struct High_speed : Bitfield<0, 1> { };
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struct Ref_rate : Bitfield<1, 1> { };
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};
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struct Phstatm : Register<0xf0, 32>
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{
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struct Pll_locked : Bitfield<0, 1> { };
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};
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/**
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* Constructor
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*/
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Sata_phy_ctrl(Genode::Env &env, Mmio::Delayer &delayer)
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:
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Attached_mmio(env, 0x12170000, 0x10000), delayer(delayer),
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i2c_sataphy(env, delayer)
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{
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i2c_sataphy.init();
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}
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/**
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* Initialize parts of SATA PHY that are controlled classically
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*
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* \retval 0 call was successful
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* \retval <0 call failed, error code
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*/
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int init()
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{
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/* reset */
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write<Reset>(0);
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write<Reset::Non_link>(~0);
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write<Reset::Link>(~0);
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write<Reset::Global>(~0);
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/* set up SATA phy generation 3 (6 Gb/s) */
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Phctrlm::access_t phctrlm = read<Phctrlm>();
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Phctrlm::Ref_rate::set(phctrlm, 0);
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Phctrlm::High_speed::set(phctrlm, 1);
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write<Phctrlm>(phctrlm);
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Ctrl0::access_t ctrl0 = read<Ctrl0>();
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Ctrl0::P0_phy_calibrated::set(ctrl0, 1);
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Ctrl0::P0_phy_calibrated_sel::set(ctrl0, 1);
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write<Ctrl0>(ctrl0);
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write<Mode0::P0_phy_spdmode>(2);
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if (i2c_sataphy.enable_40_pins()) return -1;
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/* Release reset */
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write<Reset::Global>(0);
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write<Reset::Global>(1);
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/*
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* FIXME Linux reads this bit once only and continues
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* directly, also with zero. So if we get an error
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* at this point we should study the Linux behavior
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* in more depth.
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*/
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try {
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wait_for(delayer, Phstatm::Pll_locked::Equal(1));
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} catch (Polling_timeout) {
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Genode::error("PLL lock failed");
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return -1;
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}
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if (verbose)
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Genode::log("SATA PHY initialized");
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return 0;
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}
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};
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struct Exynos5_hba : Platform::Hba
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{
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Genode::Env &env;
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Irq_connection irq { env, Exynos5::SATA_IRQ };
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Regulator::Connection clock_src { env, Regulator::CLK_SATA };
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Regulator::Connection power_src { env, Regulator::PWR_SATA };
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Exynos5_hba(Genode::Env &env, Mmio::Delayer &delayer)
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: env(env)
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{
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clock_src.state(true);
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power_src.state(true);
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Sata_phy_ctrl phy(env, delayer);
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if (phy.init())
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throw Service_denied();
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/* additionally perform some generic initializations */
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::Hba hba(env, *this, delayer);
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::Hba::Cap::access_t cap = hba.read< ::Hba::Cap>();
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::Hba::Cap2::access_t cap2 = hba.read< ::Hba::Cap2>();
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/* reset */
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hba.write< ::Hba::Ghc::Hr>(1);
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try {
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hba.wait_for(::Hba::Attempts(1000), ::Hba::Microseconds(1000),
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hba.delayer(), ::Hba::Ghc::Hr::Equal(0));
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} catch (::Hba::Polling_timeout) {
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Genode::error("HBA reset failed");
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throw Service_denied();
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}
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hba.write< ::Hba::Cap>(cap);
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hba.write< ::Hba::Cap2>(cap2);
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/* for exynos set port 0 as implemented, usally set by BIOS */
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hba.write< ::Hba::Pi>(0x1);
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}
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/*******************
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** Hba interface **
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*******************/
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Genode::addr_t base() const override { return 0x122f0000; }
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Genode::size_t size() const override { return 0x10000; }
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void sigh_irq(Signal_context_capability sigh) override
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{
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irq.sigh(sigh);
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ack_irq();
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}
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void ack_irq() override { irq.ack_irq(); }
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Ram_dataspace_capability
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alloc_dma_buffer(size_t size) override
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{
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return env.ram().alloc(size, UNCACHED);
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}
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void free_dma_buffer(Ram_dataspace_capability ds) override
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{
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env.ram().free(ds);
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}
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};
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Platform::Hba &Platform::init(Genode::Env &env, Mmio::Delayer &delayer)
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{
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static Exynos5_hba h(env, delayer);
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return h;
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}
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@ -1,5 +0,0 @@
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TARGET = exynos5_ahci_drv
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REQUIRES = arm_v7
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INC_DIR = $(call select_from_repositories,include/spec/exynos5)
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include $(REP_DIR)/src/drivers/ahci/target.inc
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