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02209e5455
commit
70c57a3be3
@ -142,10 +142,17 @@ struct Pci::Config : Genode::Mmio
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bool prefetchable() {
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return Bar_32bit::Memory_prefetchable::get(_conf()); }
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Genode::size_t size()
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Genode::uint64_t size()
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{
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return 1 + (memory() ? ~Bar_32bit::Memory_base::masked(_conf())
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: ~Bar_32bit::Io_base::masked(_conf()));
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if (memory()) {
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Genode::uint64_t size = 1 + ~Bar_32bit::Memory_base::masked(_conf());
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if (bit64())
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size += ((Genode::uint64_t)~_get_and_set<Upper_bits>(read<Upper_bits>()))<<32;
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return size;
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}
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else
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return 1 + ~Bar_32bit::Io_base::masked(_conf());
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}
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Genode::uint64_t addr()
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@ -139,7 +139,7 @@ bus_t Main::parse_pci_function(Bdf bdf,
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}
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});
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cfg.for_each_bar([&] (uint64_t addr, size_t size,
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cfg.for_each_bar([&] (uint64_t addr, uint64_t size,
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unsigned bar, bool pf)
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{
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gen.node("io_mem", [&]
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@ -149,7 +149,7 @@ bus_t Main::parse_pci_function(Bdf bdf,
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gen.attribute("size", string(size));
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if (pf) gen.attribute("prefetchable", true);
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});
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}, [&] (uint64_t addr, size_t size, unsigned bar) {
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}, [&] (uint64_t addr, uint64_t size, unsigned bar) {
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gen.node("io_port_range", [&]
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{
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gen.attribute("pci_bar", bar);
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