nvme_drv: get I/O resources from platform API only

Do not use the I/O memory service from core directly,
but instead use the I/O resources the platform session
provides to the driver anyway.

Fix #4309
This commit is contained in:
Stefan Kalkowski 2021-11-02 11:54:31 +01:00 committed by Christian Helmuth
parent 43ef9b5a3a
commit 6d991313b1
3 changed files with 22 additions and 14 deletions

View File

@ -103,6 +103,17 @@ append config {
<config>
<policy label_prefix="block_tester" writeable="} [writeable] {"/>
</config>
<route>
<service name="Platform"><child name="platform_drv"/> </service>
<service name="Timer"> <child name="timer"/> </service>
<service name="RAM"> <parent/> </service>
<service name="CAP"> <parent/> </service>
<service name="CPU"> <parent/> </service>
<service name="ROM"> <parent/> </service>
<service name="PD"> <parent/> </service>
<service name="LOG"> <parent/> </service>
<service name="SIGNAL"> <parent/> </service>
</route>
</start>
<start name="block_tester" caps="200">

View File

@ -449,7 +449,8 @@ struct Nvme::Cq : Nvme::Queue
/*
* Controller
*/
struct Nvme::Controller : public Genode::Attached_mmio
struct Nvme::Controller : public Genode::Attached_dataspace,
public Genode::Mmio
{
/**********
** MMIO **
@ -1057,10 +1058,11 @@ struct Nvme::Controller : public Genode::Attached_mmio
* Constructor
*/
Controller(Genode::Env &env, Util::Dma_allocator &dma_alloc,
addr_t const base, size_t const size,
Genode::Io_mem_dataspace_capability ds_cap,
Mmio::Delayer &delayer)
:
Genode::Attached_mmio(env, base, size),
Genode::Attached_dataspace(env.rm(), ds_cap),
Genode::Mmio((addr_t)local_addr<void>()),
_env(env), _dma_alloc(dma_alloc), _delayer(delayer)
{ }
@ -1528,8 +1530,8 @@ class Nvme::Driver : Genode::Noncopyable
}
try {
_nvme_ctrlr.construct(_env, *_nvme_pci, _nvme_pci->base(),
_nvme_pci->size(), _delayer);
_nvme_ctrlr.construct(_env, *_nvme_pci, _nvme_pci->io_mem_ds(),
_delayer);
} catch (...) {
error("could not access NVMe controller MMIO");
throw;

View File

@ -45,10 +45,10 @@ struct Nvme::Pci : Platform::Connection,
enum Pci_config { IRQ = 0x3c, CMD = 0x4, CMD_IO = 0x1,
CMD_MEMORY = 0x2, CMD_MASTER = 0x4 };
Platform::Device::Resource _res { };
Platform::Device_capability _device_cap { };
Genode::Constructible<Platform::Device_client> _device { };
Io_mem_session_capability _io_mem_cap { };
Genode::Constructible<Genode::Irq_session_client> _irq { };
/**
@ -68,14 +68,13 @@ struct Nvme::Pci : Platform::Connection,
_device.construct(_device_cap);
_res = _device->resource(NVME_BASE_ID);
uint16_t cmd = _device->config_read(Pci_config::CMD, Platform::Device::ACCESS_16BIT);
cmd |= 0x2; /* respond to memory space accesses */
cmd |= 0x4; /* enable bus master */
_device->config_write(Pci_config::CMD, cmd, Platform::Device::ACCESS_16BIT);
_io_mem_cap = _device->io_mem(_device->phys_bar_to_virt(NVME_BASE_ID));
_irq.construct(_device->irq(0));
Genode::log("NVMe PCIe controller found (",
@ -86,12 +85,8 @@ struct Nvme::Pci : Platform::Connection,
/**
* Return base address of controller MMIO region
*/
addr_t base() const { return _res.base(); }
/**
* Return size of controller MMIO region
*/
size_t size() const { return _res.size(); }
Io_mem_dataspace_capability io_mem_ds() const {
return Io_mem_session_client(_io_mem_cap).dataspace(); }
/**
* Set interrupt signal handler