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gpu/intel: add gen9 w/a for submit batch

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issue #4254
This commit is contained in:
Alexander Boettcher 2021-08-04 10:41:58 +02:00 committed by Christian Helmuth
parent b2440a72c3
commit 6c7bcdd32e
1 changed files with 17 additions and 1 deletions
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18
repos/os/src/drivers/gpu/intel/main.cc
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@ -564,7 +564,8 @@ struct Igd::Device
Ring_buffer::Index advance = 0;
size_t const need = 4 /* batchbuffer cmd */ + 6 /* prolog */ + 16 /* epilog + w/a */;
size_t const need = 4 /* batchbuffer cmd */ + 6 /* prolog */ + 16 /* epilog + w/a */
+ (_device.generation().value == 9) ? 6 : 0;
if (!el.ring_avail(need)) { el.ring_reset_and_fill_zero(); }
/* save old tail */
@ -576,6 +577,21 @@ struct Igd::Device
* Pipeline synchronization
*/
/*
* on GEN9: emit empty pipe control before VF_CACHE_INVALIDATE
* - Linux 5.13 gen8_emit_flush_rcs()
*/
if (_device.generation().value == 9) {
enum { CMD_NUM = 6 };
Genode::uint32_t cmd[CMD_NUM] = {};
Igd::Pipe_control pc(CMD_NUM);
cmd[0] = pc.value;
for (size_t i = 0; i < CMD_NUM; i++) {
advance += el.ring_append(cmd[i]);
}
}
/* prolog */
if (1)
{