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@ -19,12 +19,15 @@
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** asm-generic/io.h **
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**********************/
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#define writeq(value, addr) (*(volatile uint64_t *)(addr) = (value))
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#define writel(value, addr) (*(volatile uint32_t *)(addr) = (value))
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#define writew(value, addr) (*(volatile uint16_t *)(addr) = (value))
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#define writeb(value, addr) (*(volatile uint8_t *)(addr) = (value))
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#define iowmb dma_wmb
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#define iormb dma_rmb
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#define readq(addr) (*(volatile uint64_t *)(addr))
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#define readl(addr) (*(volatile uint32_t *)(addr))
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#define readw(addr) (*(volatile uint16_t *)(addr))
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#define readb(addr) (*(volatile uint8_t *)(addr))
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#define writeq(value, addr) ({ iowmb(); *(volatile uint64_t *)(addr) = (value); })
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#define writel(value, addr) ({ iowmb(); *(volatile uint32_t *)(addr) = (value); })
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#define writew(value, addr) ({ iowmb(); *(volatile uint16_t *)(addr) = (value); })
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#define writeb(value, addr) ({ iowmb(); *(volatile uint8_t *)(addr) = (value); })
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#define readq(addr) ({ uint64_t const r = *(volatile uint64_t *)(addr); iormb(); r; })
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#define readl(addr) ({ uint32_t const r = *(volatile uint32_t *)(addr); iormb(); r; })
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#define readw(addr) ({ uint16_t const r = *(volatile uint16_t *)(addr); iormb(); r; })
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#define readb(addr) ({ uint8_t const r = *(volatile uint8_t *)(addr); iormb(); r; })
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@ -19,6 +19,9 @@
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#define rmb() mb()
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#define wmb() asm volatile ("dsb st": : :"memory")
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#define dma_wmb() __asm__ __volatile__ ("dmb oshst" : : : "memory")
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#define dma_rmb() __asm__ __volatile__ ("dmb oshld" : : : "memory")
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/*
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* This is the "safe" implementation as needed for a configuration
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* with bufferable DMA memory and SMP enabled.
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@ -19,6 +19,9 @@
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#define rmb() mb()
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#define wmb() asm volatile ("": : :"memory")
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#define dma_wmb() barrier()
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#define dma_rmb() barrier()
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/*
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* This is the "safe" implementation as needed for a configuration
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* with SMP enabled.
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@ -19,6 +19,9 @@
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#define rmb() mb()
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#define wmb() asm volatile ("dsb st": : :"memory")
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#define dma_wmb() barrier()
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#define dma_rmb() barrier()
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/*
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* This is the "safe" implementation as needed for a configuration
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* with bufferable DMA memory and SMP enabled.
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@ -7,6 +7,9 @@
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#define rmb() asm volatile ("lfence": : :"memory")
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#define wmb() asm volatile ("sfence": : :"memory")
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#define dma_wmb() barrier()
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#define dma_rmb() barrier()
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/*
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* This is the "safe" implementation as needed for a configuration
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* with SMP enabled.
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