ExternalVendorCode/genode
1
0
Fork 0
mirror of https://github.com/genodelabs/genode.git synced 2024-12-21 14:37:50 +00:00
Code Issues Actions Packages Projects Releases Wiki Activity

base-hw: optimize cache maintainance for ARMv8

Browse Source 
* Remove the data-synchronization barrier from the inner-loop
* Instead add a system-wide barrier at the end of the operation

Fix #4269
This commit is contained in:
Stefan Kalkowski 2021-09-23 16:34:23 +02:00 committed by Norman Feske
parent 9542bcf88c
commit 6789b86871
1 changed files with 8 additions and 8 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

16
repos/base-hw/src/core/spec/arm_v8/cpu.cc
View File

@ -121,12 +121,12 @@ void Genode::Cpu::cache_clean_invalidate_data_region(addr_t const base,
Genode::memory_barrier();
auto lambda = [] (addr_t const base) {
asm volatile("dc civac, %0" :: "r" (base));
asm volatile("dsb ish");
asm volatile("isb");
};
asm volatile("dc civac, %0" :: "r" (base)); };
cache_maintainance(base, size, lambda);
asm volatile("dsb sy");
asm volatile("isb");
}
@ -136,12 +136,12 @@ void Genode::Cpu::cache_invalidate_data_region(addr_t const base,
Genode::memory_barrier();
auto lambda = [] (addr_t const base) {
asm volatile("dc ivac, %0" :: "r" (base));
asm volatile("dsb ish");
asm volatile("isb");
};
asm volatile("dc ivac, %0" :: "r" (base)); };
cache_maintainance(base, size, lambda);
asm volatile("dsb sy");
asm volatile("isb");
}