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base_hw & omap4: Timer driver.
Fix bug regarding idle thread in thread scheduling in 'base-hw/src/core/kernel.cc'. Fix regarding signal submit in signal framework in 'base-hw/src/core/kernel.cc'.
This commit is contained in:
Martin Stein
Norman Feske
parent
31d57a6257
commit
612735732a
@ -895,7 +895,7 @@ namespace Kernel
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/* update current entry */
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ENTRY_T * e = _entries.head();
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if (!e) {
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t = _idle->Entry::_time;
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t = _lap_time;
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return _idle;
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}
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e->Entry::_consume(t);
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@ -1422,7 +1422,7 @@ namespace Kernel
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void add_pending_context(Signal_context * const c)
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{
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assert(c->_receiver == this);
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_pending_contexts.enqueue(c);
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if(!c->is_enqueued()) _pending_contexts.enqueue(c);
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_listen();
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}
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};
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@ -47,7 +47,9 @@ namespace Genode
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EMIF1_EMIF2_CS0_SDRAM_BASE = 0x80000000,
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EMIF1_EMIF2_CS0_SDRAM_SIZE = 0x40000000,
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/* misc */
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SECURITY_EXTENSION = 0,
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SYS_CLK = 38400000,
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};
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};
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}
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@ -5,12 +5,13 @@
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#
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# denote wich specs are also fullfilled by this spec
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SPECS += cortex_a9 tl16c750 omap44xx
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SPECS += cortex_a9 tl16c750 omap4 platform_panda
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# add repository relative include paths
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REP_INC_DIR += include/platform/panda_a2
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# include implied specs
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include $(call select_from_repositories,mk/spec-platform_panda.mk)
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include $(call select_from_repositories,mk/spec-cortex_a9.mk)
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include $(call select_from_repositories,mk/spec-tl16c750.mk)
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@ -169,8 +169,8 @@ namespace Genode
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/**
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* Translate microseconds to a native timer value
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*/
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static unsigned long us_to_tics(unsigned long const tics) {
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return tics / TICS_PER_US; }
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static unsigned long us_to_tics(unsigned long const us) {
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return us * TICS_PER_US; }
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/**
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* Translate native timer value to microseconds
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270
os/src/drivers/timer/hw/omap4/platform_timer_base.h
Normal file
270
os/src/drivers/timer/hw/omap4/platform_timer_base.h
Normal file
@ -0,0 +1,270 @@
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/*
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* \brief Basic driver behind platform timer
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* \author Martin Stein
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* \date 2012-05-03
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*/
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/*
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* Copyright (C) 2012 Genode Labs GmbH
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*
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* This file is part of the Genode OS framework, which is distributed
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* under the terms of the GNU General Public License version 2.
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*/
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#ifndef _HW__OMAP4__PLATFORM_TIMER_BASE_H_
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#define _HW__OMAP4__PLATFORM_TIMER_BASE_H_
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/* Genode includes */
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#include <io_mem_session/connection.h>
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#include <util/mmio.h>
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#include <irq_session/connection.h>
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#include <drivers/board.h>
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namespace Genode
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{
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/**
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* Omap4 general purpose timer 3 through 9 and 11
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*/
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class Omap4_gp_timer_1 : public Mmio
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{
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/**
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* Timer tics per microsecond
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*/
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static float tics_per_us() {
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return (float)Board::SYS_CLK / 1000000; }
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/**
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* Microsecodns per timer tic
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*/
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static float us_per_tic() { return 1 / tics_per_us(); }
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/**
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* L4 interface control
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*/
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struct Tiocp_cfg : Register<0x10, 32>
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{
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struct Softreset : Bitfield<0, 1> { }; /* SW reset active */
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struct Idlemode : Bitfield<2, 2> /* action on IDLE request */
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{
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enum { FORCE_IDLE = 0 };
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};
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};
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/**
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* Timer wake-up enable register
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*/
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struct Twer : Register<0x20, 32>
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{
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struct Mat_wup_ena : Bitfield<0, 1> { }; /* wakeup on match */
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struct Ovf_wup_ena : Bitfield<1, 1> { }; /* wakeup on overflow */
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struct Tcar_wup_ena : Bitfield<2, 1> { }; /* wakeup on capture */
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/**
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* Timer initialization value
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*/
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static access_t init_timer()
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{
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return Mat_wup_ena::bits(0) |
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Ovf_wup_ena::bits(0) |
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Tcar_wup_ena::bits(0);
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}
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};
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/**
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* Timer synchronous interface control register
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*/
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struct Tsicr : Register<0x54, 32>
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{
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struct Posted : Bitfield<2, 1> { }; /* enable posted mode */
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};
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/**
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* Control timer-functionality dependent features
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*/
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struct Tclr : Register<0x38, 32>
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{
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struct St : Bitfield<0, 1> { }; /* start/stop timer */
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struct Ar : Bitfield<1, 1> { }; /* enable eutoreload */
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struct Pre : Bitfield<5, 1> { }; /* enable prescaler */
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/**
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* Run-and-wrap configuration
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*/
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static access_t init_run_and_wrap()
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{
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return St::bits(0) |
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Ar::bits(1) |
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Pre::bits(0);
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}
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};
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/**
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* Set IRQ enables
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*/
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struct Irqenable_set : Register<0x2c, 32>
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{
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struct Ovf_en_flag : Bitfield<1, 1> { }; /* enable overflow IRQ */
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};
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/**
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* IRQ status
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*/
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struct Irqstatus : Register<0x28, 32>
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{
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struct Ovf_it_flag : Bitfield<1, 1> { }; /* clear overflow IRQ */
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};
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/**
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* Timer counter register
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*/
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struct Tcrr : Register<0x3c, 32>
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{
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/**
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* maximum counter value
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*/
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static access_t max_value() { return ~0; }
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};
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/**
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* Timer load value register
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*/
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struct Tldr : Register<0x40, 32> { };
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/**
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* Freeze timer counter
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*/
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void _freeze() { write<Tclr::St>(0); }
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/**
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* Unfreeze timer counter
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*/
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void _unfreeze() { write<Tclr::St>(1); }
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/**
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* Get remaining counting amount
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*/
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unsigned long _value() { return max_value() - read<Tcrr>(); }
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/**
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* Apply counting amount
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*/
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void _value(unsigned long const v) { write<Tcrr>(max_value() - v); }
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public:
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/**
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* Constructor
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*
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* \param base MMIO base
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*/
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Omap4_gp_timer_1(addr_t const base) : Mmio(base)
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{
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_freeze();
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/* do a software reset */
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write<Tiocp_cfg::Softreset>(1);
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while (read<Tiocp_cfg::Softreset>()) ;
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/* configure Idle mode */
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write<Tiocp_cfg::Idlemode>(Tiocp_cfg::Idlemode::FORCE_IDLE);
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/* enable wake-up interrupt events */
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write<Twer>(Twer::init_timer());
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/* select posted mode */
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write<Tsicr::Posted>(0);
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}
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/**
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* Count down 'value', raise IRQ output, wrap counter and continue
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*/
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void run_and_wrap(unsigned long value)
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{
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enum { MIN_VALUE = 1 };
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/* stop timer */
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_freeze();
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clear_interrupt();
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value = value ? value : MIN_VALUE;
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/* configure for a run and wrap */
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write<Tclr>(Tclr::init_run_and_wrap());
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write<Irqenable_set::Ovf_en_flag>(1);
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/* install value */
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_value(value);
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write<Tldr>(0);
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/* start timer */
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_unfreeze();
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}
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/**
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* Clear interrupt output
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*/
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void clear_interrupt() {
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write<Irqstatus::Ovf_it_flag>(1); }
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/**
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* Maximum timeout value
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*/
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unsigned long max_value() { return Tcrr::max_value(); }
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/**
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* Translate timer tics to microseconds
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*/
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unsigned long tics_to_us(unsigned long const tics)
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{
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float const us = tics * us_per_tic();
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return (unsigned long)us;
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}
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/**
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* Translate microseconds to timer tics
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*/
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unsigned long us_to_tics(unsigned long const us)
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{
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float const tics = us * tics_per_us();
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return (unsigned long)tics;
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}
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/**
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* Sample the timer counter and according wrapped status
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*/
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unsigned long value(bool & wrapped)
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{
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Tcrr::access_t const v = _value();
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wrapped = (bool)read<Irqstatus::Ovf_it_flag>();
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return wrapped ? _value() : v;
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}
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};
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}
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/**
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* Basic driver behind platform timer
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*/
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class Platform_timer_base : public Genode::Io_mem_connection,
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public Genode::Omap4_gp_timer_1
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{
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/* FIXME these should be located in a omap4-defs file */
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enum {
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GP_TIMER_3_IRQ = 71,
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GP_TIMER_3_MMIO_BASE = 0x48034000,
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GP_TIMER_3_MMIO_SIZE = 0x00001000,
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};
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public:
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enum { IRQ = GP_TIMER_3_IRQ };
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/**
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* Constructor
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*/
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Platform_timer_base() :
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Io_mem_connection(GP_TIMER_3_MMIO_BASE, GP_TIMER_3_MMIO_SIZE),
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Genode::Omap4_gp_timer_1((Genode::addr_t)Genode::env()->rm_session()->attach(dataspace()))
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{ }
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};
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#endif /* _HW__OMAP4__PLATFORM_TIMER_BASE_H_ */
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23
os/src/drivers/timer/hw/omap4/target.mk
Executable file
23
os/src/drivers/timer/hw/omap4/target.mk
Executable file
@ -0,0 +1,23 @@
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#
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# \brief Timer session server
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# \author Martin Stein
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# \date 2012-05-03
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#
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# Set program name
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TARGET = timer
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# Add C++ sources
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SRC_CC += main.cc
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# Skip build if required specs not fullfilled
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REQUIRES += hw omap4
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# Add libraries
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LIBS += cxx server env alarm
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# Add include paths
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INC_DIR += $(PRG_DIR) $(PRG_DIR)/../ $(PRG_DIR)/../../nova/
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# Declare source paths
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vpath main.cc $(PRG_DIR)/../..
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