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hw_x86_64: read number of I/O redirection table entries from IOAPIC
Fixes #2475
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@ -170,6 +170,9 @@ Irte::access_t Ioapic::_create_irt_entry(unsigned const irq)
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Ioapic::Ioapic() : Mmio(Platform::mmio_to_virt(Hw::Cpu_memory_map::MMIO_IOAPIC_BASE))
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{
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write<Ioregsel>(IOAPICVER);
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_irte_count = read<Iowin::Maximum_redirection_entry>() + 1;
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for (unsigned i = 0; i < IRQ_COUNT; i++)
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{
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/* set legacy/ISA IRQs to edge, high */
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@ -182,7 +185,7 @@ Ioapic::Ioapic() : Mmio(Platform::mmio_to_virt(Hw::Cpu_memory_map::MMIO_IOAPIC_B
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}
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/* remap all IRQs managed by I/O APIC */
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if (i < IRTE_COUNT) {
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if (i < _irte_count) {
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Irte::access_t irte = _create_irt_entry(i);
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write<Ioregsel>(IOREDTBL + 2 * i + 1);
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write<Iowin>(irte >> Iowin::ACCESS_WIDTH);
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@ -198,7 +201,7 @@ void Ioapic::toggle_mask(unsigned const vector, bool const set)
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/*
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* Ignore toggle requests for vectors not handled by the I/O APIC.
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*/
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if (vector < REMAP_BASE || vector >= REMAP_BASE + IRTE_COUNT) {
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if (vector < REMAP_BASE || vector >= REMAP_BASE + _irte_count) {
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return;
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}
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@ -53,12 +53,10 @@ class Genode::Ioapic : public Mmio
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enum { REMAP_BASE = Board::VECTOR_REMAP_BASE };
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uint8_t _irt_count;
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/* Number of Redirection Table entries */
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unsigned _irte_count;
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enum {
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/* Number of Redirection Table entries */
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IRTE_COUNT = 24,
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/* Register selectors */
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IOAPICVER = 0x01,
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IOREDTBL = 0x10,
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@ -130,7 +128,10 @@ class Genode::Ioapic : public Mmio
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*/
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struct Ioregsel : Register<0x00, 32> { };
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struct Iowin : Register<0x10, 32> { };
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struct Iowin : Register<0x10, 32>
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{
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struct Maximum_redirection_entry : Bitfield<16, 8> { };
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};
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};
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class Genode::Pic : public Mmio
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