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Remove i.MX6 platforms from base repositories

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Fix genodelabs/genode#4941
This commit is contained in:
Stefan Kalkowski 2023-06-28 16:18:35 +02:00 committed by Norman Feske
parent edcd44d9a7
commit 5e7e6514be
33 changed files with 8 additions and 1373 deletions
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1
repos/base-hw/board/imx6q_sabrelite/arch
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arm_v7a

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repos/base-hw/board/imx6q_sabrelite/image_link_address
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0x10001000

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repos/base-hw/board/nit6_solox/arch
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arm_v7a

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repos/base-hw/board/nit6_solox/image_link_address
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0x88000000

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repos/base-hw/board/wand_quad/arch
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arm_v7a

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repos/base-hw/board/wand_quad/image_link_address
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0x10001000

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repos/base-hw/lib/mk/spec/arm_v7/bootstrap-hw-imx6q_sabrelite.mk
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REP_INC_DIR += src/bootstrap/board/imx6q_sabrelite
SRC_CC += bootstrap/spec/arm/cpu.cc
SRC_CC += bootstrap/spec/arm/cortex_a9_mmu.cc
SRC_CC += bootstrap/spec/arm/gicv2.cc
SRC_CC += bootstrap/spec/arm/imx6_platform.cc
include $(call select_from_repositories,lib/mk/spec/arm_v7/bootstrap-hw.inc)

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repos/base-hw/lib/mk/spec/arm_v7/bootstrap-hw-nit6_solox.mk
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REP_INC_DIR += src/bootstrap/board/nit6_solox
SRC_CC += bootstrap/spec/arm/cpu.cc
SRC_CC += bootstrap/spec/arm/cortex_a9_mmu.cc
SRC_CC += bootstrap/spec/arm/gicv2.cc
SRC_CC += bootstrap/spec/arm/imx6_platform.cc
include $(call select_from_repositories,lib/mk/spec/arm_v7/bootstrap-hw.inc)

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repos/base-hw/lib/mk/spec/arm_v7/bootstrap-hw-wand_quad.mk
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REP_INC_DIR += src/bootstrap/board/wand_quad
SRC_CC += bootstrap/spec/arm/cpu.cc
SRC_CC += bootstrap/spec/arm/cortex_a9_mmu.cc
SRC_CC += bootstrap/spec/arm/gicv2.cc
SRC_CC += bootstrap/spec/arm/imx6_platform.cc
include $(call select_from_repositories,lib/mk/spec/arm_v7/bootstrap-hw.inc)

16
repos/base-hw/lib/mk/spec/arm_v7/core-hw-imx6q_sabrelite.mk
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#
# \brief Build config for Genodes core process
# \author Stefan Kalkowski
# \author Josef Söntgen
# \author Martin Stein
# \date 2014-02-25
#
# add include paths
REP_INC_DIR += src/core/board/imx6q_sabrelite
# add C++ sources
SRC_CC += platform_services.cc
# include less specific configuration
include $(call select_from_repositories,lib/mk/spec/cortex_a9/core-hw.inc)

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repos/base-hw/lib/mk/spec/arm_v7/core-hw-nit6_solox.mk
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#
# \brief Build config for Genodes core process
# \author Stefan Kalkowski
# \author Josef Söntgen
# \author Martin Stein
# \date 2014-02-25
#
# add include paths
REP_INC_DIR += src/core/board/nit6_solox
# add C++ sources
SRC_CC += platform_services.cc
# include less specific configuration
include $(call select_from_repositories,lib/mk/spec/cortex_a9/core-hw.inc)

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repos/base-hw/lib/mk/spec/arm_v7/core-hw-wand_quad.mk
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#
# \brief Build config for Genodes core process
# \author Stefan Kalkowski
# \author Josef Söntgen
# \author Martin Stein
# \date 2014-02-25
#
# add include paths
REP_INC_DIR += src/core/board/wand_quad
# add C++ sources
SRC_CC += platform_services.cc
# include less specific configuration
include $(call select_from_repositories,lib/mk/spec/cortex_a9/core-hw.inc)

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repos/base-hw/recipes/src/base-hw-imx6q_sabrelite/content.mk
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include $(GENODE_DIR)/repos/base-hw/recipes/src/base-hw_content.inc

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repos/base-hw/recipes/src/base-hw-imx6q_sabrelite/hash
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2023-06-15 876e53e4d77920fe345b07bc623bf4d8bc9c3343

2
repos/base-hw/recipes/src/base-hw-imx6q_sabrelite/used_apis
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base-hw
base

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repos/base-hw/recipes/src/base-hw-nit6_solox/content.mk
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include $(GENODE_DIR)/repos/base-hw/recipes/src/base-hw_content.inc

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repos/base-hw/recipes/src/base-hw-nit6_solox/hash
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2023-06-15 fe7671e108c407f96c1c8319d93d09b94838c5b0

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repos/base-hw/recipes/src/base-hw-nit6_solox/used_apis
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base-hw
base

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repos/base-hw/src/bootstrap/board/imx6q_sabrelite/board.h
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/*
* \brief i.MX6Quad Sabrelite specific board definitions
* \author Stefan Kalkowski
* \date 2019-01-05
*/
/*
* Copyright (C) 2019 Genode Labs GmbH
*
* This file is part of the Genode OS framework, which is distributed
* under the terms of the GNU Affero General Public License version 3.
*/
#ifndef _SRC__BOOTSTRAP__SPEC__IMX6Q_SABRELITE__BOARD_H_
#define _SRC__BOOTSTRAP__SPEC__IMX6Q_SABRELITE__BOARD_H_
#include <hw/spec/arm/imx6q_sabrelite_board.h>
#include <spec/arm/cortex_a9_actlr.h>
#include <spec/arm/cortex_a9_page_table.h>
#include <spec/arm/cpu.h>
#include <hw/spec/arm/gicv2.h>
namespace Board {
using namespace Hw::Imx6q_sabrelite_board;
using Pic = Hw::Gicv2;
struct L2_cache;
static constexpr bool NON_SECURE = false;
static volatile unsigned long initial_values[][2] {
// (IOMUX Controller)
{ 0x20e0004, 0x48613005 },
{ 0x20e0008, 0x0 },
{ 0x20e000c, 0x1e00040 },
{ 0x20e0020, 0xfffd4000 },
{ 0x20e0030, 0xf004490 },
{ 0x20e0034, 0x593e4a4 },
{ 0x20e004c, 0x3 },
{ 0x20e0050, 0x3 },
{ 0x20e0054, 0x3 },
{ 0x20e015c, 0x0 },
{ 0x20e0160, 0x0 },
{ 0x20e0164, 0x0 },
{ 0x20e0168, 0x0 },
{ 0x20e0170, 0x0 },
{ 0x20e0174, 0x0 },
{ 0x20e0178, 0x0 },
{ 0x20e017c, 0x0 },
{ 0x20e0180, 0x0 },
{ 0x20e0184, 0x0 },
{ 0x20e0188, 0x0 },
{ 0x20e018c, 0x0 },
{ 0x20e0190, 0x0 },
{ 0x20e0194, 0x0 },
{ 0x20e0198, 0x0 },
{ 0x20e019c, 0x0 },
{ 0x20e01a0, 0x0 },
{ 0x20e01a4, 0x0 },
{ 0x20e01a8, 0x0 },
{ 0x20e01ac, 0x0 },
{ 0x20e01b0, 0x0 },
{ 0x20e01b4, 0x0 },
{ 0x20e01b8, 0x0 },
{ 0x20e01bc, 0x0 },
{ 0x20e01c0, 0x0 },
{ 0x20e01c4, 0x0 },
{ 0x20e01c8, 0x0 },
{ 0x20e01cc, 0x0 },
{ 0x20e0208, 0x2 },
{ 0x20e020c, 0x2 },
{ 0x20e0218, 0x2 },
{ 0x20e0220, 0x0 },
{ 0x20e0224, 0x3 },
{ 0x20e0230, 0x11 },
{ 0x20e02b8, 0x0 },
{ 0x20e02f4, 0x0 },
{ 0x20e033c, 0x2 },
{ 0x20e0344, 0x3 },
{ 0x20e0348, 0x2 },
{ 0x20e035c, 0x3 },
{ 0x20e0360, 0x130b0 },
{ 0x20e0364, 0x110b0 },
{ 0x20e0368, 0x130b0 },
{ 0x20e036c, 0x10030 },
{ 0x20e0370, 0x10030 },
{ 0x20e0374, 0x10030 },
{ 0x20e0378, 0x10030 },
{ 0x20e037c, 0x10030 },
{ 0x20e0388, 0x10030 },
{ 0x20e03b0, 0xb1 },
{ 0x20e03bc, 0xb0 },
{ 0x20e03c0, 0xb0 },
{ 0x20e0470, 0x10 },
{ 0x20e0474, 0x10 },
{ 0x20e0478, 0x10 },
{ 0x20e047c, 0x10 },
{ 0x20e0484, 0x10 },
{ 0x20e0488, 0x10 },
{ 0x20e048c, 0x10 },
{ 0x20e0490, 0x10 },
{ 0x20e0494, 0x10 },
{ 0x20e0498, 0x10 },
{ 0x20e049c, 0x10 },
{ 0x20e04a0, 0x10 },
{ 0x20e04a4, 0x10 },
{ 0x20e04a8, 0x10 },
{ 0x20e04ac, 0x10 },
{ 0x20e04b0, 0x10 },
{ 0x20e04b4, 0x10 },
{ 0x20e04b8, 0x10 },
{ 0x20e04bc, 0x10 },
{ 0x20e04c0, 0x10 },
{ 0x20e04c4, 0x10 },
{ 0x20e04c8, 0x10 },
{ 0x20e04cc, 0x10 },
{ 0x20e04d0, 0x10 },
{ 0x20e04d4, 0x10 },
{ 0x20e04d8, 0x10 },
{ 0x20e04dc, 0x10 },
{ 0x20e04e0, 0x10 },
{ 0x20e04e4, 0x100b0 },
{ 0x20e04e8, 0x100b0 },
{ 0x20e0508, 0x100b0 },
{ 0x20e05f0, 0x30b0 },
{ 0x20e05f4, 0x17059 },
{ 0x20e0600, 0xb1 },
{ 0x20e061c, 0x30b0 },
{ 0x20e069c, 0x1f0b0 },
{ 0x20e06a4, 0x10059 },
{ 0x20e06e0, 0x10059 },
{ 0x20e0724, 0x1b0b1 },
{ 0x20e072c, 0x1b0b1 },
{ 0x20e0730, 0x1b0b1 },
{ 0x20e0744, 0x130b0 },
{ 0x20e07c4, 0x1 },
{ 0x20e0944, 0x1 },
// (Global Power Controller)
{ 0x20dc008, 0x70f7f01b },
{ 0x20dc00c, 0xff79b60f },
{ 0x20dc010, 0xfffe0003 },
{ 0x20dc014, 0xfef7f9ff },
// (Power Management Unit)
{ 0x20c8140, 0x4c0013 },
{ 0x20c8150, 0x4010088 },
{ 0x20c8160, 0x8000040b },
{ 0x20c8170, 0xff672f67 },
// (Clock Controller Module)
{ 0x20c4018, 0x10204 },
{ 0x20c402c, 0x7348c1 },
{ 0x20c4030, 0x33e71f92 },
{ 0x20c4034, 0x12088 },
{ 0x20c4038, 0x12090 },
{ 0x20c4054, 0x78 },
{ 0x20c4060, 0x10e0101 },
{ 0x20c4064, 0x2fe62 },
{ 0x20c4068, 0xc03f0f },
{ 0x20c406c, 0x30fc00 },
{ 0x20c4070, 0x3ff0033 },
{ 0x20c4074, 0x3f3300c3 },
{ 0x20c4078, 0xc303 },
{ 0x20c4080, 0xf03 },
{ 0x20c8010, 0x80003040 },
{ 0x20c8070, 0x1006 },
{ 0x20c80a0, 0x1028 },
{ 0x20c80b0, 0x0 },
{ 0x20c80c0, 0xf4240 },
{ 0x20c80e0, 0x80182001 },
{ 0x20c80f0, 0xd3d150cc },
{ 0x20c8100, 0x5018d0db }
};
}
struct Board::L2_cache : Hw::Pl310
{
L2_cache(Genode::addr_t mmio) : Hw::Pl310(mmio)
{
Aux::access_t aux = 0;
Aux::Full_line_of_zero::set(aux, true);
Aux::Associativity::set(aux, Aux::Associativity::WAY_16);
Aux::Way_size::set(aux, Aux::Way_size::KB_64);
Aux::Share_override::set(aux, true);
Aux::Replacement_policy::set(aux, Aux::Replacement_policy::PRAND);
Aux::Ns_lockdown::set(aux, true);
Aux::Data_prefetch::set(aux, true);
Aux::Inst_prefetch::set(aux, true);
Aux::Early_bresp::set(aux, true);
write<Aux>(aux);
Tag_ram::access_t tag_ram = 0;
Tag_ram::Setup_latency::set(tag_ram, 2);
Tag_ram::Read_latency::set(tag_ram, 3);
Tag_ram::Write_latency::set(tag_ram, 1);
write<Tag_ram>(tag_ram);
Data_ram::access_t data_ram = 0;
Data_ram::Setup_latency::set(data_ram, 2);
Data_ram::Read_latency::set(data_ram, 3);
Data_ram::Write_latency::set(data_ram, 1);
write<Data_ram>(data_ram);
Prefetch_ctrl::access_t prefetch = 0;
Prefetch_ctrl::Data_prefetch::set(prefetch, 1);
Prefetch_ctrl::Inst_prefetch::set(prefetch, 1);
write<Prefetch_ctrl>(prefetch | 0xF);
}
using Hw::Pl310::invalidate;
void enable()
{
Pl310::mask_interrupts();
write<Control::Enable>(1);
}
void disable() {
write<Control::Enable>(0);
}
};
#endif /* _SRC__BOOTSTRAP__SPEC__IMX6Q_SABRELITE__BOARD_H_ */

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repos/base-hw/src/bootstrap/board/nit6_solox/board.h
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/*
* \brief Nit6 SOLOX specific board definitions
* \author Stefan Kalkowski
* \date 2017-10-18
*/
/*
* Copyright (C) 2017 Genode Labs GmbH
*
* This file is part of the Genode OS framework, which is distributed
* under the terms of the GNU Affero General Public License version 3.
*/
#ifndef _SRC__BOOTSTRAP__SPEC__NIT6_SOLOX__BOARD_H_
#define _SRC__BOOTSTRAP__SPEC__NIT6_SOLOX__BOARD_H_
#include <hw/spec/arm/nit6_solox_board.h>
#include <spec/arm/cortex_a9_actlr.h>
#include <spec/arm/cortex_a9_page_table.h>
#include <spec/arm/cpu.h>
#include <hw/spec/arm/gicv2.h>
namespace Board {
using namespace Hw::Nit6_solox_board;
using Pic = Hw::Gicv2;
struct L2_cache;
static constexpr bool NON_SECURE = false;
static volatile unsigned long initial_values[][2] {
// (IOMUX Controller)
{ 0x20E006C, 0x0},
{ 0x20E00CC, 0x10},
{ 0x20E00D0, 0x10},
{ 0x20E00D4, 0x10},
{ 0x20E00D8, 0x10},
{ 0x20E00DC, 0x10},
{ 0x20E00E0, 0x10},
{ 0x20E00E4, 0x10},
{ 0x20E00E8, 0x10},
{ 0x20E00EC, 0x10},
{ 0x20E00F0, 0x10},
{ 0x20E00F4, 0x10},
{ 0x20E00F8, 0x10},
{ 0x20E00FC, 0x10},
{ 0x20E0100, 0x10},
{ 0x20E0104, 0x10},
{ 0x20E0108, 0x10},
{ 0x20E010C, 0x10},
{ 0x20E0110, 0x10},
{ 0x20E0114, 0x10},
{ 0x20E0118, 0x10},
{ 0x20E011C, 0x10},
{ 0x20E0120, 0x10},
{ 0x20E0124, 0x10},
{ 0x20E0128, 0x10},
{ 0x20E012C, 0x10},
{ 0x20E0130, 0x10},
{ 0x20E0134, 0x10},
{ 0x20E0138, 0x15},
{ 0x20E013C, 0x10},
{ 0x20E0150, 0x5},
{ 0x20E0154, 0x5},
{ 0x20E0158, 0x5},
{ 0x20E0224, 0x5},
{ 0x20E0268, 0x5},
{ 0x20E026C, 0x5},
{ 0x20E0270, 0x3},
{ 0x20E0274, 0x3},
{ 0x20E035C, 0x1b8b1},
{ 0x20E0360, 0x1b8b1},
{ 0x20E0364, 0x1b8b1},
{ 0x20E0368, 0x1b8b1},
{ 0x20E0380, 0x1b0b0},
{ 0x20E0384, 0x170b1},
{ 0x20E0390, 0x110b0},
{ 0x20E0394, 0x110b0},
{ 0x20E0398, 0x110b0},
{ 0x20E039C, 0x110b0},
{ 0x20E03A0, 0x110b0},
{ 0x20E03A4, 0x110b0},
{ 0x20E03A8, 0x110b0},
{ 0x20E03AC, 0x110b0},
{ 0x20E03B0, 0x110b0},
{ 0x20E03B4, 0x110b0},
{ 0x20E03B8, 0x110b0},
{ 0x20E03BC, 0x110b0},
{ 0x20E03C0, 0x110b0},
{ 0x20E03D4, 0xb0b0},
{ 0x20E03D8, 0xb0b0},
{ 0x20E03DC, 0xb0b0},
{ 0x20E03E0, 0xb0b0},
{ 0x20E03E4, 0xb0b0},
{ 0x20E03E8, 0xb0b0},
{ 0x20E03FC, 0x1b8b1},
{ 0x20E0404, 0xb0b1},
{ 0x20E0408, 0x1b0b0},
{ 0x20E0410, 0x1b8b1},
{ 0x20E0414, 0x1b0b0},
{ 0x20E0418, 0x1b0b0},
{ 0x20E041C, 0x1b0b0},
{ 0x20E0420, 0x1b0b0},
{ 0x20E0424, 0x1b0b0},
{ 0x20E0428, 0x1b0b0},
{ 0x20E042C, 0x1b0b0},
{ 0x20E0430, 0x1b0b0},
{ 0x20E0434, 0x1b0b0},
{ 0x20E0438, 0x1b0b0},
{ 0x20E043C, 0x1b0b0},
{ 0x20E0440, 0x1b0b0},
{ 0x20E0444, 0x1b0b0},
{ 0x20E0448, 0x1b0b0},
{ 0x20E044C, 0x1b0b0},
{ 0x20E0450, 0x1b0b0},
{ 0x20E0454, 0x1b0b0},
{ 0x20E0458, 0x1b0b0},
{ 0x20E045C, 0x1b0b0},
{ 0x20E0460, 0x1b0b0},
{ 0x20E0464, 0x1b0b0},
{ 0x20E0468, 0x1b0b0},
{ 0x20E046C, 0x1b0b0},
{ 0x20E0470, 0x1b0b0},
{ 0x20E0474, 0x1b0b0},
{ 0x20E0478, 0x1b0b0},
{ 0x20E047C, 0x1b0b0},
{ 0x20E0480, 0x1b0b0},
{ 0x20E0484, 0x1b0b0},
{ 0x20E0488, 0xb0b0},
{ 0x20E0490, 0x30b0},
{ 0x20E0498, 0x30b1},
{ 0x20E049C, 0x30b0},
{ 0x20E04A0, 0x30b1},
{ 0x20E04A4, 0xb0b1},
{ 0x20E04AC, 0x30b0},
{ 0x20E04B0, 0x30b0},
{ 0x20E04B4, 0x30b0},
{ 0x20E04E0, 0xb0b0},
{ 0x20E04E8, 0xb0b0},
{ 0x20E04F0, 0xb0b0},
{ 0x20E04F4, 0xb0b0},
{ 0x20E0508, 0x3081},
{ 0x20E050C, 0x3081},
{ 0x20E0510, 0x3081},
{ 0x20E0514, 0x3081},
{ 0x20E0518, 0x3081},
{ 0x20E051C, 0x3081},
{ 0x20E0520, 0x30b1},
{ 0x20E0524, 0x30b1},
{ 0x20E0528, 0x30b1},
{ 0x20E052C, 0x30b1},
{ 0x20E0530, 0x30b1},
{ 0x20E0534, 0x30b1},
{ 0x20E0538, 0x3081},
{ 0x20E053C, 0x3081},
{ 0x20E0540, 0x3081},
{ 0x20E0544, 0x3081},
{ 0x20E0548, 0x3081},
{ 0x20E054C, 0x3081},
{ 0x20E0550, 0x30b1},
{ 0x20E0554, 0x30b1},
{ 0x20E0558, 0x30b1},
{ 0x20E055C, 0x30b1},
{ 0x20E0560, 0x30b1},
{ 0x20E0564, 0x30b1},
{ 0x20E056C, 0x30b0},
{ 0x20E0570, 0x1b0b0},
{ 0x20E0574, 0x1b0b0},
{ 0x20E0578, 0x1b0b0},
{ 0x20E057C, 0x1b0b0},
{ 0x20E0598, 0x10071},
{ 0x20E059C, 0x17071},
{ 0x20E05A0, 0x17071},
{ 0x20E05A4, 0x17071},
{ 0x20E05A8, 0x17071},
{ 0x20E05AC, 0x17071},
{ 0x20E05B0, 0x1b0b0},
{ 0x20E05B4, 0x1b0b0},
{ 0x20E05B8, 0x1b0b1},
{ 0x20E05BC, 0x1b0b1},
{ 0x20E05C0, 0x100f9},
{ 0x20E05C4, 0x170f9},
{ 0x20E05C8, 0x170f9},
{ 0x20E05CC, 0x170f9},
{ 0x20E05D0, 0x170f9},
{ 0x20E05D4, 0x170f9},
{ 0x20E05D8, 0x170f9},
{ 0x20E05DC, 0x170f9},
{ 0x20E05E0, 0x170f9},
{ 0x20E05E4, 0x170f9},
{ 0x20E05E8, 0x17071},
{ 0x20E083C, 0x2},
// (Global Power Controller}
{ 0x20DC000, 0x140000},
{ 0x20DC008, 0x2077fe0b},
{ 0x20DC00C, 0xff7db18f},
{ 0x20DC010, 0xfbfe0003},
{ 0x20DC014, 0xff2ff93f},
// (Power Management Unit}
{ 0x20C8120, 0x11775},
{ 0x20C8140, 0x4c0016},
{ 0x20C8160, 0x8003000a},
// (Clock Controller Module}
{ 0x20C4004, 0x20000},
{ 0x20C4018, 0x269114},
{ 0x20C401C, 0x4510a9c0},
{ 0x20C4020, 0x13212c06},
{ 0x20C4028, 0x0},
{ 0x20C402C, 0x4b600},
{ 0x20C4030, 0x30074792},
{ 0x20C4038, 0x12153},
{ 0x20C4054, 0x78},
{ 0x20C4060, 0x10e008e},
{ 0x20C4064, 0x2fe62},
{ 0x20C4068, 0xf0c03f0f},
{ 0x20C406C, 0x333c0c00},
{ 0x20C4070, 0x3fff003f},
{ 0x20C4074, 0xfff33ff3},
{ 0x20C4078, 0xc0c3fc},
{ 0x20C407C, 0xf030fff},
{ 0x20C4080, 0x3cfc33},
{ 0x20C8000, 0x80002053},
{ 0x20C8010, 0x80003040},
{ 0x20C8020, 0x3840},
{ 0x20C8070, 0x119006},
{ 0x20C80A0, 0x80002025},
{ 0x20C80B0, 0x13a74},
{ 0x20C80C0, 0xf4240},
{ 0x20C80E0, 0x8030200f},
{ 0x20C80F0, 0xd3d1d0cc},
{ 0x20C8100, 0x5258d0db}
};
}
struct Board::L2_cache : Hw::Pl310
{
L2_cache(Genode::addr_t mmio) : Hw::Pl310(mmio)
{
Aux::access_t aux = 0;
Aux::Full_line_of_zero::set(aux, true);
Aux::Associativity::set(aux, Aux::Associativity::WAY_16);
Aux::Way_size::set(aux, Aux::Way_size::KB_16);
Aux::Replacement_policy::set(aux, Aux::Replacement_policy::PRAND);
Aux::Ns_lockdown::set(aux, true);
Aux::Data_prefetch::set(aux, true);
Aux::Inst_prefetch::set(aux, true);
Aux::Early_bresp::set(aux, true);
write<Aux>(aux);
Tag_ram::access_t tag_ram = 0;
Tag_ram::Setup_latency::set(tag_ram, 2);
Tag_ram::Read_latency::set(tag_ram, 3);
Tag_ram::Write_latency::set(tag_ram, 1);
write<Tag_ram>(tag_ram);
Data_ram::access_t data_ram = 0;
Data_ram::Setup_latency::set(data_ram, 2);
Data_ram::Read_latency::set(data_ram, 3);
Data_ram::Write_latency::set(data_ram, 1);
write<Data_ram>(data_ram);
Prefetch_ctrl::access_t prefetch = read<Prefetch_ctrl>();
Prefetch_ctrl::Data_prefetch::set(prefetch, 1);
Prefetch_ctrl::Inst_prefetch::set(prefetch, 1);
write<Prefetch_ctrl>(prefetch | 0xF);
}
using Hw::Pl310::invalidate;
void enable()
{
Pl310::mask_interrupts();
write<Control::Enable>(1);
}
void disable() {
write<Control::Enable>(0);
}
};
#endif /* _SRC__BOOTSTRAP__SPEC__NIT6_SOLOX__BOARD_H_ */

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/*
* \brief Pbxa9 specific board definitions
* \author Stefan Kalkowski
* \date 2017-02-20
*/
/*
* Copyright (C) 2017 Genode Labs GmbH
*
* This file is part of the Genode OS framework, which is distributed
* under the terms of the GNU Affero General Public License version 3.
*/
#ifndef _SRC__BOOTSTRAP__SPEC__WAND_QUAD__BOARD_H_
#define _SRC__BOOTSTRAP__SPEC__WAND_QUAD__BOARD_H_
#include <hw/spec/arm/wand_quad_board.h>
#include <spec/arm/cortex_a9_actlr.h>
#include <spec/arm/cortex_a9_page_table.h>
#include <spec/arm/cpu.h>
#include <hw/spec/arm/gicv2.h>
namespace Board {
using namespace Hw::Wand_quad_board;
using Pic = Hw::Gicv2;
struct L2_cache;
static constexpr bool NON_SECURE = false;
static volatile unsigned long initial_values[][2] {
// (IOMUX Controller)
{ 0x20e0000, 0x1 },
{ 0x20e0004, 0x48643005 },
{ 0x20e0008, 0x221 },
{ 0x20e000c, 0x1e00040 },
{ 0x20e0034, 0x593e4a4 },
{ 0x20e004c, 0x0 },
{ 0x20e0050, 0x0 },
{ 0x20e0054, 0x0 },
{ 0x20e0090, 0x1 },
{ 0x20e0094, 0x1 },
{ 0x20e0098, 0x1 },
{ 0x20e00a4, 0x16 },
{ 0x20e00a8, 0x4 },
{ 0x20e00ac, 0x2 },
{ 0x20e00b0, 0x2 },
{ 0x20e00b4, 0x2 },
{ 0x20e00b8, 0x2 },
{ 0x20e00c4, 0x11 },
{ 0x20e015c, 0x0 },
{ 0x20e0160, 0x0 },
{ 0x20e0164, 0x0 },
{ 0x20e0168, 0x0 },
{ 0x20e016c, 0x0 },
{ 0x20e0170, 0x0 },
{ 0x20e0174, 0x0 },
{ 0x20e0178, 0x0 },
{ 0x20e017c, 0x0 },
{ 0x20e0180, 0x0 },
{ 0x20e0184, 0x0 },
{ 0x20e0188, 0x0 },
{ 0x20e018c, 0x0 },
{ 0x20e0190, 0x0 },
{ 0x20e0194, 0x0 },
{ 0x20e0198, 0x0 },
{ 0x20e019c, 0x0 },
{ 0x20e01a0, 0x0 },
{ 0x20e01a4, 0x0 },
{ 0x20e01a8, 0x0 },
{ 0x20e01ac, 0x0 },
{ 0x20e01b0, 0x0 },
{ 0x20e01b4, 0x0 },
{ 0x20e01b8, 0x0 },
{ 0x20e01bc, 0x0 },
{ 0x20e01c0, 0x0 },
{ 0x20e01c4, 0x0 },
{ 0x20e01c8, 0x0 },
{ 0x20e01cc, 0x0 },
{ 0x20e01d4, 0x1 },
{ 0x20e01e4, 0x3 },
{ 0x20e0220, 0x0 },
{ 0x20e0224, 0x3 },
{ 0x20e022c, 0x4 },
{ 0x20e023c, 0x16 },
{ 0x20e0248, 0x12 },
{ 0x20e0250, 0x5 },
{ 0x20e0264, 0x5 },
{ 0x20e0268, 0x4 },
{ 0x20e026c, 0x4 },
{ 0x20e0270, 0x4 },
{ 0x20e0274, 0x4 },
{ 0x20e02b8, 0x0 },
{ 0x20e0320, 0x2 },
{ 0x20e0348, 0x0 },
{ 0x20e0354, 0x0 },
{ 0x20e0358, 0x0 },
{ 0x20e035c, 0x0 },
{ 0x20e0360, 0x17059 },
{ 0x20e0364, 0x17059 },
{ 0x20e0368, 0x17059 },
{ 0x20e03a0, 0xf0b0 },
{ 0x20e03a4, 0x100b1 },
{ 0x20e03a8, 0x100b1 },
{ 0x20e03ac, 0x100b1 },
{ 0x20e03b8, 0x1b8b1 },
{ 0x20e03c0, 0x1b0b1 },
{ 0x20e03c4, 0x1b0b1 },
{ 0x20e03c8, 0x1b0b1 },
{ 0x20e03cc, 0x1b0b1 },
{ 0x20e03d8, 0x1b8b1 },
{ 0x20e0470, 0x10 },
{ 0x20e0474, 0x10 },
{ 0x20e0478, 0x10 },
{ 0x20e047c, 0x10 },
{ 0x20e0484, 0x10 },
{ 0x20e0488, 0x10 },
{ 0x20e048c, 0x10 },
{ 0x20e0490, 0x10 },
{ 0x20e0494, 0x10 },
{ 0x20e0498, 0x10 },
{ 0x20e049c, 0x10 },
{ 0x20e04a0, 0x10 },
{ 0x20e04a4, 0x10 },
{ 0x20e04a8, 0x10 },
{ 0x20e04ac, 0x10 },
{ 0x20e04b0, 0x10 },
{ 0x20e04b4, 0x10 },
{ 0x20e04b8, 0x10 },
{ 0x20e04bc, 0x10 },
{ 0x20e04c0, 0x10 },
{ 0x20e04c4, 0x10 },
{ 0x20e04c8, 0x10 },
{ 0x20e04cc, 0x10 },
{ 0x20e04d0, 0x10 },
{ 0x20e04d4, 0x10 },
{ 0x20e04d8, 0x10 },
{ 0x20e04dc, 0x10 },
{ 0x20e04e0, 0x10 },
{ 0x20e05e8, 0xb0 },
{ 0x20e05f0, 0xb0 },
{ 0x20e05f4, 0x17059 },
{ 0x20e05fc, 0xb0 },
{ 0x20e0600, 0xb0b0 },
{ 0x20e060c, 0x1b8b1 },
{ 0x20e0618, 0x1b0a8 },
{ 0x20e0638, 0x130b0 },
{ 0x20e063c, 0x110b0 },
{ 0x20e0640, 0x130b0 },
{ 0x20e0644, 0x130b0 },
{ 0x20e064c, 0x1b0b0 },
{ 0x20e06a4, 0x10059 },
{ 0x20e0704, 0x0 },
{ 0x20e0708, 0x1b0b1 },
{ 0x20e0738, 0x10059 },
{ 0x20e073c, 0x10059 },
{ 0x20e0740, 0x17059 },
{ 0x20e0744, 0x17059 },
{ 0x20e083c, 0x1 },
{ 0x20e0870, 0x0 },
{ 0x20e0874, 0x0 },
{ 0x20e08a8, 0x2 },
{ 0x20e08ac, 0x2 },
{ 0x20e092c, 0x1 },
{ 0x20e0930, 0x1 },
// (Global Power Controller)
{ 0x20dc008, 0x6a23e613 },
{ 0x20dc00c, 0xff69b64f },
{ 0x20dc010, 0xfffe0003 },
{ 0x20dc014, 0xff30f7ff },
// (Power Management Unit)
{ 0x20c8120, 0x11775 },
{ 0x20c8140, 0x580016 },
{ 0x20c8160, 0x8000000b },
{ 0x20c8170, 0xc0672f67 },
// (Clock Controller Module)
{ 0x20c4018, 0x10204 },
{ 0x20c402c, 0x7312c1 },
{ 0x20c4030, 0x32271f92 },
{ 0x20c4034, 0x12680 },
{ 0x20c4038, 0x12090 },
{ 0x20c4054, 0x78 },
{ 0x20c4058, 0x41a0000 },
{ 0x20c4060, 0x10e0101 },
{ 0x20c4064, 0x2fe62 },
{ 0x20c4068, 0xc03f0f },
{ 0x20c406c, 0x30fc00 },
{ 0x20c4070, 0x3ff0033 },
{ 0x20c4074, 0x3ff3303f },
{ 0x20c4078, 0x30c300 },
{ 0x20c407c, 0xf0000f3 },
{ 0x20c4080, 0xc00 },
{ 0x20c8000, 0x80002053 },
{ 0x20c8020, 0x3040 },
{ 0x20c8070, 0x1006 },
{ 0x20c80a0, 0x80002031 },
{ 0x20c80b0, 0x7a120 },
{ 0x20c80c0, 0xf4240 },
{ 0x20c80e0, 0x80002003 },
{ 0x20c80f0, 0x9391508c },
{ 0x20c8100, 0x5058d01b }
};
}
struct Board::L2_cache : Hw::Pl310
{
L2_cache(Genode::addr_t mmio) : Hw::Pl310(mmio)
{
Aux::access_t aux = 0;
Aux::Full_line_of_zero::set(aux, true);
Aux::Associativity::set(aux, Aux::Associativity::WAY_16);
Aux::Way_size::set(aux, Aux::Way_size::KB_64);
Aux::Share_override::set(aux, true);
Aux::Replacement_policy::set(aux, Aux::Replacement_policy::PRAND);
Aux::Ns_lockdown::set(aux, true);
Aux::Data_prefetch::set(aux, true);
Aux::Inst_prefetch::set(aux, true);
Aux::Early_bresp::set(aux, true);
write<Aux>(aux);
Tag_ram::access_t tag_ram = 0;
Tag_ram::Setup_latency::set(tag_ram, 2);
Tag_ram::Read_latency::set(tag_ram, 3);
Tag_ram::Write_latency::set(tag_ram, 1);
write<Tag_ram>(tag_ram);
Data_ram::access_t data_ram = 0;
Data_ram::Setup_latency::set(data_ram, 2);
Data_ram::Read_latency::set(data_ram, 3);
Data_ram::Write_latency::set(data_ram, 1);
write<Data_ram>(data_ram);
Prefetch_ctrl::access_t prefetch = 0;
Prefetch_ctrl::Data_prefetch::set(prefetch, 1);
Prefetch_ctrl::Inst_prefetch::set(prefetch, 1);
write<Prefetch_ctrl>(prefetch | 0xF);
}
using Hw::Pl310::invalidate;
void enable()
{
Pl310::mask_interrupts();
write<Control::Enable>(1);
}
void disable() {
write<Control::Enable>(0);
}
};
#endif /* _SRC__BOOTSTRAP__SPEC__WAND_QUAD__BOARD_H_ */

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/*
* \brief Specific bootstrap implementations
* \author Stefan Kalkowski
* \author Josef Soentgen
* \author Martin Stein
* \date 2014-02-25
*/
/*
* Copyright (C) 2014-2017 Genode Labs GmbH
*
* This file is part of the Genode OS framework, which is distributed
* under the terms of the GNU Affero General Public License version 3.
*/
#include <platform.h>
#include <spec/arm/imx_aipstz.h>
using namespace Board;
Bootstrap::Platform::Board::Board()
:
early_ram_regions(Memory_region { RAM_BASE, RAM_SIZE }),
core_mmio(Memory_region { UART_BASE,
UART_SIZE },
Memory_region { CORTEX_A9_PRIVATE_MEM_BASE,
CORTEX_A9_PRIVATE_MEM_SIZE },
Memory_region { PL310_MMIO_BASE,
PL310_MMIO_SIZE })
{
Aipstz aipstz_1(AIPS_1_MMIO_BASE);
Aipstz aipstz_2(AIPS_2_MMIO_BASE);
unsigned num_values = sizeof(initial_values) / (2*sizeof(unsigned long));
for (unsigned i = 0; i < num_values; i++)
*((volatile unsigned long*)initial_values[i][0]) = initial_values[i][1];
}
bool Board::Cpu::errata(Board::Cpu::Errata err) {
return (err == ARM_764369) ? true : false; }
void Board::Cpu::wake_up_all_cpus(void * const entry)
{
struct Src : Genode::Mmio
{
struct Scr : Register<0x0, 32>
{
struct Core_1_reset : Bitfield<14,1> {};
struct Core_2_reset : Bitfield<15,1> {};
struct Core_3_reset : Bitfield<16,1> {};
struct Core_1_enable : Bitfield<22,1> {};
struct Core_2_enable : Bitfield<23,1> {};
struct Core_3_enable : Bitfield<24,1> {};
};
struct Gpr1 : Register<0x20, 32> {}; /* ep core 0 */
struct Gpr3 : Register<0x28, 32> {}; /* ep core 1 */
struct Gpr5 : Register<0x30, 32> {}; /* ep core 2 */
struct Gpr7 : Register<0x38, 32> {}; /* ep core 3 */
Src(void * const entry) : Genode::Mmio(SRC_MMIO_BASE)
{
write<Gpr3>((Gpr3::access_t)entry);
write<Gpr5>((Gpr5::access_t)entry);
write<Gpr7>((Gpr7::access_t)entry);
Scr::access_t v = read<Scr>();
Scr::Core_1_enable::set(v,1);
Scr::Core_1_reset::set(v,1);
Scr::Core_2_enable::set(v,1);
Scr::Core_2_reset::set(v,1);
Scr::Core_3_enable::set(v,1);
Scr::Core_3_reset::set(v,1);
write<Scr>(v);
}
};
Src src(entry);
}

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/*
* \brief Board driver
* \author Stefan Kalkowski
* \date 2019-01-05
*/
/*
* Copyright (C) 2019 Genode Labs GmbH
*
* This file is part of the Genode OS framework, which is distributed
* under the terms of the GNU Affero General Public License version 3.
*/
#ifndef _CORE__SPEC__IMX6Q_SABRELITE__BOARD_H_
#define _CORE__SPEC__IMX6Q_SABRELITE__BOARD_H_
/* base-hw internal includes */
#include <hw/spec/arm/gicv2.h>
#include <hw/spec/arm/imx6q_sabrelite_board.h>
/* base-hw core includes */
#include <spec/arm/cortex_a9_global_timer.h>
#include <spec/cortex_a9/cpu.h>
namespace Board {
using namespace Hw::Imx6q_sabrelite_board;
class Global_interrupt_controller { public: void init() {} };
class Pic : public Hw::Gicv2 { public: Pic(Global_interrupt_controller &) { } };
using L2_cache = Hw::Pl310;
L2_cache & l2_cache();
enum {
CORTEX_A9_GLOBAL_TIMER_CLK = 396000000, /* timer clk runs half the CPU freq */
CORTEX_A9_GLOBAL_TIMER_DIV = 100,
};
}
#endif /* _CORE__SPEC__WAND_QUAD__BOARD_H_ */

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/*
* \brief Board driver
* \author Stefan Kalkowski
* \date 2017-10-18
*/
/*
* Copyright (C) 2017 Genode Labs GmbH
*
* This file is part of the Genode OS framework, which is distributed
* under the terms of the GNU Affero General Public License version 3.
*/
#ifndef _CORE__SPEC__NIT6_SOLOX__BOARD_H_
#define _CORE__SPEC__NIT6_SOLOX__BOARD_H_
/* base-hw internal includes */
#include <hw/spec/arm/gicv2.h>
#include <hw/spec/arm/nit6_solox_board.h>
/* base-hw core includes */
#include <spec/arm/cortex_a9_global_timer.h>
#include <spec/cortex_a9/cpu.h>
namespace Board {
using namespace Hw::Nit6_solox_board;
class Global_interrupt_controller { public: void init() {} };
class Pic : public Hw::Gicv2 { public: Pic(Global_interrupt_controller &) { } };
using L2_cache = Hw::Pl310;
L2_cache & l2_cache();
enum {
CORTEX_A9_GLOBAL_TIMER_CLK = 500000000, /* timer clk runs half the CPU freq */
CORTEX_A9_GLOBAL_TIMER_DIV = 100,
};
}
#endif /* _CORE__SPEC__NIT6_SOLOX__BOARD_H_ */

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repos/base-hw/src/core/board/wand_quad/board.h
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/*
* \brief Board driver
* \author Stefan Kalkowski
* \author Martin Stein
* \date 2014-02-25
*/
/*
* Copyright (C) 2014-2017 Genode Labs GmbH
*
* This file is part of the Genode OS framework, which is distributed
* under the terms of the GNU Affero General Public License version 3.
*/
#ifndef _CORE__SPEC__WAND_QUAD__BOARD_H_
#define _CORE__SPEC__WAND_QUAD__BOARD_H_
/* base-hw internal includes */
#include <hw/spec/arm/gicv2.h>
#include <hw/spec/arm/wand_quad_board.h>
/* base-hw core includes */
#include <spec/arm/cortex_a9_global_timer.h>
#include <spec/cortex_a9/cpu.h>
namespace Board {
using namespace Hw::Wand_quad_board;
using L2_cache = Hw::Pl310;
class Global_interrupt_controller { public: void init() {} };
class Pic : public Hw::Gicv2 { public: Pic(Global_interrupt_controller &) { } };
L2_cache & l2_cache();
enum {
CORTEX_A9_GLOBAL_TIMER_CLK = 500000000, /* timer clk runs half the CPU freq */
CORTEX_A9_GLOBAL_TIMER_DIV = 100,
};
}
#endif /* _CORE__SPEC__WAND_QUAD__BOARD_H_ */

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repos/base-hw/src/include/hw/spec/arm/imx6q_sabrelite_board.h
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/*
* \brief i.MX6Quad Sabrelite specific board definitions
* \author Stefan Kalkowski
* \date 2019-05-16
*/
/*
* Copyright (C) 2019 Genode Labs GmbH
*
* This file is part of the Genode OS framework, which is distributed
* under the terms of the GNU Affero General Public License version 3.
*/
#ifndef _SRC__INCLUDE__HW__SPEC__ARM__IMX6Q_SABRELITE_BOARD_H_
#define _SRC__INCLUDE__HW__SPEC__ARM__IMX6Q_SABRELITE_BOARD_H_
#include <drivers/defs/imx6q_sabrelite.h>
#include <drivers/uart/imx.h>
#include <hw/spec/arm/boot_info.h>
#include <hw/spec/arm/cortex_a9.h>
#include <hw/spec/arm/pl310.h>
namespace Hw::Imx6q_sabrelite_board {
using namespace Imx6q_sabrelite;
using Cpu_mmio = Hw::Cortex_a9_mmio<CORTEX_A9_PRIVATE_MEM_BASE>;
using Serial = Genode::Imx_uart;
enum {
UART_BASE = UART_2_MMIO_BASE,
UART_SIZE = UART_2_MMIO_SIZE,
UART_CLOCK = 0, /* dummy value, not used */
};
static constexpr Genode::size_t NR_OF_CPUS = 4;
}
#endif /* _SRC__INCLUDE__HW__SPEC__ARM__IMX6Q_SABRELITE_BOARD_H_ */

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/*
* \brief Nit6 SOLOX specific board definitions
* \author Stefan Kalkowski
* \date 2019-05-16
*/
/*
* Copyright (C) 2019 Genode Labs GmbH
*
* This file is part of the Genode OS framework, which is distributed
* under the terms of the GNU Affero General Public License version 3.
*/
#ifndef _SRC__INCLUDE__HW__SPEC__ARM__NIT6_SOLOX_BOARD_H_
#define _SRC__INCLUDE__HW__SPEC__ARM__NIT6_SOLOX_BOARD_H_
#include <drivers/defs/nit6_solox.h>
#include <drivers/uart/imx.h>
#include <hw/spec/arm/boot_info.h>
#include <hw/spec/arm/cortex_a9.h>
#include <hw/spec/arm/pl310.h>
namespace Hw::Nit6_solox_board {
using namespace Nit6_solox;
using Cpu_mmio = Hw::Cortex_a9_mmio<CORTEX_A9_PRIVATE_MEM_BASE>;
using Serial = Genode::Imx_uart;
enum {
UART_BASE = UART_1_MMIO_BASE,
UART_SIZE = UART_1_MMIO_SIZE,
UART_CLOCK = 0, /* dummy value, not used */
};
static constexpr Genode::size_t NR_OF_CPUS = 1;
}
#endif /* _SRC__INCLUDE__HW__SPEC__ARM__NIT6_SOLOX_BOARD_H_ */

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/*
* \brief Wandboard Quad specific definitions
* \author Stefan Kalkowski
* \date 2019-05-16
*/
/*
* Copyright (C) 2019 Genode Labs GmbH
*
* This file is part of the Genode OS framework, which is distributed
* under the terms of the GNU Affero General Public License version 3.
*/
#ifndef _SRC__INCLUDE__HW__SPEC__ARM__WAND_QUAD_BOARD_H_
#define _SRC__INCLUDE__HW__SPEC__ARM__WAND_QUAD_BOARD_H_
#include <drivers/defs/wand_quad.h>
#include <drivers/uart/imx.h>
#include <hw/spec/arm/cortex_a9.h>
#include <hw/spec/arm/pl310.h>
#include <hw/spec/arm/boot_info.h>
namespace Hw::Wand_quad_board {
using namespace Wand_quad;
using Cpu_mmio = Hw::Cortex_a9_mmio<CORTEX_A9_PRIVATE_MEM_BASE>;
using Serial = Genode::Imx_uart;
enum {
UART_BASE = UART_1_MMIO_BASE,
UART_SIZE = UART_1_MMIO_SIZE,
UART_CLOCK = 0, /* dummy value, not used */
};
static constexpr Genode::size_t NR_OF_CPUS = 4;
}
#endif /* _SRC__INCLUDE__HW__SPEC__ARM__WAND_QUAD_BOARD_H_ */

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repos/base/include/drivers/defs/imx6.h
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/*
* \brief MMIO and IRQ definitions common to i.MX6 SoC
* \author Nikolay Golikov <nik@ksyslabs.org>
* \author Josef Soentgen
* \author Martin Stein
* \date 2017-06-20
*/
/*
* Copyright (C) 2017 Genode Labs GmbH
*
* This file is part of the Genode OS framework, which is distributed
* under the terms of the GNU Affero General Public License version 3.
*/
#ifndef _INCLUDE__DRIVERS__DEFS__IMX6_H_
#define _INCLUDE__DRIVERS__DEFS__IMX6_H_
namespace Imx6 {
enum {
/* device IO memory */
MMIO_BASE = 0x00000000,
MMIO_SIZE = 0x10000000,
UART_1_IRQ = 58,
UART_1_MMIO_BASE = 0x02020000,
UART_1_MMIO_SIZE = 0x00004000,
UART_2_IRQ = 59,
UART_2_MMIO_BASE = 0x021e8000,
UART_2_MMIO_SIZE = 0x00004000,
/* timer */
EPIT_2_IRQ = 89,
EPIT_2_MMIO_BASE = 0x020d4000,
EPIT_2_MMIO_SIZE = 0x00004000,
/* ARM IP Bus control */
AIPS_1_MMIO_BASE = 0x0207c000,
AIPS_1_MMIO_SIZE = 0x00004000,
AIPS_2_MMIO_BASE = 0x0217c000,
AIPS_2_MMIO_SIZE = 0x00004000,
/* CPU */
CORTEX_A9_PRIVATE_MEM_BASE = 0x00a00000,
CORTEX_A9_PRIVATE_MEM_SIZE = 0x00002000,
/* L2 cache controller */
PL310_MMIO_BASE = 0x00a02000,
PL310_MMIO_SIZE = 0x00001000,
/* System reset controller */
SRC_MMIO_BASE = 0x20d8000,
/* SD host controller */
SDHC_1_IRQ = 54,
SDHC_1_MMIO_BASE = 0x02190000,
SDHC_1_MMIO_SIZE = 0x00004000,
SDHC_2_IRQ = 55,
SDHC_2_MMIO_BASE = 0x02194000,
SDHC_2_MMIO_SIZE = 0x00004000,
SDHC_3_IRQ = 56,
SDHC_3_MMIO_BASE = 0x02198000,
SDHC_3_MMIO_SIZE = 0x00004000,
SDHC_4_IRQ = 57,
SDHC_4_MMIO_BASE = 0x0219c000,
SDHC_4_MMIO_SIZE = 0x00004000,
/* GPIO */
GPIO1_MMIO_BASE = 0x0209c000,
GPIO1_MMIO_SIZE = 0x4000,
GPIO2_MMIO_BASE = 0x020a0000,
GPIO2_MMIO_SIZE = 0x4000,
GPIO3_MMIO_BASE = 0x020a4000,
GPIO3_MMIO_SIZE = 0x4000,
GPIO4_MMIO_BASE = 0x020a8000,
GPIO4_MMIO_SIZE = 0x4000,
GPIO5_MMIO_BASE = 0x020ac000,
GPIO5_MMIO_SIZE = 0x4000,
GPIO6_MMIO_BASE = 0x020b0000,
GPIO6_MMIO_SIZE = 0x4000,
GPIO7_MMIO_BASE = 0x020b4000,
GPIO7_MMIO_SIZE = 0x4000,
GPIO1_IRQL = 98,
GPIO1_IRQH = 99,
GPIO2_IRQL = 100,
GPIO2_IRQH = 101,
GPIO3_IRQL = 102,
GPIO3_IRQH = 103,
GPIO4_IRQL = 104,
GPIO4_IRQH = 105,
GPIO5_IRQL = 106,
GPIO5_IRQH = 107,
GPIO6_IRQL = 108,
GPIO6_IRQH = 109,
GPIO7_IRQL = 110,
GPIO7_IRQH = 111,
};
};
#endif /* _INCLUDE__DRIVERS__DEFS__IMX6_H_ */

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repos/base/include/drivers/defs/imx6q_sabrelite.h
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@ -1,30 +0,0 @@
/*
* \brief MMIO and IRQ definitions of the i.MX6Quad Sabrelite
* \author Stefan Kalkowski
* \date 2019-01-05
*/
/*
* Copyright (C) 2019 Genode Labs GmbH
*
* This file is part of the Genode OS framework, which is distributed
* under the terms of the GNU Affero General Public License version 3.
*/
#ifndef _INCLUDE__DRIVERS__DEFS__IMX6Q_SABRELITE_H_
#define _INCLUDE__DRIVERS__DEFS__IMX6Q_SABRELITE_H_
/* Genode includes */
#include <drivers/defs/imx6.h>
namespace Imx6q_sabrelite {
using namespace Imx6;
enum {
RAM_BASE = 0x10000000,
RAM_SIZE = 0x40000000,
};
};
#endif /* _INCLUDE__DRIVERS__DEFS__IMX6Q_SABRELITE_H_ */

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repos/base/include/drivers/defs/nit6_solox.h
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/*
* \brief MMIO and IRQ definitions for Nit6 SOLOX board
* \author Stefan Kalkowski
* \date 2017-10-18
*/
/*
* Copyright (C) 2017 Genode Labs GmbH
*
* This file is part of the Genode OS framework, which is distributed
* under the terms of the GNU Affero General Public License version 3.
*/
#ifndef _INCLUDE__DRIVERS__DEFS__NIT6_SOLOX_H_
#define _INCLUDE__DRIVERS__DEFS__NIT6_SOLOX_H_
/* Genode includes */
#include <drivers/defs/imx6.h>
namespace Nit6_solox {
using namespace Imx6;
enum {
/* normal RAM */
RAM_BASE = 0x80000000,
RAM_SIZE = 0x40000000,
};
};
#endif /* _INCLUDE__DRIVERS__DEFS__NIT6_SOLOX_H_ */

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repos/base/include/drivers/defs/wand_quad.h
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/*
* \brief MMIO and IRQ definitions of the Wandboard Quad
* \author Nikolay Golikov <nik@ksyslabs.org>
* \author Josef Soentgen
* \author Martin Stein
* \date 2014-02-25
*/
/*
* Copyright (C) 2014-2016 Ksys Labs LLC
* Copyright (C) 2014-2017 Genode Labs GmbH
*
* This file is part of the Genode OS framework, which is distributed
* under the terms of the GNU Affero General Public License version 3.
*/
#ifndef _INCLUDE__DRIVERS__DEFS__WAND_QUAD_H_
#define _INCLUDE__DRIVERS__DEFS__WAND_QUAD_H_
/* Genode includes */
#include <drivers/defs/imx6.h>
namespace Wand_quad {
using namespace Imx6;
enum {
/* normal RAM */
RAM_BASE = 0x10000000,
RAM_SIZE = 0x80000000,
};
};
#endif /* _INCLUDE__DRIVERS__DEFS__WAND_QUAD_H_ */

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repos/base/src/timer/epit/imx6/timer.cc
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@ -14,19 +14,22 @@
* under the terms of the GNU Affero General Public License version 3. * under the terms of the GNU Affero General Public License version 3.
*/ */
/* base include */
#include <drivers/defs/imx6.h>
/* local include */ /* local include */
#include <time_source.h> #include <time_source.h>
enum {
EPIT_2_IRQ = 89,
EPIT_2_MMIO_BASE = 0x020d4000,
EPIT_2_MMIO_SIZE = 0x00004000
};
using namespace Genode; using namespace Genode;
Timer::Time_source::Time_source(Env &env) Timer::Time_source::Time_source(Env &env)
: :
Attached_mmio(env, Imx6::EPIT_2_MMIO_BASE, Imx6::EPIT_2_MMIO_SIZE), Attached_mmio(env, EPIT_2_MMIO_BASE, EPIT_2_MMIO_SIZE),
Signalled_time_source(env), Signalled_time_source(env),
_timer_irq(env, unsigned(Imx6::EPIT_2_IRQ)) _timer_irq(env, unsigned(EPIT_2_IRQ))
{ {
_timer_irq.sigh(_signal_handler); _timer_irq.sigh(_signal_handler);
while (read<Cr::Swr>()) ; while (read<Cr::Swr>()) ;