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hw: fix bug in Kernel::update_*_region

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fix #1125
This commit is contained in:
Martin Stein 2014-04-17 12:42:39 +02:00 committed by Christian Helmuth
parent 0e208c3d3d
commit 58c4f1585b
3 changed files with 30 additions and 3 deletions
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2
base-hw/src/core/kernel/kernel.cc
View File

@ -213,7 +213,7 @@ extern "C" void init_kernel_multiprocessor()
/* synchronize data view of all processors */
Processor::invalidate_data_caches();
Processor::invalidate_instruction_caches();
Processor::invalidate_instr_caches();
Processor::invalidate_control_flow_predictions();
Processor::data_synchronization_barrier();

27
base-hw/src/core/kernel/thread.cc
View File

@ -543,6 +543,19 @@ void Thread::_call_update_pd()
void Thread::_call_update_data_region()
{
/*
* FIXME: If the caller is not a core thread, the kernel operates in a
* different address space than the caller. Combined with the fact
* that at least ARMv7 doesn't provide cache operations by physical
* address, this prevents us from selectively maintaining caches.
* The future solution will be a kernel that is mapped to every
* address space so we can use virtual addresses of the caller. Up
* until then we apply operations to caches as a whole instead.
*/
if (!_core()) {
Processor::flush_data_caches();
return;
}
auto base = (addr_t)user_arg_1();
auto const size = (size_t)user_arg_2();
Processor::flush_data_caches_by_virt_region(base, size);
@ -551,6 +564,20 @@ void Thread::_call_update_data_region()
void Thread::_call_update_instr_region()
{
/*
* FIXME: If the caller is not a core thread, the kernel operates in a
* different address space than the caller. Combined with the fact
* that at least ARMv7 doesn't provide cache operations by physical
* address, this prevents us from selectively maintaining caches.
* The future solution will be a kernel that is mapped to every
* address space so we can use virtual addresses of the caller. Up
* until then we apply operations to caches as a whole instead.
*/
if (!_core()) {
Processor::flush_data_caches();
Processor::invalidate_instr_caches();
return;
}
auto base = (addr_t)user_arg_1();
auto const size = (size_t)user_arg_2();
Processor::flush_data_caches_by_virt_region(base, size);

4
base-hw/src/core/processor_driver/arm.h
View File

@ -625,7 +625,7 @@ namespace Arm
* Invalidate all entries of all instruction caches
*/
__attribute__((always_inline))
static void invalidate_instruction_caches()
static void invalidate_instr_caches()
{
asm volatile ("mcr p15, 0, %[rd], c7, c5, 0" :: [rd]"r"(0) : );
}
@ -646,7 +646,7 @@ namespace Arm
static void flush_caches()
{
flush_data_caches();
invalidate_instruction_caches();
invalidate_instr_caches();
}
/**