mirror of
https://github.com/genodelabs/genode.git
synced 2025-04-07 19:34:56 +00:00
vmm: rename State to Vcpu_state for clarity
Rename locally extended VCPU state from State to Vcpu_state for clarity. The local namespace only adds two accessor methods, which does not justify a local generic name. Ref #4968
This commit is contained in:
parent
0e49149a46
commit
558a00138c
@ -38,7 +38,7 @@ Cpu_base::System_register::System_register(unsigned op0,
|
||||
}
|
||||
|
||||
|
||||
bool Cpu_base::_handle_sys_reg(State & state)
|
||||
bool Cpu_base::_handle_sys_reg(Vcpu_state & state)
|
||||
{
|
||||
using Iss = System_register::Iss;
|
||||
|
||||
@ -76,7 +76,7 @@ bool Cpu_base::_handle_sys_reg(State & state)
|
||||
}
|
||||
|
||||
|
||||
void Cpu_base::_handle_wfi(State &state)
|
||||
void Cpu_base::_handle_wfi(Vcpu_state &state)
|
||||
{
|
||||
state.ip += sizeof(Genode::uint32_t);
|
||||
|
||||
@ -87,7 +87,7 @@ void Cpu_base::_handle_wfi(State &state)
|
||||
}
|
||||
|
||||
|
||||
void Cpu_base::_handle_startup(State &state)
|
||||
void Cpu_base::_handle_startup(Vcpu_state &state)
|
||||
{
|
||||
Generic_timer::setup_state(state);
|
||||
Gic::Gicd_banked::setup_state(state);
|
||||
@ -103,7 +103,7 @@ void Cpu_base::_handle_startup(State &state)
|
||||
}
|
||||
|
||||
|
||||
void Cpu_base::_handle_sync(State &state)
|
||||
void Cpu_base::_handle_sync(Vcpu_state &state)
|
||||
{
|
||||
/* check device number*/
|
||||
switch (Esr::Ec::get(state.esr_el2)) {
|
||||
@ -131,7 +131,7 @@ void Cpu_base::_handle_sync(State &state)
|
||||
}
|
||||
|
||||
|
||||
void Cpu_base::_handle_irq(State &state)
|
||||
void Cpu_base::_handle_irq(Vcpu_state &state)
|
||||
{
|
||||
switch (state.irqs.last_irq) {
|
||||
case VTIMER_IRQ:
|
||||
@ -143,7 +143,7 @@ void Cpu_base::_handle_irq(State &state)
|
||||
}
|
||||
|
||||
|
||||
void Cpu_base::_handle_hyper_call(State &state)
|
||||
void Cpu_base::_handle_hyper_call(Vcpu_state &state)
|
||||
{
|
||||
switch(state.reg(0)) {
|
||||
case Psci::PSCI_VERSION:
|
||||
@ -158,7 +158,7 @@ void Cpu_base::_handle_hyper_call(State &state)
|
||||
case Psci::CPU_ON_32: [[fallthrough]];
|
||||
case Psci::CPU_ON:
|
||||
_vm.cpu((unsigned)state.reg(1), [&] (Cpu & cpu) {
|
||||
State & local_state = cpu.state();
|
||||
Vcpu_state & local_state = cpu.state();
|
||||
cpu.initialize_boot(local_state, state.reg(2), state.reg(3));
|
||||
cpu.set_ready();
|
||||
});
|
||||
@ -171,14 +171,14 @@ void Cpu_base::_handle_hyper_call(State &state)
|
||||
}
|
||||
|
||||
|
||||
void Cpu_base::_handle_data_abort(State &state)
|
||||
void Cpu_base::_handle_data_abort(Vcpu_state &state)
|
||||
{
|
||||
_vm.bus().handle_memory_access(state, *static_cast<Cpu *>(this));
|
||||
state.ip += sizeof(Genode::uint32_t);
|
||||
}
|
||||
|
||||
|
||||
void Cpu_base::_update_state(State &state)
|
||||
void Cpu_base::_update_state(Vcpu_state &state)
|
||||
{
|
||||
if (!_gic.pending_irq(state)) return;
|
||||
|
||||
|
@ -63,17 +63,17 @@ class Vmm::Cpu_base
|
||||
unsigned cpu_id() const;
|
||||
bool active() const;
|
||||
Gic::Gicd_banked & gic();
|
||||
void dump(State & state);
|
||||
void handle_exception(State &state);
|
||||
void dump(Vcpu_state & state);
|
||||
void handle_exception(Vcpu_state &state);
|
||||
void recall();
|
||||
void initialize_boot(State &state,
|
||||
void initialize_boot(Vcpu_state &state,
|
||||
Genode::addr_t ip,
|
||||
Genode::addr_t dtb);
|
||||
virtual void setup_state(State &) { };
|
||||
virtual void setup_state(Vcpu_state &) { };
|
||||
|
||||
virtual ~Cpu_base() = default;
|
||||
|
||||
State & state() {
|
||||
Vcpu_state & state() {
|
||||
return _state->ref;
|
||||
}
|
||||
|
||||
@ -90,8 +90,8 @@ class Vmm::Cpu_base
|
||||
template <typename FUNC>
|
||||
void handle_signal(FUNC handler)
|
||||
{
|
||||
_vm_vcpu.with_state([this, handler](Vcpu_state &vmstate) {
|
||||
State & state = static_cast<State &>(vmstate);
|
||||
_vm_vcpu.with_state([this, handler](Genode::Vcpu_state &vmstate) {
|
||||
Vmm::Vcpu_state & state = static_cast<Vmm::Vcpu_state &>(vmstate);
|
||||
_state.construct(state);
|
||||
|
||||
try {
|
||||
@ -225,7 +225,7 @@ class Vmm::Cpu_base
|
||||
return (r->_encoding > _encoding); }
|
||||
};
|
||||
|
||||
struct State_container { State &ref; };
|
||||
struct Vcpu_state_container { Vcpu_state &ref; };
|
||||
|
||||
unsigned _vcpu_id;
|
||||
bool _active { true };
|
||||
@ -236,7 +236,7 @@ class Vmm::Cpu_base
|
||||
Genode::Vm_connection::Exit_config _exit_config { };
|
||||
Genode::Vm_connection::Vcpu _vm_vcpu;
|
||||
Genode::Avl_tree<System_register> _reg_tree {};
|
||||
Genode::Constructible<State_container> _state {};
|
||||
Genode::Constructible<Vcpu_state_container> _state {};
|
||||
Semaphore _cpu_ready {};
|
||||
|
||||
|
||||
@ -249,15 +249,15 @@ class Vmm::Cpu_base
|
||||
Generic_timer _timer;
|
||||
|
||||
void _handle_nothing() {}
|
||||
void _handle_startup(State &state);
|
||||
bool _handle_sys_reg(State &state);
|
||||
void _handle_brk(State &state);
|
||||
void _handle_wfi(State &state);
|
||||
void _handle_sync(State &state);
|
||||
void _handle_irq(State &state);
|
||||
void _handle_data_abort(State &state);
|
||||
void _handle_hyper_call(State &state);
|
||||
void _update_state(State &state);
|
||||
void _handle_startup(Vcpu_state &state);
|
||||
bool _handle_sys_reg(Vcpu_state &state);
|
||||
void _handle_brk(Vcpu_state &state);
|
||||
void _handle_wfi(Vcpu_state &state);
|
||||
void _handle_sync(Vcpu_state &state);
|
||||
void _handle_irq(Vcpu_state &state);
|
||||
void _handle_data_abort(Vcpu_state &state);
|
||||
void _handle_hyper_call(Vcpu_state &state);
|
||||
void _update_state(Vcpu_state &state);
|
||||
|
||||
public:
|
||||
|
||||
|
@ -164,7 +164,7 @@ Gic::Irq & Gic::Gicd_banked::irq(unsigned i)
|
||||
}
|
||||
|
||||
|
||||
void Gic::Gicd_banked::handle_irq(State &state)
|
||||
void Gic::Gicd_banked::handle_irq(Vcpu_state &state)
|
||||
{
|
||||
unsigned i = state.irqs.virtual_irq;
|
||||
if (i > MAX_IRQ) return;
|
||||
@ -175,7 +175,7 @@ void Gic::Gicd_banked::handle_irq(State &state)
|
||||
}
|
||||
|
||||
|
||||
bool Gic::Gicd_banked::pending_irq(State &state)
|
||||
bool Gic::Gicd_banked::pending_irq(Vcpu_state &state)
|
||||
{
|
||||
Genode::Mutex::Guard guard(big_gic_lock());
|
||||
|
||||
@ -211,7 +211,7 @@ Gic::Gicd_banked::Gicd_banked(Cpu_base & cpu, Gic & gic, Mmio_bus & bus)
|
||||
}
|
||||
}
|
||||
|
||||
void Gic::Gicd_banked::setup_state(State &state)
|
||||
void Gic::Gicd_banked::setup_state(Vcpu_state &state)
|
||||
{
|
||||
state.irqs.last_irq = SPURIOUS;
|
||||
state.irqs.virtual_irq = SPURIOUS;
|
||||
|
@ -137,9 +137,9 @@ class Vmm::Gic : public Vmm::Mmio_device
|
||||
public:
|
||||
|
||||
Irq & irq(unsigned num);
|
||||
void handle_irq(State &state);
|
||||
bool pending_irq(State &state);
|
||||
static void setup_state(State &state);
|
||||
void handle_irq(Vcpu_state &state);
|
||||
bool pending_irq(Vcpu_state &state);
|
||||
static void setup_state(Vcpu_state &state);
|
||||
|
||||
Gicd_banked(Cpu_base & cpu, Gic & gic, Mmio_bus & bus);
|
||||
|
||||
|
@ -80,7 +80,7 @@ void Mmio_device::write(Address_range & access, Cpu & cpu, Register value)
|
||||
void Mmio_device::add(Mmio_register & reg) { _registers.add(reg); }
|
||||
|
||||
|
||||
void Vmm::Mmio_bus::handle_memory_access(State &state, Vmm::Cpu &cpu)
|
||||
void Vmm::Mmio_bus::handle_memory_access(Vcpu_state &state, Vmm::Cpu &cpu)
|
||||
{
|
||||
using namespace Genode;
|
||||
|
||||
|
@ -100,7 +100,7 @@ class Vmm::Mmio_device : public Vmm::Address_range
|
||||
|
||||
struct Vmm::Mmio_bus : Vmm::Address_space
|
||||
{
|
||||
void handle_memory_access(State &state, Cpu &cpu);
|
||||
void handle_memory_access(Vcpu_state &state, Cpu &cpu);
|
||||
};
|
||||
|
||||
#endif /* _SRC__SERVER__VMM__MMIO_H_ */
|
||||
|
@ -21,7 +21,7 @@ using Vmm::Cpu;
|
||||
using Vmm::Gic;
|
||||
using namespace Genode;
|
||||
|
||||
addr_t Vmm::State::reg(addr_t idx) const
|
||||
addr_t Vmm::Vcpu_state::reg(addr_t idx) const
|
||||
{
|
||||
if (idx > 15) return 0;
|
||||
|
||||
@ -31,7 +31,7 @@ addr_t Vmm::State::reg(addr_t idx) const
|
||||
}
|
||||
|
||||
|
||||
void Vmm::State::reg(addr_t idx, addr_t v)
|
||||
void Vmm::Vcpu_state::reg(addr_t idx, addr_t v)
|
||||
{
|
||||
if (idx > 15) return;
|
||||
|
||||
@ -64,13 +64,13 @@ Cpu_base::System_register::Iss::mask_encoding(access_t v)
|
||||
}
|
||||
|
||||
|
||||
void Cpu_base::_handle_brk(State &)
|
||||
void Cpu_base::_handle_brk(Vcpu_state &)
|
||||
{
|
||||
error(__func__, " not implemented yet");
|
||||
}
|
||||
|
||||
|
||||
void Cpu_base::handle_exception(State & state)
|
||||
void Cpu_base::handle_exception(Vcpu_state & state)
|
||||
{
|
||||
/* check exception reason */
|
||||
switch (state.cpu_exception) {
|
||||
@ -87,7 +87,7 @@ void Cpu_base::handle_exception(State & state)
|
||||
}
|
||||
|
||||
|
||||
void Cpu_base::dump(State &state)
|
||||
void Cpu_base::dump(Vcpu_state &state)
|
||||
{
|
||||
auto lambda = [] (unsigned i) {
|
||||
switch (i) {
|
||||
@ -109,7 +109,7 @@ void Cpu_base::dump(State &state)
|
||||
log(" lr = ", Hex(state.lr, Hex::PREFIX, Hex::PAD));
|
||||
log(" ip = ", Hex(state.ip, Hex::PREFIX, Hex::PAD));
|
||||
log(" cpsr = ", Hex(state.cpsr, Hex::PREFIX, Hex::PAD));
|
||||
for (unsigned i = 0; i < State::Mode_state::MAX; i++) {
|
||||
for (unsigned i = 0; i < Vcpu_state::Mode_state::MAX; i++) {
|
||||
log(" sp_", lambda(i), " = ",
|
||||
Hex(state.mode[i].sp, Hex::PREFIX, Hex::PAD));
|
||||
log(" lr_", lambda(i), " = ",
|
||||
@ -129,7 +129,7 @@ void Cpu_base::dump(State &state)
|
||||
}
|
||||
|
||||
|
||||
void Cpu_base::initialize_boot(State &state, addr_t ip, addr_t dtb)
|
||||
void Cpu_base::initialize_boot(Vcpu_state &state, addr_t ip, addr_t dtb)
|
||||
{
|
||||
state.reg(1, 0xffffffff); /* invalid machine type */
|
||||
state.reg(2, dtb);
|
||||
@ -156,7 +156,7 @@ addr_t Cpu::Ccsidr::read() const
|
||||
return 0;
|
||||
}
|
||||
|
||||
void Cpu::setup_state(State &state)
|
||||
void Cpu::setup_state(Vcpu_state &state)
|
||||
{
|
||||
state.cpsr = 0x93; /* el1 mode and IRQs disabled */
|
||||
state.sctrl = 0xc50078;
|
||||
|
@ -44,7 +44,7 @@ class Vmm::Cpu : public Vmm::Cpu_base
|
||||
TRAP,
|
||||
};
|
||||
|
||||
void setup_state(State & state) override;
|
||||
void setup_state(Vcpu_state & state) override;
|
||||
|
||||
private:
|
||||
|
||||
|
@ -21,14 +21,14 @@ using Vmm::Cpu;
|
||||
using Vmm::Gic;
|
||||
using namespace Genode;
|
||||
|
||||
addr_t Vmm::State::reg(addr_t idx) const
|
||||
addr_t Vmm::Vcpu_state::reg(addr_t idx) const
|
||||
{
|
||||
if (idx > 30) return 0;
|
||||
return r[idx];
|
||||
}
|
||||
|
||||
|
||||
void Vmm::State::reg(addr_t idx, addr_t v)
|
||||
void Vmm::Vcpu_state::reg(addr_t idx, addr_t v)
|
||||
{
|
||||
if (idx > 30) return;
|
||||
r[idx] = v;
|
||||
@ -60,7 +60,7 @@ Cpu_base::System_register::Iss::mask_encoding(access_t v)
|
||||
}
|
||||
|
||||
|
||||
void Cpu_base::_handle_brk(State & state)
|
||||
void Cpu_base::_handle_brk(Vcpu_state & state)
|
||||
{
|
||||
addr_t offset = 0x0;
|
||||
if (!(state.pstate & 0b100)) {
|
||||
@ -78,7 +78,7 @@ void Cpu_base::_handle_brk(State & state)
|
||||
}
|
||||
|
||||
|
||||
void Cpu_base::handle_exception(State &state)
|
||||
void Cpu_base::handle_exception(Vcpu_state &state)
|
||||
{
|
||||
/* check exception reason */
|
||||
switch (state.exception_type) {
|
||||
@ -94,7 +94,7 @@ void Cpu_base::handle_exception(State &state)
|
||||
}
|
||||
|
||||
|
||||
void Cpu_base::dump(State &state)
|
||||
void Cpu_base::dump(Vcpu_state &state)
|
||||
{
|
||||
auto lambda = [] (addr_t exc) {
|
||||
switch (exc) {
|
||||
@ -129,7 +129,7 @@ void Cpu_base::dump(State &state)
|
||||
|
||||
addr_t Cpu::Ccsidr::read() const
|
||||
{
|
||||
State & state = cpu.state();
|
||||
Vcpu_state & state = cpu.state();
|
||||
|
||||
struct Clidr : Genode::Register<32>
|
||||
{
|
||||
@ -203,14 +203,14 @@ void Cpu::Icc_sgi1r_el1::write(addr_t v)
|
||||
};
|
||||
|
||||
|
||||
void Cpu_base::initialize_boot(State &state, addr_t ip, addr_t dtb)
|
||||
void Cpu_base::initialize_boot(Vcpu_state &state, addr_t ip, addr_t dtb)
|
||||
{
|
||||
state.reg(0, dtb);
|
||||
state.ip = ip;
|
||||
}
|
||||
|
||||
|
||||
void Cpu::setup_state(State &state)
|
||||
void Cpu::setup_state(Vcpu_state &state)
|
||||
{
|
||||
_sr_id_aa64isar0_el1.write(state.id_aa64isar0_el1);
|
||||
_sr_id_aa64isar1_el1.write(state.id_aa64isar1_el1);
|
||||
|
@ -44,7 +44,7 @@ class Vmm::Cpu : public Vmm::Cpu_base
|
||||
NO_EXCEPTION = 0xffff,
|
||||
};
|
||||
|
||||
void setup_state(State & state) override;
|
||||
void setup_state(Vcpu_state & state) override;
|
||||
|
||||
private:
|
||||
|
||||
|
@ -17,10 +17,9 @@
|
||||
#include <cpu/vcpu_state_virtualization.h>
|
||||
|
||||
using Genode::addr_t;
|
||||
using Genode::Vcpu_state;
|
||||
|
||||
namespace Vmm {
|
||||
struct State : Genode::Vcpu_state
|
||||
struct Vcpu_state : Genode::Vcpu_state
|
||||
{
|
||||
addr_t reg(addr_t idx) const;
|
||||
void reg(addr_t idx, addr_t v);
|
||||
|
Loading…
x
Reference in New Issue
Block a user