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hw: remove kernel unit test framework (fix #2096)

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* Remove 'test' routine from kernel/core
* Move 'cpu_scheduler' and 'double_list' test to user-land
* Remove 'hw_info' target at all (can be recycled in a topic branch)
This commit is contained in:
Stefan Kalkowski 2016-09-13 11:01:15 +02:00 committed by Christian Helmuth
parent 4d7d4dd2fc
commit 4bd5634bd5
18 changed files with 117 additions and 652 deletions
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11
repos/base-hw/lib/mk/spec/panda/test-hw_info.mk
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@ -1,11 +0,0 @@
#
# \brief Build config for a core that prints hardware information
# \author Martin Stein
# \date 2011-12-16
#
# add C++ sources
SRC_CC += spec/arm_v7/info.cc
# decrlare source directories
vpath % $(REP_DIR)/src/test/hw_info

12
repos/base-hw/lib/mk/spec/zynq/test-hw_info.mk
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@ -1,12 +0,0 @@
#
# \brief Build config for a core that prints hardware information
# \author Johannes Schlatow
# \author Martin Stein
# \date 2011-12-16
#
# add C++ sources
SRC_CC += spec/arm_v7/info.cc
# decrlare source directories
vpath % $(REP_DIR)/src/test/hw_info

23
repos/base-hw/run/cpu_scheduler.run
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@ -5,17 +5,28 @@
#
# build program images
build "test/cpu_scheduler"
build "core init test/cpu_scheduler"
# create directory where the boot files are written to
create_boot_directory
# the init config is not used but the build system needs it
install_config {<dummy/>}
install_config {
<config>
<parent-provides>
<service name="LOG"/>
<service name="RM"/>
</parent-provides>
<default-route>
<any-service> <parent/> </any-service>
</default-route>
<start name="test-cpu_scheduler">
<resource name="RAM" quantum="10M"/>
</start>
</config>}
# create single boot image from the compiled program images
set core_test 1
build_boot_image "test-cpu_scheduler"
build_boot_image "core init test-cpu_scheduler"
# configure qemu to use 64 MB RAM and avoid GUI mode
append qemu_args " -m 64 -nographic"
@ -24,5 +35,5 @@ append qemu_args " -m 64 -nographic"
run_genode_until "done.*\n" 10
# check the output
grep_output {\[test\]}
compare_output_to { [test] done }
grep_output {\[init -> test-cpu_scheduler\]}
compare_output_to { [init -> test-cpu_scheduler] done }

53
repos/base-hw/run/double_list.run
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@ -5,17 +5,29 @@
#
# build program images
build "test/double_list"
build "core init test/double_list"
# create directory where the boot files are written to
create_boot_directory
# the init config is not used but the build system needs it
install_config {<dummy/>}
install_config {
<config>
<parent-provides>
<service name="LOG"/>
<service name="RM"/>
</parent-provides>
<default-route>
<any-service> <parent/> </any-service>
</default-route>
<start name="test-double_list">
<resource name="RAM" quantum="10M"/>
</start>
</config>
}
# create single boot image from the compiled program images
set core_test 1
build_boot_image "test-double_list"
build_boot_image "core init test-double_list"
# configure qemu to use 64 MB RAM and avoid GUI mode
append qemu_args " -m 64 -nographic"
@ -24,12 +36,31 @@ append qemu_args " -m 64 -nographic"
run_genode_until "done.*\n" 10
# check the output
grep_output {\[test\]}
grep_output {\[init -> test-double_list\]}
compare_output_to {
[test] print each
[test] print each 1
[test] print each 3 2 5 7 6 4 1
[test] print each 8 9 2 5 1 7 6 4 3
[test] print each 7 8
[test] done
[init -> test-double_list] print each
[init -> test-double_list] print each
[init -> test-double_list] 1
[init -> test-double_list] print each
[init -> test-double_list] 3
[init -> test-double_list] 2
[init -> test-double_list] 5
[init -> test-double_list] 7
[init -> test-double_list] 6
[init -> test-double_list] 4
[init -> test-double_list] 1
[init -> test-double_list] print each
[init -> test-double_list] 8
[init -> test-double_list] 9
[init -> test-double_list] 2
[init -> test-double_list] 5
[init -> test-double_list] 1
[init -> test-double_list] 7
[init -> test-double_list] 6
[init -> test-double_list] 4
[init -> test-double_list] 3
[init -> test-double_list] print each
[init -> test-double_list] 7
[init -> test-double_list] 8
[init -> test-double_list] done
}

24
repos/base-hw/run/hw_info.run
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@ -1,24 +0,0 @@
#
# \brief Print some useful information on the underlying hardware
# \author Martin Stein
# \date 2014-10-21
#
# build program images
build "test/hw_info"
# create directory where the boot files are written to
create_boot_directory
# the init config is not used but the build system needs it
install_config {<dummy/>}
# create single boot image from the compiled program images
set core_test 1
build_boot_image "test-hw_info"
# configure qemu to use 64 MB RAM and avoid GUI mode
append qemu_args " -m 64 -nographic"
# execute the test in qemu if the targeted platform is supported
run_genode_until "------ End ------.*\n" 60

26
repos/base-hw/src/core/include/kernel/test.h
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@ -1,26 +0,0 @@
/*
* \brief Automated testing of kernel internals
* \author Stefan Kalkowski
* \author Martin Stein
* \date 2015-05-21
*/
/*
* Copyright (C) 2015 Genode Labs GmbH
*
* This file is part of the Genode OS framework, which is distributed
* under the terms of the GNU General Public License version 2.
*/
#ifndef _KERNEL__TEST_H_
#define _KERNEL__TEST_H_
namespace Kernel {
/**
* Hook that enables automated testing of kernel internals
*/
void test();
}
#endif /* _KERNEL__TEST_H_ */

3
repos/base-hw/src/core/kernel/init.cc
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@ -15,7 +15,6 @@
/* core includes */
#include <kernel/pd.h>
#include <kernel/kernel.h>
#include <kernel/test.h>
#include <platform_pd.h>
#include <pic.h>
#include <board.h>
@ -62,7 +61,5 @@ extern "C" void init_kernel()
Genode::printf("\nkernel initialized\n");
test();
kernel();
}

7
repos/base-hw/src/core/kernel/test.cc
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@ -1,7 +0,0 @@
/*
* \brief Dummy implementation of kernel-internal test
* \author Martin Stein
* \date 2014-09-30
*/
namespace Kernel { void test() { } }

13
repos/base-hw/src/core/target.mk
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@ -11,9 +11,6 @@ TARGET = core
# library that provides the whole configuration
LIBS += core
# add C++ sources
SRC_CC += kernel/test.cc
#
# On RISCV we need a link address for core that differs from that of the other
# components.
@ -21,3 +18,13 @@ SRC_CC += kernel/test.cc
ifneq ($(filter riscv, $(SPECS)),)
LD_TEXT_ADDR = $(CORE_LD_TEXT_ADDR)
endif
#
# We do not have additional source files than the core library
# so we need to define a dummy compilation unit,
# otherwise our build-system won't link
#
SRC_C += dummy.cc
dummy.cc:
$(VERBOSE)touch $@

16
repos/base-hw/src/test/cpu_scheduler/target.mk
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@ -4,14 +4,10 @@
# \date 2011-12-16
#
# set target name that this configuration applies to
TARGET = test-cpu_scheduler
TARGET = test-cpu_scheduler
SRC_CC = test.cc cpu_scheduler.cc double_list.cc
INC_DIR = $(REP_DIR)/src/core/include $(BASE_DIR)/src/include
LIBS = base
# library that provides the whole configuration
LIBS += core
# add C++ sources
SRC_CC += kernel/test.cc
# allow the test to use base-internal headers, i.e., page_size.h
INC_DIR += $(BASE_DIR)/src/include
vpath test.cc $(PRG_DIR)
vpath %.cc $(REP_DIR)/src/core/kernel

15
repos/base-hw/src/test/cpu_scheduler/kernel/test.cc → repos/base-hw/src/test/cpu_scheduler/test.cc
View File

@ -11,9 +11,10 @@
* under the terms of the GNU General Public License version 2.
*/
#include <base/component.h>
/* core includes */
#include <kernel/cpu_scheduler.h>
#include <kernel/test.h>
/*
* Utilities
@ -43,7 +44,7 @@ Data * data()
void done()
{
Genode::printf("[test] done\n");
Genode::log("done");
while (1) ;
}
@ -100,18 +101,18 @@ void update_check(unsigned const l, unsigned const c, unsigned const t,
data()->scheduler.update(c);
unsigned const st = time();
if (t != st) {
Genode::printf("[test] wrong time %u in line %u\n", st, l);
Genode::log("wrong time ", st, " in line ", l);
done();
}
Cpu_share * const hs = data()->scheduler.head();
unsigned const hq = data()->scheduler.head_quota();
if (hs != share(s)) {
unsigned const hi = share_id(hs);
Genode::printf("[test] wrong share %u in line %u\n", hi, l);
Genode::log("wrong share ", hi, " in line ", l);
done();
}
if (hq != q) {
Genode::printf("[test] wrong quota %u in line %u\n", hq, l);
Genode::log("wrong quota ", hq, " in line ", l);
done();
}
}
@ -120,7 +121,7 @@ void ready_check(unsigned const l, unsigned const s, bool const x)
{
bool const y = data()->scheduler.ready_check(share(s));
if (y != x) {
Genode::printf("[test] wrong check result %u in line %u\n", y, l);
Genode::log("wrong check result ", y, " in line ", l);
done();
}
}
@ -144,7 +145,7 @@ void ready_check(unsigned const l, unsigned const s, bool const x)
/**
* Main routine
*/
void Kernel::test()
void Component::construct(Genode::Env &)
{
/*
* Step-by-step testing

12
repos/base-hw/src/test/double_list/target.mk
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@ -4,11 +4,9 @@
# \date 2011-12-16
#
# set target name that this configuration applies to
TARGET = test-double_list
TARGET = test-double_list
INC_DIR = $(REP_DIR)/src/core/include
SRC_CC = test.cc double_list.cc
LIBS = base
# library that provides the whole configuration
LIBS += core
# add C++ sources
SRC_CC += kernel/test.cc
vpath double_list.cc $(REP_DIR)/src/core/kernel

20
repos/base-hw/src/test/double_list/kernel/test.cc → repos/base-hw/src/test/double_list/test.cc
View File

@ -12,12 +12,11 @@
*/
/* base includes */
#include <base/stdint.h>
#include <base/printf.h>
#include <base/component.h>
#include <base/log.h>
/* core includes */
#include <kernel/double_list.h>
#include <kernel/test.h>
/*
@ -38,7 +37,7 @@ struct Item : Item_load, Double_list_item
Item(unsigned const id) : _id(id) { x = 1; y = 2; z = 3; }
void iteration() { Genode::printf(" %u", _id); }
void iteration() { Genode::log(_id); }
};
struct Data
@ -63,7 +62,7 @@ Data * data()
void done()
{
Genode::printf("[test] done\n");
Genode::log("done");
while (1) ;
}
@ -72,22 +71,21 @@ void check(unsigned i1, unsigned l)
Item * const i2 = data()->list.head();
if (i1 && i2) {
if(i1 == i2->_id) { return; }
Genode::printf("[test] head %u in line %u\n", i2->_id, l);
Genode::log("head ", i2->_id, " in line ", l);
done();
} else if (i1 && !i2) {
Genode::printf("[test] empty in line %u\n", l);
Genode::log("empty in line ", l);
done();
} else if (!i1 && i2){
Genode::printf("[test] non-empty %u in line %u\n", i2->_id, l);
Genode::log("non-empty ", i2->_id, " in line ", l);
done();
}
}
void print_each()
{
Genode::printf("[test] print each");
Genode::log("print each");
data()->list.for_each([] (Item * const i) { i->iteration(); });
Genode::printf("\n");
}
Item * item(unsigned const i) {
@ -110,7 +108,7 @@ Item * item(unsigned const i) {
/**
* Main routine
*/
void Kernel::test()
void Component::construct(Genode::Env &)
{
/*
* Step-by-step testing

33
repos/base-hw/src/test/hw_info/kernel/test.cc
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@ -1,33 +0,0 @@
/*
* \brief Provide detailed hardware Information
* \author Martin Stein
* \date 2014-10-20
*/
/*
* Copyright (C) 2014 Genode Labs GmbH
*
* This file is part of the Genode OS framework, which is distributed
* under the terms of the GNU General Public License version 2.
*/
/* base includes */
#include <base/printf.h>
/* core includes */
#include <kernel/test.h>
using namespace Genode;
void info();
/**
* Main routine
*/
void Kernel::test()
{
printf("\n");
info();
printf("------ End ------\n");
while (1) ;
}

427
repos/base-hw/src/test/hw_info/spec/arm_v7/info.cc
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@ -1,427 +0,0 @@
/*
* \brief Provide detailed hardware Information
* \author Martin Stein
* \date 2014-10-20
*/
/*
* Copyright (C) 2014 Genode Labs GmbH
*
* This file is part of the Genode OS framework, which is distributed
* under the terms of the GNU General Public License version 2.
*/
/* base includes */
#include <util/register.h>
#include <base/printf.h>
using namespace Genode;
struct Reg_32_8: Register<32>
{
struct B0 : Bitfield<0,4> { };
struct B1 : Bitfield<4,4> { };
struct B2 : Bitfield<8,4> { };
struct B3 : Bitfield<12,4> { };
struct B4 : Bitfield<16,4> { };
struct B5 : Bitfield<20,4> { };
struct B6 : Bitfield<24,4> { };
struct B7 : Bitfield<28,4> { };
};
struct Id_pfr1 : Reg_32_8
{
static access_t read()
{
access_t v;
asm volatile ("mrc p15, 0, %0, c0, c1, 1" : "=r" (v) :: );
return v;
}
};
struct Id_mmfr0 : Reg_32_8
{
static access_t read()
{
access_t v;
asm volatile ("mrc p15, 0, %0, c0, c1, 4" : "=r" (v) :: );
return v;
}
};
struct Id_mmfr1 : Reg_32_8
{
static access_t read()
{
access_t v;
asm volatile ("mrc p15, 0, %0, c0, c1, 5" : "=r" (v) :: );
return v;
}
};
struct Id_mmfr2 : Reg_32_8
{
static access_t read()
{
access_t v;
asm volatile ("mrc p15, 0, %0, c0, c1, 6" : "=r" (v) :: );
return v;
}
};
struct Id_mmfr3 : Reg_32_8
{
static access_t read()
{
access_t v;
asm volatile ("mrc p15, 0, %0, c0, c1, 7" : "=r" (v) :: );
return v;
}
};
struct Id_pfr0 : Reg_32_8
{
static access_t read()
{
access_t v;
asm volatile ("mrc p15, 0, %0, c0, c1, 0" : "=r" (v) :: );
return v;
}
};
struct Ctr : Register<32>
{
struct Iminline : Bitfield<0,4> { };
struct L1ip : Bitfield<14,2> { };
struct Dminline : Bitfield<16,4> { };
struct Erg : Bitfield<20,4> { };
struct Cgw : Bitfield<24,4> { };
static access_t read()
{
access_t v;
asm volatile ("mrc p15, 0, %0, c0, c0, 1" : "=r" (v) :: );
return v;
}
};
struct Ccsidr : Register<32>
{
struct Line_size : Bitfield<0,3> { };
struct Associativity : Bitfield<3,10> { };
struct Num_sets : Bitfield<13,15> { };
struct Wa : Bitfield<28,1> { };
struct Ra : Bitfield<29,1> { };
struct Wb : Bitfield<30,1> { };
struct Wt : Bitfield<31,1> { };
static access_t read()
{
access_t v;
asm volatile ("mrc p15, 1, %0, c0, c0, 0" : "=r" (v) :: );
return v;
}
};
struct Clidr : Register<32>
{
struct Ctype1 : Bitfield<0,3> { };
struct Ctype2 : Bitfield<3,3> { };
struct Ctype3 : Bitfield<6,3> { };
struct Ctype4 : Bitfield<9,3> { };
struct Ctype5 : Bitfield<12,3> { };
struct Ctype6 : Bitfield<15,3> { };
struct Ctype7 : Bitfield<18,3> { };
struct Louis : Bitfield<21,3> { };
struct Loc : Bitfield<24,3> { };
struct Louu : Bitfield<27,3> { };
static access_t read()
{
access_t v;
asm volatile ("mrc p15, 1, %0, c0, c0, 1" : "=r" (v) :: );
return v;
}
};
struct Fpsid : Register<32>
{
struct Revision : Bitfield<0,4> { };
struct Variant : Bitfield<4,4> { };
struct Part_number : Bitfield<8,8> { };
struct Subarchitecture : Bitfield<16,7> { };
struct Sw : Bitfield<23,1> { };
struct Implementer : Bitfield<24,8> { };
static access_t read()
{
access_t v;
asm volatile ("mrc p10, 7, %0, cr0, cr0" : "=r" (v) :: );
return v;
}
};
struct Mvfr0 : Reg_32_8
{
static access_t read()
{
access_t v;
asm volatile("mrc p10, 7, %0, cr7, cr0" : "=r" (v) :: );
return v;
}
};
struct Mvfr1 : Reg_32_8
{
static access_t read()
{
access_t v;
asm volatile("mrc p10, 7, %0, cr6, cr0" : "=r" (v));
return v;
}
};
struct Mpidr : Register<32>
{
struct Mp : Bitfield<31,1> { };
static access_t read()
{
access_t v;
asm volatile ("mrc p15, 0, %0, c0, c0, 5" : "=r" (v) :: );
return v;
}
};
struct Tlbtr : Register<32>
{
struct Nu : Bitfield<0,1> { };
static access_t read()
{
access_t v;
asm volatile ("mrc p15, 0, %0, c0, c0, 3" : "=r" (v) :: );
return v;
}
};
struct Midr : Register<32>
{
struct Revision : Bitfield<0,4> { };
struct Primary_part_number : Bitfield<4,12> { };
struct Architecture : Bitfield<16,4> { };
struct Variant : Bitfield<20,4> { };
struct Implementer : Bitfield<24,8> { };
static access_t read()
{
access_t v;
asm volatile ("mrc p15, 0, %0, c0, c0, 0" : "=r" (v) :: );
return v;
}
};
struct Csselr : Register<32>
{
struct Ind : Bitfield<0,1> { };
struct Level : Bitfield<1,3> { };
static access_t read()
{
access_t v;
asm volatile ("mrc p15, 2, %0, c0, c0, 0" : "=r" (v) :: );
return v;
}
static void write(access_t const v) {
asm volatile ("mcr p15, 2, %0, c0, c0, 0" :: "r" (v) : ); }
};
void info_ccsidr()
{
printf(" Cache Size Identification Register for L%u %s:\n", Csselr::Level::get(Csselr::read()) + 1, Csselr::Ind::get(Csselr::read()) ? "Instruction Cache" : "Data Cache");
printf(" Line size: 0x%x\n", Ccsidr::Line_size::get(Ccsidr::read()));
printf(" Associativity: 0x%x\n", Ccsidr::Associativity::get(Ccsidr::read()));
printf(" Number of Sets: 0x%x\n", Ccsidr::Num_sets::get(Ccsidr::read()));
printf(" Write-Allocation: 0x%x\n", Ccsidr::Wa::get(Ccsidr::read()));
printf(" Read-Allocation: 0x%x\n", Ccsidr::Ra::get(Ccsidr::read()));
printf(" Write-Back: 0x%x\n", Ccsidr::Wb::get(Ccsidr::read()));
printf(" Write-Through: 0x%x\n", Ccsidr::Wt::get(Ccsidr::read()));
printf(" \n");
}
void info_ccsidr_level(unsigned const l, Clidr::access_t const t)
{
Csselr::access_t s = 0;
Csselr::Level::set(s, l - 1);
if (t & 1) { Csselr::Ind::set(s, 1); Csselr::write(s); info_ccsidr(); }
if (t & 2) { Csselr::Ind::set(s, 0); Csselr::write(s); info_ccsidr(); }
}
void info()
{
/*
* Processor
*/
printf("------ ARMv7 processor ------\n");
printf("\n");
printf(" Main Identification Register:\n");
printf(" Revision: %u\n", Midr::Revision::get(Midr::read()));
printf(" Primary Part number: %u\n", Midr::Primary_part_number::get(Midr::read()));
printf(" Architecture: %u\n", Midr::Architecture::get(Midr::read()));
printf(" Variant: %u\n", Midr::Variant::get(Midr::read()));
printf(" Implementer: %c\n", Midr::Implementer::get(Midr::read()));
printf(" \n");
printf(" Multiprocessor Identification Register 0:\n");
printf(" Multiprocessor: %u\n", Mpidr::Mp::get(Mpidr::read()));
printf(" \n");
printf(" Processor feature register 0:\n");
printf(" ARM instruction set support: 0x%x\n", Id_pfr0::B0::get(Id_pfr0::read()));
printf(" Thumb instruction set support: 0x%x\n", Id_pfr0::B1::get(Id_pfr0::read()));
printf(" Jazelle extension support: 0x%x\n", Id_pfr0::B2::get(Id_pfr0::read()));
printf(" ThumbEE instruction set support: 0x%x\n", Id_pfr0::B3::get(Id_pfr0::read()));
printf(" \n");
printf(" Processor feature register 1:\n");
printf(" Programmers’ model: 0x%x\n", Id_pfr1::B0::get(Id_pfr1::read()));
printf(" Security Extensions: 0x%x\n", Id_pfr1::B1::get(Id_pfr1::read()));
printf(" M profile programmers model: 0x%x\n", Id_pfr1::B2::get(Id_pfr1::read()));
printf(" Virtualization Extensions: 0x%x\n", Id_pfr1::B3::get(Id_pfr1::read()));
printf(" Generic Timer Extension: 0x%x\n", Id_pfr1::B4::get(Id_pfr1::read()));
printf(" \n");
/*
* Memory Model
*/
printf("------ ARMv7 memory model ------\n");
printf("\n");
printf(" Memory model feature register 0:\n");
printf(" VMSA support: 0x%x\n", Id_mmfr0::B0::get(Id_mmfr0::read()));
printf(" PMSA support: 0x%x\n", Id_mmfr0::B1::get(Id_mmfr0::read()));
printf(" Outermost shareability: 0x%x\n", Id_mmfr0::B2::get(Id_mmfr0::read()));
printf(" Shareability levels: 0x%x\n", Id_mmfr0::B3::get(Id_mmfr0::read()));
printf(" TCM support: 0x%x\n", Id_mmfr0::B4::get(Id_mmfr0::read()));
printf(" Auxiliary registers: 0x%x\n", Id_mmfr0::B5::get(Id_mmfr0::read()));
printf(" FCSE support: 0x%x\n", Id_mmfr0::B6::get(Id_mmfr0::read()));
printf(" Innermost shareability: 0x%x\n", Id_mmfr0::B7::get(Id_mmfr0::read()));
printf(" \n");
printf(" Memory model feature register 1:\n");
printf(" L1 Harvard cache VA: 0x%x\n", Id_mmfr1::B0::get(Id_mmfr1::read()));
printf(" L1 unified cache VA: 0x%x\n", Id_mmfr1::B1::get(Id_mmfr1::read()));
printf(" L1 Harvard cache set/way: 0x%x\n", Id_mmfr1::B2::get(Id_mmfr1::read()));
printf(" L1 unified cache set/way: 0x%x\n", Id_mmfr1::B3::get(Id_mmfr1::read()));
printf(" L1 Harvard cache: 0x%x\n", Id_mmfr1::B4::get(Id_mmfr1::read()));
printf(" L1 unified cache: 0x%x\n", Id_mmfr1::B5::get(Id_mmfr1::read()));
printf(" L1 cache test and clean: 0x%x\n", Id_mmfr1::B6::get(Id_mmfr1::read()));
printf(" Branch predictor: 0x%x\n", Id_mmfr1::B7::get(Id_mmfr1::read()));
printf(" \n");
printf(" Memory model feature register 2:\n");
printf(" L1 Harvard fg fetch: 0x%x\n", Id_mmfr2::B0::get(Id_mmfr2::read()));
printf(" L1 Harvard bg fetch: 0x%x\n", Id_mmfr2::B1::get(Id_mmfr2::read()));
printf(" L1 Harvard range: 0x%x\n", Id_mmfr2::B2::get(Id_mmfr2::read()));
printf(" Harvard TLB: 0x%x\n", Id_mmfr2::B3::get(Id_mmfr2::read()));
printf(" Unified TLB: 0x%x\n", Id_mmfr2::B4::get(Id_mmfr2::read()));
printf(" Mem barrier: 0x%x\n", Id_mmfr2::B5::get(Id_mmfr2::read()));
printf(" WFI stall: 0x%x\n", Id_mmfr2::B6::get(Id_mmfr2::read()));
printf(" HW Access flag: 0x%x\n", Id_mmfr2::B7::get(Id_mmfr2::read()));
printf(" \n");
printf(" Memory model feature register 3:\n");
printf(" Cache maintain MVA: 0x%x\n", Id_mmfr3::B0::get(Id_mmfr3::read()));
printf(" Cache maintain set/way: 0x%x\n", Id_mmfr3::B1::get(Id_mmfr3::read()));
printf(" BP maintain: 0x%x\n", Id_mmfr3::B2::get(Id_mmfr3::read()));
printf(" Maintenance broadcast: 0x%x\n", Id_mmfr3::B3::get(Id_mmfr3::read()));
printf(" Coherent walk: 0x%x\n", Id_mmfr3::B5::get(Id_mmfr3::read()));
printf(" Cached memory size: 0x%x\n", Id_mmfr3::B6::get(Id_mmfr3::read()));
printf(" Supersection support: 0x%x\n", Id_mmfr3::B7::get(Id_mmfr3::read()));
printf(" \n");
printf(" TLB Type Register:\n");
printf(" Unified TLB: %u\n", !Tlbtr::Nu::get(Tlbtr::read()));
printf(" \n");
/*
* Caches
*/
printf("------ ARMv7 caches ------\n");
printf("\n");
printf(" Cache Type Register:\n");
printf(" Instruction Cache Min Line: 0x%x\n", Ctr::Iminline::get(Ctr::read()));
printf(" Level 1 Instruction Cache Policy: 0x%x\n", Ctr::L1ip::get(Ctr::read()));
printf(" Data Cache Min Line: 0x%x\n", Ctr::Dminline::get(Ctr::read()));
printf(" Exclusives Reservation Granule: 0x%x\n", Ctr::Erg::get(Ctr::read()));
printf(" Cache Write-back Granule: 0x%x\n", Ctr::Cgw::get(Ctr::read()));
printf(" \n");
printf(" Cache Level Identification Register:\n");
printf(" Cache type 1: 0x%x\n", Clidr::Ctype1::get(Clidr::read()));
printf(" Cache type 2: 0x%x\n", Clidr::Ctype2::get(Clidr::read()));
printf(" Cache type 3: 0x%x\n", Clidr::Ctype3::get(Clidr::read()));
printf(" Cache type 4: 0x%x\n", Clidr::Ctype4::get(Clidr::read()));
printf(" Cache type 5: 0x%x\n", Clidr::Ctype5::get(Clidr::read()));
printf(" Cache type 6: 0x%x\n", Clidr::Ctype6::get(Clidr::read()));
printf(" Cache type 7: 0x%x\n", Clidr::Ctype7::get(Clidr::read()));
printf(" Level of Unification Inner Shareable: 0x%x\n", Clidr::Louis::get(Clidr::read()));
printf(" Level of Coherency: 0x%x\n", Clidr::Loc::get(Clidr::read()));
printf(" Level of Unification Uniprocessor: 0x%x\n", Clidr::Louu::get(Clidr::read()));
printf(" \n");
info_ccsidr_level(1, Clidr::Ctype1::get(Clidr::read()));
info_ccsidr_level(2, Clidr::Ctype2::get(Clidr::read()));
info_ccsidr_level(3, Clidr::Ctype3::get(Clidr::read()));
info_ccsidr_level(4, Clidr::Ctype4::get(Clidr::read()));
info_ccsidr_level(5, Clidr::Ctype5::get(Clidr::read()));
info_ccsidr_level(6, Clidr::Ctype6::get(Clidr::read()));
info_ccsidr_level(7, Clidr::Ctype7::get(Clidr::read()));
/*
* Advanced SIMD and Floating-point Extensions
*/
printf("------ ARMv7 advanced SIMD and floating-point extensions ------\n");
printf("\n");
printf(" Floating-point System Identification Register:\n");
printf(" Revision: %u\n", Fpsid::Revision::get(Fpsid::read()));
printf(" Variant: %u\n", Fpsid::Variant::get(Fpsid::read()));
printf(" Part number: %u\n", Fpsid::Part_number::get(Fpsid::read()));
printf(" Subarchitecture: %u\n", Fpsid::Subarchitecture::get(Fpsid::read()));
printf(" Software emulation: %u\n", Fpsid::Sw::get(Fpsid::read()));
printf(" Implementer: %c\n", Fpsid::Implementer::get(Fpsid::read()));
printf(" \n");
printf(" Media and VFP Feature Register 0:\n");
printf(" Advanced SIMD registers: 0x%x\n", Mvfr0::B0::get(Mvfr0::read()));
printf(" Single-precision: 0x%x\n", Mvfr0::B1::get(Mvfr0::read()));
printf(" Double-precision: 0x%x\n", Mvfr0::B2::get(Mvfr0::read()));
printf(" VFP exception trapping: 0x%x\n", Mvfr0::B3::get(Mvfr0::read()));
printf(" Divide: 0x%x\n", Mvfr0::B4::get(Mvfr0::read()));
printf(" Square root: 0x%x\n", Mvfr0::B5::get(Mvfr0::read()));
printf(" Short vectors: 0x%x\n", Mvfr0::B6::get(Mvfr0::read()));
printf(" VFP rounding modes: 0x%x\n", Mvfr0::B7::get(Mvfr0::read()));
printf(" \n");
printf(" Media and VFP Feature Register 1:\n");
printf(" Flush-to-Zero mode: 0x%x\n", Mvfr1::B0::get(Mvfr1::read()));
printf(" Default NaN mode: 0x%x\n", Mvfr1::B1::get(Mvfr1::read()));
printf(" Advanced SIMD load/store: 0x%x\n", Mvfr1::B2::get(Mvfr1::read()));
printf(" Advanced SIMD integer instructions: 0x%x\n", Mvfr1::B3::get(Mvfr1::read()));
printf(" Advanced SIMD single-precision FP: 0x%x\n", Mvfr1::B4::get(Mvfr1::read()));
printf(" Advanced SIMD half-precision FP: 0x%x\n", Mvfr1::B5::get(Mvfr1::read()));
printf(" VFP half-precision FP conversion: 0x%x\n", Mvfr1::B6::get(Mvfr1::read()));
printf(" Fused multiply accumulate: 0x%x\n", Mvfr1::B7::get(Mvfr1::read()));
printf(" \n");
}

14
repos/base-hw/src/test/hw_info/target.mk
View File

@ -1,14 +0,0 @@
#
# \brief Build config for a core that prints hardware information
# \author Martin Stein
# \date 2011-12-16
#
# set target name that this configuration applies to
TARGET = test-hw_info
# add library dependencies
LIBS += core test-hw_info
# add C++ sources
SRC_CC += kernel/test.cc

30
tool/run/boot_dir/hw
View File

@ -20,16 +20,6 @@ proc run_boot_string { } {
#
proc run_boot_dir {binaries} {
# adapt to wether this is a core-internal test or a common scenario
global core_test
if {[info exists core_test]} {
set core_bin "test-[run_name]"
set core_target "test/[run_name]"
} else {
set core_bin "core"
set core_target "core"
}
# generate static ACPI report for platform driver on Muen
if {[have_spec "hw_x86_64_muen"]} {
set fh [open "bin/acpi" "WRONLY CREAT TRUNC"]
@ -82,7 +72,7 @@ proc run_boot_dir {binaries} {
# generate header for each boot module except core
set i 1
foreach binary $binaries {
if {$binary == $core_bin} { continue }
if {$binary == "core"} { continue }
exec echo -e \
"\n${address_type} _boot_module_${i}_name" \
"\n${address_type} _boot_module_${i}_begin" \
@ -99,7 +89,7 @@ proc run_boot_dir {binaries} {
# generate name string for each module except core
set i 1
foreach binary $binaries {
if {$binary == $core_bin} { continue }
if {$binary == "core"} { continue }
exec echo -e \
"\n.p2align DATA_ACCESS_ALIGNM_LOG2" \
"\n_boot_module_${i}_name:" \
@ -117,7 +107,7 @@ proc run_boot_dir {binaries} {
# include raw data of modules consecutively but page aligned
set i 1
foreach binary $binaries {
if {$binary == $core_bin} { continue }
if {$binary == "core"} { continue }
exec echo -e \
"\n.p2align MIN_PAGE_SIZE_LOG2" \
"\n_boot_module_${i}_begin:" \
@ -135,10 +125,10 @@ proc run_boot_dir {binaries} {
exec ln -s $boot_modules boot_modules.s
# recompile core with boot modules
exec cp -L bin/$core_bin $core_target/$core_bin.standalone
exec find . -type f -name $core_bin -delete
exec cp -L bin/core core/core.standalone
exec find . -type f -name core -delete
set timeout 10000
set pid [eval "spawn make $core_target"]
set pid [eval "spawn make core"]
expect { eof { } }
if {[lindex [wait $pid] end] != 0} {
clean_boot_modules
@ -154,10 +144,10 @@ proc run_boot_dir {binaries} {
if {[have_spec "x86_64"]} {
# as startup is done in 32 bit mode, GRUB expects a 32 bit image
exec [cross_dev_prefix]objcopy -O elf32-i386 bin/$core_bin $elf_img
exec [cross_dev_prefix]objcopy -O elf32-i386 bin/core $elf_img
}
if {[expr [have_spec "arm"] || [have_spec "x86_32"] || [have_spec "riscv"]]} {
exec cp -L bin/$core_bin $elf_img
exec cp -L bin/core $elf_img
}
exec [cross_dev_prefix]strip $elf_img
@ -239,6 +229,6 @@ proc run_boot_dir {binaries} {
}
# retrieve stand-alone core
exec cp $core_target/$core_bin.standalone bin/$core_bin
exec rm $core_target/$core_bin.standalone
exec cp core/core.standalone bin/core
exec rm core/core.standalone
}

30
tool/run/boot_dir/sel4
View File

@ -24,16 +24,6 @@ proc run_boot_string { } {
#
proc run_boot_dir {binaries} {
# adapt to wether this is a core-internal test or a common scenario
global core_test
if {[info exists core_test]} {
set core_bin "test-$core_test"
set core_target "test/$core_test"
} else {
set core_bin "core"
set core_target "core"
}
# strip binaries
copy_and_strip_genode_binaries_to_run_dir $binaries
@ -83,7 +73,7 @@ proc run_boot_dir {binaries} {
# generate header for each boot module except core
set i 1
foreach binary $binaries {
if {$binary == $core_bin} { continue }
if {$binary == "core"} { continue }
exec echo -e \
"\n${address_type} _boot_module_${i}_name" \
"\n${address_type} _boot_module_${i}_begin" \
@ -100,7 +90,7 @@ proc run_boot_dir {binaries} {
# generate name string for each module except core
set i 1
foreach binary $binaries {
if {$binary == $core_bin} { continue }
if {$binary == "core"} { continue }
exec echo -e \
"\n.p2align DATA_ACCESS_ALIGNM_LOG2" \
"\n_boot_module_${i}_name:" \
@ -118,7 +108,7 @@ proc run_boot_dir {binaries} {
# include raw data of modules consecutively but page aligned
set i 1
foreach binary $binaries {
if {$binary == $core_bin} { continue }
if {$binary == "core"} { continue }
exec echo -e \
"\n.p2align MIN_PAGE_SIZE_LOG2" \
"\n_boot_module_${i}_begin:" \
@ -136,10 +126,10 @@ proc run_boot_dir {binaries} {
exec ln -s $boot_modules boot_modules.s
# recompile core with boot modules
exec cp -L bin/$core_bin $core_target/$core_bin.standalone
exec find . -type f -name $core_bin -delete
exec cp -L bin/core core/core.standalone
exec find . -type f -name core -delete
set timeout 10000
set pid [eval "spawn make $core_target"]
set pid [eval "spawn make core"]
expect { eof { } }
if {[lindex [wait $pid] end] != 0} {
clean_boot_modules
@ -153,10 +143,10 @@ proc run_boot_dir {binaries} {
set elf_img "[run_dir]/image.elf"
if {[have_spec "x86_64"]} {
# as startup is done in 32 bit mode, GRUB expects a 32 bit image
exec [cross_dev_prefix]objcopy -O elf32-i386 bin/$core_bin $elf_img
exec [cross_dev_prefix]objcopy -O elf32-i386 bin/core $elf_img
}
if {[expr [have_spec "arm"] || [have_spec "x86_32"]]} {
exec cp -L bin/$core_bin $elf_img
exec cp -L bin/core $elf_img
}
exec [cross_dev_prefix]strip $elf_img
@ -207,6 +197,6 @@ proc run_boot_dir {binaries} {
}
# retrieve stand-alone core
exec cp $core_target/$core_bin.standalone bin/$core_bin
exec rm $core_target/$core_bin.standalone
exec cp core/core.standalone bin/core
exec rm core/core.standalone
}