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Simple driver for the PL390 Interrupt controller
This commit is contained in:
Martin Stein
Christian Helmuth
parent
dce09679bc
commit
45b4cb5bbf
308
base/include/drivers/pic/pl390_base.h
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308
base/include/drivers/pic/pl390_base.h
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/*
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* \brief Base driver for the ARM PL390 interrupt controller
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* \author Martin stein
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* \date 2011-10-26
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*/
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/*
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* Copyright (C) 2009-2012 Genode Labs GmbH
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*
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* This file is part of the Genode OS framework, which is distributed
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* under the terms of the GNU General Public License version 2.
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*/
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#ifndef _BASE__INCLUDE__DRIVERS__PIC__PL390_BASE_H_
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#define _BASE__INCLUDE__DRIVERS__PIC__PL390_BASE_H_
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/* Genode includes */
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#include <util/mmio.h>
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#include <base/printf.h>
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namespace Genode
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{
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/**
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* Base driver for the ARM PL390 interrupt controller
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*/
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class Pl390_base
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{
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public:
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enum { MAX_INTERRUPT_ID = 1023 };
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protected:
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enum {
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MIN_SPI = 32,
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SPURIOUS_ID = 1023,
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};
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/**
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* Distributor interface
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*/
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struct Distr : public Mmio
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{
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Distr(addr_t const base) : Mmio(base) { }
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/**
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* Distributor control register
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*/
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struct Icddcr : Register<0x000, 32>
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{
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struct Enable : Bitfield<0,1> { };
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};
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/**
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* Interrupt controller type register
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*/
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struct Icdictr : Register<0x004, 32>
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{
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struct It_lines_number : Bitfield<0,5> { };
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struct Cpu_number : Bitfield<5,3> { };
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};
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/**
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* Interrupt set enable registers
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*/
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struct Icdiser : Register_array<0x100, 32, MAX_INTERRUPT_ID+1, 1, true>
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{
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struct Set_enable : Bitfield<0, 1> { };
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};
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/**
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* Interrupt clear enable registers
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*/
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struct Icdicer : Register_array<0x180, 32, MAX_INTERRUPT_ID+1, 1, true>
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{
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struct Clear_enable : Bitfield<0, 1> { };
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};
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/**
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* Interrupt priority level registers
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*/
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struct Icdipr : Register_array<0x400, 32, MAX_INTERRUPT_ID+1, 8>
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{
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struct Priority : Bitfield<0, 8>
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{
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enum { GET_MIN_PRIORITY = 0xff };
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};
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};
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/**
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* Interrupt processor target registers
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*/
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struct Icdiptr : Register_array<0x800, 32, MAX_INTERRUPT_ID+1, 8>
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{
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struct Cpu_targets : Bitfield<0, 8>
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{
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enum { ALL = 0xff };
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};
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};
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/**
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* Interrupt configuration registers
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*/
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struct Icdicr : Register_array<0xc00, 32, MAX_INTERRUPT_ID+1, 2>
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{
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struct Edge_triggered : Bitfield<1, 1> { };
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};
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/**
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* Minimum supported interrupt priority
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*/
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Icdipr::access_t min_priority()
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{
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write<Icdipr::Priority>(Icdipr::Priority::GET_MIN_PRIORITY, 0);
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return read<Icdipr::Priority>(0);
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}
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/**
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* Maximum supported interrupt priority
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*/
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Icdipr::access_t max_priority() { return 0; }
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/**
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* ID of the maximum supported interrupt
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*/
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Icdictr::access_t max_interrupt()
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{
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enum { LINE_WIDTH_LOG2 = 5 };
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Icdictr::access_t lnr = read<Icdictr::It_lines_number>();
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return ((lnr + 1) << LINE_WIDTH_LOG2) - 1;
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}
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} _distr;
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/**
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* CPU interface
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*/
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struct Cpu : public Mmio
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{
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Cpu(addr_t const base) : Mmio(base) { }
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/**
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* CPU interface control register
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*/
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struct Iccicr : Register<0x00, 32>
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{
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/* Without security extension */
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struct Enable : Bitfield<0,1> { };
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/* With security extension */
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struct Enable_s : Bitfield<0,1> { };
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struct Enable_ns : Bitfield<1,1> { };
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struct Ack_ctl : Bitfield<2,1> { };
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struct Fiq_en : Bitfield<3,1> { };
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struct Sbpr : Bitfield<4,1> { };
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};
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/**
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* Priority mask register
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*/
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struct Iccpmr : Register<0x04, 32>
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{
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struct Priority : Bitfield<0,8> { };
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};
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/**
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* Binary point register
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*/
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struct Iccbpr : Register<0x08, 32>
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{
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struct Binary_point : Bitfield<0,3>
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{
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enum { NO_PREEMPTION = 7 };
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};
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};
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/**
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* Interrupt acknowledge register
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*/
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struct Icciar : Register<0x0c, 32, true>
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{
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struct Ack_int_id : Bitfield<0,10> { };
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struct Cpu_id : Bitfield<10,3> { };
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};
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/**
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* End of interrupt register
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*/
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struct Icceoir : Register<0x10, 32, true>
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{
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struct Eoi_int_id : Bitfield<0,10> { };
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struct Cpu_id : Bitfield<10,3> { };
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};
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} _cpu;
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unsigned const _max_interrupt;
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unsigned long _last_taken_request;
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public:
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/**
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* Constructor, all interrupts get masked
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*/
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Pl390_base(addr_t const distributor, addr_t const cpu_interface) :
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_distr(distributor),
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_cpu(cpu_interface),
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_max_interrupt(_distr.max_interrupt()),
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_last_taken_request(SPURIOUS_ID)
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{
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/* Disable device */
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_distr.write<Distr::Icddcr::Enable>(0);
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_cpu.write<Cpu::Iccicr::Enable>(0);
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mask();
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/* Supported priority range */
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unsigned const min_prio = _distr.min_priority();
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unsigned const max_prio = _distr.max_priority();
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/* Configure every shared peripheral interrupt */
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for (unsigned i=MIN_SPI; i <= _max_interrupt; i++)
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{
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_distr.write<Distr::Icdicr::Edge_triggered>(0, i);
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_distr.write<Distr::Icdipr::Priority>(max_prio, i);
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_distr.write<Distr::Icdiptr::Cpu_targets>(Distr::Icdiptr::Cpu_targets::ALL, i);
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}
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/* Disable the priority filter */
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_cpu.write<Cpu::Iccpmr::Priority>(min_prio);
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/* Disable preemption of interrupt handling by interrupts */
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_cpu.write<Cpu::Iccbpr::Binary_point>(
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Cpu::Iccbpr::Binary_point::NO_PREEMPTION);
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/* Enable device */
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_distr.write<Distr::Icddcr::Enable>(1);
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_cpu.write<Cpu::Iccicr::Enable>(1);
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}
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/**
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* Get the ID of the last interrupt request
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*
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* \return True if the request with ID 'i' is treated as accepted
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* by the CPU and awaits an subsequently 'finish_request'
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* call. Otherwise this returns false and the value of 'i'
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* remains useless.
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*/
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bool take_request(unsigned & i)
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{
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_last_taken_request = _cpu.read<Cpu::Icciar::Ack_int_id>();
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i = _last_taken_request;
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return valid(i);
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}
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/**
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* Complete the last request that was taken via 'take_request'
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*/
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void finish_request()
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{
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if (!valid(_last_taken_request)) return;
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_cpu.write<Cpu::Icceoir>(Cpu::Icceoir::Eoi_int_id::bits(_last_taken_request) |
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Cpu::Icceoir::Cpu_id::bits(0) );
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_last_taken_request = SPURIOUS_ID;
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}
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/**
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* Check if 'i' is a valid interrupt request ID at the device
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*/
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bool valid(unsigned const i) const { return i <= _max_interrupt; }
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/**
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* Unmask all interrupts
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*/
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void unmask()
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{
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for (unsigned i=0; i <= _max_interrupt; i++)
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_distr.write<Distr::Icdiser::Set_enable>(1, i);
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}
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/**
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* Unmask interrupt 'i'
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*/
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void unmask(unsigned const i)
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{
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_distr.write<Distr::Icdiser::Set_enable>(1, i);
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}
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/**
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* Mask all interrupts
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*/
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void mask()
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{
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for (unsigned i=0; i <= _max_interrupt; i++)
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_distr.write<Distr::Icdicer::Clear_enable>(1, i);
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}
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/**
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* Mask interrupt 'i'
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*/
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void mask(unsigned const i)
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{
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_distr.write<Distr::Icdicer::Clear_enable>(1, i);
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}
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};
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}
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#endif /* _BASE__INCLUDE__DRIVERS__PIC__PL390_BASE_H_ */
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