mirror of
https://github.com/genodelabs/genode.git
synced 2025-01-21 03:55:04 +00:00
Reinier Millo Sánchez
Christian Helmuth
parent
6776d6c9a8
commit
433f859cb9
@ -3,7 +3,7 @@
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* \author Alexy Gallardo Segura <alexy@uclv.cu>
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* \author Humberto López León <humberto@uclv.cu>
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* \author Reinier Millo Sánchez <rmillo@uclv.cu>
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* \date 2015-04-27
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* \date 2015-07-08
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*/
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/*
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@ -30,12 +30,16 @@ struct Genode::Board_base : Exynos4
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enum
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{
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/* clock management unit */
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CMU_MMIO_BASE = 0x10040000,
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CMU_MMIO_BASE = 0x10030000,
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CMU_MMIO_SIZE = 0x18000,
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/* power management unit */
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PMU_MMIO_BASE = 0x10020000,
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PMU_MMIO_SIZE = 0x5000,
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/* USB HOST interrupt */
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USB_HOST20_IRQ = 102,
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};
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};
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@ -3,11 +3,11 @@
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# \author Alexy Gallardo Segura <alexy@uclv.cu>
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# \author Humberto López León <humberto@uclv.cu>
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# \author Reinier Millo Sánchez <rmillo@uclv.cu>
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# \date 2015-04-28
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# \date 2015-07-08
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#
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# denote specs that are fullfilled by this spec
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SPECS += exynos4 cortex_a9
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SPECS += exynos4 cortex_a9 usb
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# add repository relative paths
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REP_INC_DIR += include/platform/odroid_x2
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@ -2,6 +2,7 @@ proc have_platform_drv {} {
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if {[have_spec linux]} {
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return 0
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}
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return [expr [have_spec platform_arndale] \
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|| [have_spec platform_imx53] \
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|| [have_spec platform_rpi] \
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29
repos/dde_linux/include/usb/platform_odroid_x2/usb_masks.h
Normal file
29
repos/dde_linux/include/usb/platform_odroid_x2/usb_masks.h
Normal file
@ -0,0 +1,29 @@
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/*
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* \brief USB registers masks for Odroid-x2
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* \author Alexy Gallardo Segura <alexy@uclv.cu>
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* \author Humberto Lopez Leon <humberto@uclv.cu>
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* \author Reinir Millo Sanchez <rmillo@uclv.cu>
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* \date 2015-07-08
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*/
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/*
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* Copyright (C) 2015 Genode Labs GmbH
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*
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* This file is part of the Genode OS framework, which is distributed
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* under the terms of the GNU General Public License version 2.
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*/
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#ifndef _USB_MASKS_H_
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#define _USB_MASKS_H_
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enum {
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PHY0_NORMAL_MASK = 0x39 << 0,
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PHY0_SWRST_MASK = 0x7 << 0,
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PHY1_STD_NORMAL_MASK = 0x7 << 6,
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EXYNOS4X12_HSIC0_NORMAL_MASK = 0x7 << 9,
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EXYNOS4X12_HSIC1_NORMAL_MASK = 0x7 << 12,
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EXYNOS4X12_HOST_LINK_PORT_SWRST_MASK = 0xf << 7,
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EXYNOS4X12_PHY1_SWRST_MASK = 0xf << 3,
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};
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#endif /* _USB_MASKS_H_ */
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4
repos/dde_linux/lib/mk/platform_odroid_x2/usb-stat.mk
Normal file
4
repos/dde_linux/lib/mk/platform_odroid_x2/usb-stat.mk
Normal file
@ -0,0 +1,4 @@
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LIBS += net-stat
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CC_OPT += -DGENODE_NET_STAT
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include $(REP_DIR)/lib/mk/platform_odroid_x2/usb.mk
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15
repos/dde_linux/lib/mk/platform_odroid_x2/usb.mk
Normal file
15
repos/dde_linux/lib/mk/platform_odroid_x2/usb.mk
Normal file
@ -0,0 +1,15 @@
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SRC_C += $(addprefix net/usb/, usbnet.c smsc95xx.c)
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SRC_C += usb/host/ehci-exynos.c
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include $(REP_DIR)/lib/mk/usb.inc
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include $(REP_DIR)/lib/mk/armv7/usb.inc
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CC_OPT += -DCONFIG_USB_EHCI_TT_NEWSCHED \
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-DCONFIG_USB_OTG_UTILS
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SRC_CC += platform.cc
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INC_DIR += $(REP_DIR)/include/usb/platform_odroid_x2
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vpath platform.cc $(LIB_DIR)/arm/platform_odroid_x2
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296
repos/dde_linux/src/lib/usb/arm/platform_odroid_x2/platform.cc
Normal file
296
repos/dde_linux/src/lib/usb/arm/platform_odroid_x2/platform.cc
Normal file
@ -0,0 +1,296 @@
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/*
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* \brief EHCI for Odroid-x2 initializaion code
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* \author Sebastian Sumpf
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* \author Alexy Gallardo Segura <alexy@uclv.cu>
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* \author Humberto Lopez Leon <humberto@uclv.cu>
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* \author Reinir Millo Sanchez <rmillo@uclv.cu>
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* \date 2015-07-08
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*/
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/*
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* Copyright (C) 2015 Genode Labs GmbH
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*
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* This file is part of the Genode OS framework, which is distributed
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* under the terms of the GNU General Public License version 2.
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*/
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/* Genode */
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#include <drivers/board_base.h>
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#include <os/attached_io_mem_dataspace.h>
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#include <io_mem_session/connection.h>
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#include <regulator/consts.h>
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#include <regulator_session/connection.h>
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#include <timer_session/connection.h>
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#include <irq_session/connection.h>
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#include <util/mmio.h>
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/* Emulation */
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#include <platform/platform.h>
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#include <extern_c_begin.h>
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#include <lx_emul.h>
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#include <extern_c_end.h>
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#include <platform.h>
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#include <usb_masks.h>
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using namespace Genode;
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enum {
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/*The EHCI base is taken from linux kernel */
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EHCI_BASE = 0x12580000,
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GPIO_BASE = 0x11000000,
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USBOTG = 0x125B0000,
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EHCI_IRQ = Board_base::USB_HOST20_IRQ,
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};
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static resource _ehci[] =
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{
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{ EHCI_BASE, EHCI_BASE + 0xfff, "ehci", IORESOURCE_MEM },
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{ EHCI_IRQ, EHCI_IRQ, "ehci-irq", IORESOURCE_IRQ },
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};
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/**
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* EHCI controller
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*/
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struct Ehci : Genode::Mmio
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{
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Ehci(addr_t const mmio_base) : Mmio(mmio_base)
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{
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write<Cmd>(0);
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/* reset */
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write<Cmd::Reset>(1);
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while(read<Cmd::Reset>())
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msleep(1);
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}
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struct Cmd : Register<0x10, 32>
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{
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struct Reset : Bitfield<1, 1> { };
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};
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};
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/**
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* Gpio ETC6 register handling
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*/
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struct Etc6 : Genode::Mmio
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{
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Etc6(Genode::addr_t base):Genode::Mmio (base)
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{
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unsigned int value;
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value = read<Pud>();
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write<Pud>((value & ~(0x3 << 14)) | (0x3 << 14));
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value = read<Pud>();
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}
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struct Pud : Register<0x0228, 16>{};
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};
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/**
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* USB OTG handling
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*/
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struct Usb_Otg : Genode::Mmio
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{
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Usb_Otg(Genode::addr_t base):Genode::Mmio (base)
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{
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Timer::Connection timer;
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unsigned int rstcon_mask = 0;
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unsigned int phyclk_mask = 5;
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unsigned int phypwr_mask = 0;
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/*set the clock of device*/
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write<Phyclk>(phyclk_mask);
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rstcon_mask= read<Phyclk>();
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/* set to normal of Device */
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phypwr_mask= read<Phypwr>() & ~PHY0_NORMAL_MASK;
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write<Phypwr>(phypwr_mask);
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/* set to normal of Host */
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phypwr_mask=read<Phypwr>();
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phypwr_mask &= ~(PHY1_STD_NORMAL_MASK
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|EXYNOS4X12_HSIC0_NORMAL_MASK
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|EXYNOS4X12_HSIC1_NORMAL_MASK);
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write<Phypwr>(phypwr_mask);
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/* reset both PHY and Link of Device */
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rstcon_mask = read<Rstcon>() | PHY0_SWRST_MASK;
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write<Rstcon>(rstcon_mask);
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timer.usleep(10);
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rstcon_mask &= ~PHY0_SWRST_MASK;
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write<Rstcon>(rstcon_mask);
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/* reset both PHY and Link of Host */
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rstcon_mask = read<Rstcon>()
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|EXYNOS4X12_HOST_LINK_PORT_SWRST_MASK
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|EXYNOS4X12_PHY1_SWRST_MASK;
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write<Rstcon>(rstcon_mask);
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timer.usleep(10);
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rstcon_mask &= ~(EXYNOS4X12_HOST_LINK_PORT_SWRST_MASK
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|EXYNOS4X12_PHY1_SWRST_MASK);
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write<Rstcon>(rstcon_mask);
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timer.usleep(10);
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}
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struct Phypwr : Register <0x0,32>{};
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struct Phyclk : Register <0x4,32>{};
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struct Rstcon : Register <0x8,32>{};
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};
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/**
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* Gpio handling
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*/
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class Gpio_bank : Genode::Mmio
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{
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public:
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Gpio_bank(Genode::addr_t base):Genode::Mmio (base){}
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struct Con : Register<0x0C60, 32>{};
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struct Dat : Register<0x0C64, 32>{};
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void setDirection(int gpio , int en)
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{
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unsigned int value;
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enum { GPIO_OUTPUT = 0x1 };
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value = read<Dat>();
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value &= ~(0x1 << gpio);
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if (en)
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value |= 0x1 << gpio;
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write<Dat>(value);
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configurePin(gpio, GPIO_OUTPUT);
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write<Dat>(value);
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}
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private:
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void configurePin(int gpio, int cfg)
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{
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unsigned int value;
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value = read<Con>();
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value &= ~con_mask(gpio);
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value |= con_sfr(gpio, cfg);
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write<Con>(value);
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}
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static inline
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unsigned con_mask(unsigned val) { return 0xf << ((val) << 2); }
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static inline
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unsigned con_sfr(unsigned x, unsigned v) { return (v) << ((x) << 2); }
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};
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static void clock_pwr_init()
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{
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/*Initialization of register etc6*/
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Io_mem_connection io_gpio(GPIO_BASE, 0x1000);
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addr_t gpio_base = (addr_t)env()->rm_session()->attach(io_gpio.dataspace());
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Etc6 etc6(gpio_base);
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env()->rm_session()->detach(gpio_base);
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/* enable USB2 clock and power up */
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static Regulator::Connection reg_clk(Regulator::CLK_USB20);
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reg_clk.state(true);
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static Regulator::Connection reg_pwr(Regulator::PWR_USB20);
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reg_pwr.state(true);
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}
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static void usb_phy_init()
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{
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Io_mem_connection io_usbotg(USBOTG, 0x1000);
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addr_t usbotg_base = (addr_t)env()->rm_session()->attach(io_usbotg.dataspace());
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Usb_Otg usbotg(usbotg_base);
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env()->rm_session()->detach(usbotg_base);
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}
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static void odroidx2_ehci_init()
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{
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clock_pwr_init();
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usb_phy_init();
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/* reset hub via GPIO */
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Io_mem_connection io_gpio(GPIO_BASE, 0x1000);
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addr_t gpio_base = (addr_t)env()->rm_session()->attach(io_gpio.dataspace());
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Gpio_bank x3(gpio_base);
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/* Set Ref freq 0 => 24MHz, 1 => 26MHz*/
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/* Odroid Us have it at 24MHz, Odroid Xs at 26MHz */
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x3.setDirection(0,1);
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/* Disconnect, Reset, Connect */
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x3.setDirection(4,0);
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x3.setDirection(5,0);
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x3.setDirection(5,1);
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x3.setDirection(4,1);
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env()->rm_session()->detach(gpio_base);
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/* reset ehci controller */
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Io_mem_connection io_ehci(EHCI_BASE, 0x1000);
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addr_t ehci_base = (addr_t)env()->rm_session()->attach(io_ehci.dataspace());
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Ehci ehci(ehci_base);
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env()->rm_session()->detach(ehci_base);
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}
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extern "C" void module_ehci_exynos_init();
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extern "C" int module_usbnet_init();
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extern "C" int module_smsc95xx_driver_init();
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void ehci_setup(Services *services)
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{
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/* register network */
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if (services->nic){
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module_usbnet_init();
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module_smsc95xx_driver_init();
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}
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/* register EHCI controller */
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module_ehci_exynos_init();
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/* setup controller */
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odroidx2_ehci_init();
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/* setup EHCI-controller platform device */
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platform_device *pdev = (platform_device *)kzalloc(sizeof(platform_device), 0);
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pdev->name = (char *)"exynos-ehci";
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pdev->id = 0;
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pdev->num_resources = 2;
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pdev->resource = _ehci;
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/*needed for DMA buffer allocation. See 'hcd_buffer_alloc' in 'buffer.c' */
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static u64 dma_mask = ~(u64)0;
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pdev->dev.dma_mask = &dma_mask;
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pdev->dev.coherent_dma_mask = ~0;
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platform_device_register(pdev);
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}
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void platform_hcd_init(Services *services)
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{
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/* register network */
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if (services->nic){
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module_usbnet_init();
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module_smsc95xx_driver_init();
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}
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/* register ehci */
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if (services->ehci)
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ehci_setup(services);
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}
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Genode::Irq_session_capability platform_irq_activate(int irq)
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{
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try {
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Genode::Irq_connection conn(irq);
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conn.on_destruction(Genode::Irq_connection::KEEP_OPEN);
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return conn;
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} catch (...) { }
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return Genode::Irq_session_capability();
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}
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@ -3,7 +3,7 @@
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* \author Alexy Gallardo Segura <alexy@uclv.cu>
|
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* \author Humberto Lopez Leon <humberto@uclv.cu>
|
||||
* \author Reinier Millo Sanchez <rmillo@uclv.cu>
|
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* \date 2015-04-30
|
||||
* \date 2015-07-08
|
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*/
|
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|
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/*
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@ -58,9 +58,10 @@ class Cmu : public Regulator::Driver,
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** CMU CPU registers **
|
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***********************/
|
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typedef Pll_lock<4000> Apll_lock;
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typedef Pll_con0<0x4100> Apll_con0;
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typedef Pll_con0<0x14100> Apll_con0;
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struct Clk_src_cpu : Register<0x4200, 32>
|
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|
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struct Clk_src_cpu : Register<0x14200, 32>
|
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{
|
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struct Mux_core_sel : Bitfield<16, 1>
|
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{
|
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@ -68,28 +69,30 @@ class Cmu : public Regulator::Driver,
|
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};
|
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};
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struct Clk_mux_stat_cpu : Register<0x4400, 32>
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struct Clk_mux_stat_cpu : Register<0x14400, 32>
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{
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struct Core_sel : Bitfield<16, 3>
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{
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enum { MOUT_APLL = 0b1, SCLK_MPLL = 0b10 };
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};
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};
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struct Clk_div_cpu0 : Register<0x4500, 32>
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struct Clk_div_cpu0 : Register<0x14500, 32>
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{
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/* Cpu0 divider values for frequencies 200 - 1400 */
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static const Genode::uint32_t values[];
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};
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struct Clk_div_cpu1 : Register<0x4504, 32>
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struct Clk_div_cpu1 : Register<0x14504, 32>
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{
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/* Divider for cpu1 doesn't change */
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enum { FIX_VALUE = 32 };
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};
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struct Clk_div_stat_cpu0 : Register<0x4600, 32>
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struct Clk_div_stat_cpu0 : Register<0x14600, 32>
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{
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struct Div_core : Bitfield< 0, 1> {};
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struct Div_corem0 : Bitfield< 4, 1> {};
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struct Div_corem1 : Bitfield< 8, 1> {};
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@ -99,6 +102,7 @@ class Cmu : public Regulator::Driver,
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struct Div_apll : Bitfield<24, 1> {};
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struct Div_core2 : Bitfield<28, 1> {};
|
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|
||||
|
||||
static bool in_progress(access_t stat_word)
|
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{
|
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return stat_word & (Div_core::bits(1) |
|
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@ -112,7 +116,7 @@ class Cmu : public Regulator::Driver,
|
||||
}
|
||||
};
|
||||
|
||||
struct Clk_div_stat_cpu1 : Register<0x4604, 32>
|
||||
struct Clk_div_stat_cpu1 : Register<0x14604, 32>
|
||||
{
|
||||
struct Div_copy : Bitfield<0, 1> { };
|
||||
struct Div_hpm : Bitfield<4, 1> { };
|
||||
@ -128,18 +132,37 @@ class Cmu : public Regulator::Driver,
|
||||
/************************
|
||||
** CMU CORE registers **
|
||||
************************/
|
||||
|
||||
typedef Pll_lock<0x0008> Mpll_lock;
|
||||
typedef Pll_con0<0x0108> Mpll_con0;
|
||||
|
||||
struct Clk_src_dmc : Register<0x4200, 32>
|
||||
struct Clk_src_dmc : Register<0x10200, 32>
|
||||
|
||||
{
|
||||
struct Mux_mpll_sel : Bitfield<12, 1> { enum { XXTI, MPLL_FOUT_RGT }; };
|
||||
};
|
||||
|
||||
struct Clk_gate_ip_dmc : Register<0x0900, 32> { };
|
||||
|
||||
|
||||
struct Clk_gate_ip_acp : Register<0x0900, 32> { };
|
||||
struct Clk_gate_ip_isp0 : Register<0x8800, 32> { };
|
||||
struct Clk_gate_ip_isp1 : Register<0x8804, 32> { };
|
||||
|
||||
|
||||
|
||||
/***********************
|
||||
** CMU TOP registers **
|
||||
***********************/
|
||||
|
||||
struct Clk_gate_ip_fsys : Register<0xC940, 32>
|
||||
{
|
||||
struct Usbhost20 : Bitfield<12, 1> { };
|
||||
struct Usbdevice : Bitfield<13, 1> { };
|
||||
|
||||
};
|
||||
|
||||
|
||||
|
||||
/*******************
|
||||
** CPU functions **
|
||||
*******************/
|
||||
@ -148,7 +171,7 @@ class Cmu : public Regulator::Driver,
|
||||
|
||||
void _cpu_clk_freq(unsigned long level)
|
||||
{
|
||||
PINF("Setting CPU frequency %lu\n",level);
|
||||
PINF("Changing CPU frequency to %lu",level);
|
||||
unsigned freq;
|
||||
switch (level) {
|
||||
case CPU_FREQ_200:
|
||||
@ -218,6 +241,34 @@ class Cmu : public Regulator::Driver,
|
||||
!= Clk_mux_stat_cpu::Core_sel::MOUT_APLL) ;
|
||||
|
||||
_cpu_freq = static_cast<Cpu_clock_freq>(level);
|
||||
PINF("End of Changing CPU frequency to %lu",level);
|
||||
}
|
||||
|
||||
|
||||
void _enable(Regulator_id id)
|
||||
{
|
||||
switch (id) {
|
||||
case CLK_USB20:
|
||||
{
|
||||
write<Clk_gate_ip_fsys::Usbdevice>(1);
|
||||
return write<Clk_gate_ip_fsys::Usbhost20>(1);
|
||||
}
|
||||
default:
|
||||
PWRN("Unsupported for %s", names[id].name);
|
||||
}
|
||||
}
|
||||
|
||||
void _disable(Regulator_id id)
|
||||
{
|
||||
switch (id) {
|
||||
case CLK_USB20:
|
||||
{
|
||||
write<Clk_gate_ip_fsys::Usbdevice>(0);
|
||||
return write<Clk_gate_ip_fsys::Usbhost20>(0);
|
||||
}
|
||||
default:
|
||||
PWRN("Unsupported for %s", names[id].name);
|
||||
}
|
||||
}
|
||||
|
||||
public:
|
||||
@ -230,9 +281,19 @@ class Cmu : public Regulator::Driver,
|
||||
Genode::Board_base::CMU_MMIO_SIZE),
|
||||
_cpu_freq(CPU_FREQ_1400)
|
||||
{
|
||||
|
||||
|
||||
/**
|
||||
* Close certain clock gates by default (~ 0.7 Watt reduction)
|
||||
*/
|
||||
|
||||
write<Clk_gate_ip_fsys>(0);
|
||||
|
||||
/**
|
||||
* Set default CPU frequency
|
||||
*/
|
||||
|
||||
|
||||
_cpu_clk_freq(_cpu_freq);
|
||||
|
||||
}
|
||||
@ -265,10 +326,21 @@ class Cmu : public Regulator::Driver,
|
||||
|
||||
void state(Regulator_id id, bool enable)
|
||||
{
|
||||
if (enable)
|
||||
_enable(id);
|
||||
else
|
||||
_disable(id);
|
||||
}
|
||||
|
||||
bool state(Regulator_id id)
|
||||
{
|
||||
|
||||
switch (id) {
|
||||
case CLK_USB20:
|
||||
return read<Clk_gate_ip_fsys::Usbhost20>();
|
||||
default:
|
||||
PWRN("Unsupported for %s", names[id].name);
|
||||
}
|
||||
return true;
|
||||
}
|
||||
};
|
||||
|
||||
@ -3,7 +3,7 @@
|
||||
* \author Alexy Gallardo Segura <alexy@uclv.cu>
|
||||
* \author Humberto Lopez Leon <humberto@uclv.cu>
|
||||
* \author Reinier Millo Sanchez <rmillo@uclv.cu>
|
||||
* \date 2015-04-30
|
||||
* \date 2015-07-08
|
||||
*/
|
||||
|
||||
/*
|
||||
@ -24,14 +24,17 @@
|
||||
|
||||
struct Driver_factory: Regulator::Driver_factory
|
||||
{
|
||||
|
||||
Cmu _cmu;
|
||||
Pmu _pmu;
|
||||
|
||||
Regulator::Driver &create(Regulator::Regulator_id id)
|
||||
{
|
||||
switch (id) {
|
||||
case Regulator::CLK_CPU:
|
||||
case Regulator::CLK_USB20:
|
||||
return _cmu;
|
||||
case Regulator::PWR_USB20:
|
||||
return _pmu;
|
||||
default:
|
||||
throw Root::Invalid_args(); /* invalid regulator */
|
||||
};
|
||||
@ -39,14 +42,13 @@ struct Driver_factory: Regulator::Driver_factory
|
||||
|
||||
void destroy(Regulator::Driver &driver) {
|
||||
}
|
||||
|
||||
};
|
||||
|
||||
int main(int, char **)
|
||||
{
|
||||
using namespace Genode;
|
||||
|
||||
PINF("--- Odroid-x2 platform driver ---\n");
|
||||
PINF("--- Odroid-x2 platform driver ---");
|
||||
|
||||
static Cap_connection cap;
|
||||
static Rpc_entrypoint ep(&cap, 4096, "odroid_x2_plat_ep");
|
||||
@ -54,6 +56,7 @@ int main(int, char **)
|
||||
static Regulator::Root reg_root(&ep, env()->heap(), driver_factory);
|
||||
env()->parent()->announce(ep.manage(®_root));
|
||||
|
||||
PINF("--- Odroid-x2 platform driver. Done ---");
|
||||
sleep_forever();
|
||||
return 0;
|
||||
}
|
||||
|
||||
@ -3,7 +3,7 @@
|
||||
* \author Alexy Gallardo Segura <alexy@uclv.cu>
|
||||
* \author Humberto Lopez Leon <humberto@uclv.cu>
|
||||
* \author Reinier Millo Sanchez <rmillo@uclv.cu>
|
||||
* \date 2015-04-30
|
||||
* \date 2015-07-08
|
||||
*/
|
||||
|
||||
/*
|
||||
@ -65,68 +65,19 @@ class Pmu : public Regulator::Driver,
|
||||
struct Div_ratio : Bitfield<16, 10> { };
|
||||
};
|
||||
|
||||
typedef Control<0x704> Usbdrd_phy_control;
|
||||
typedef Control<0x708> Usbhost_phy_control;
|
||||
typedef Control<0x70c> Efnand_phy_control;
|
||||
typedef Control<0x718> Adc_phy_control;
|
||||
typedef Control<0x71c> Mtcadc_phy_control;
|
||||
typedef Control<0x720> Dptx_phy_control;
|
||||
typedef Control<0x724> Sata_phy_control;
|
||||
typedef Control<0x0704> Usbdrd_phy_control;
|
||||
typedef Control<0x0708> Usbhost_phy1_control;
|
||||
typedef Control<0x70c> Usbhost_phy2_control;
|
||||
|
||||
typedef Sysclk_configuration<0x2a40> Vpll_sysclk_configuration;
|
||||
typedef Sysclk_status<0x2a44> Vpll_sysclk_status;
|
||||
typedef Sysclk_configuration<0x2a60> Epll_sysclk_configuration;
|
||||
typedef Sysclk_status<0x2a64> Epll_sysclk_status;
|
||||
typedef Sysclk_configuration<0x2aa0> Cpll_sysclk_configuration;
|
||||
typedef Sysclk_status<0x2aa4> Cpll_sysclk_status;
|
||||
typedef Sysclk_configuration<0x2ac0> Gpll_sysclk_configuration;
|
||||
typedef Sysclk_status<0x2ac4> Gpll_sysclk_status;
|
||||
|
||||
typedef Configuration<0x4000> Gscl_configuration;
|
||||
typedef Status<0x4004> Gscl_status;
|
||||
typedef Configuration<0x4020> Isp_configuration;
|
||||
typedef Status<0x4024> Isp_status;
|
||||
typedef Configuration<0x4040> Mfc_configuration;
|
||||
typedef Status<0x4044> Mfc_status;
|
||||
typedef Configuration<0x4060> G3d_configuration;
|
||||
typedef Status<0x4064> G3d_status;
|
||||
typedef Configuration<0x40A0> Disp1_configuration;
|
||||
typedef Status<0x40A4> Disp1_status;
|
||||
typedef Configuration<0x40C0> Mau_configuration;
|
||||
typedef Status<0x40C4> Mau_status;
|
||||
|
||||
|
||||
template <typename C, typename S>
|
||||
void _disable_domain()
|
||||
{
|
||||
if (read<typename S::Stat>() == 0)
|
||||
return;
|
||||
write<typename C::Local_pwr_cfg>(0);
|
||||
while (read<typename S::Stat>() != 0) ;
|
||||
}
|
||||
|
||||
template <typename C, typename S>
|
||||
void _enable_domain()
|
||||
{
|
||||
if (read<typename S::Stat>() == 7)
|
||||
return;
|
||||
write<typename C::Local_pwr_cfg>(7);
|
||||
while (read<typename S::Stat>() != 7) ;
|
||||
}
|
||||
|
||||
void _enable(unsigned long id)
|
||||
{
|
||||
switch (id) {
|
||||
case PWR_USB20:
|
||||
write<Usbhost_phy_control::Enable>(1);
|
||||
write<Usbdrd_phy_control::Enable>(1);
|
||||
write<Usbhost_phy1_control::Enable>(1);
|
||||
write<Usbhost_phy2_control::Enable>(1);
|
||||
break;
|
||||
case PWR_HDMI: {
|
||||
_enable_domain<Disp1_configuration, Disp1_status>();
|
||||
Hdmi_phy_control::access_t hpc = read<Hdmi_phy_control>();
|
||||
Hdmi_phy_control::Div_ratio::set(hpc, 150);
|
||||
Hdmi_phy_control::Enable::set(hpc, 1);
|
||||
write<Hdmi_phy_control>(hpc);
|
||||
break; }
|
||||
default:
|
||||
PWRN("Unsupported for %s", names[id].name);
|
||||
}
|
||||
@ -136,7 +87,9 @@ class Pmu : public Regulator::Driver,
|
||||
{
|
||||
switch (id) {
|
||||
case PWR_USB20:
|
||||
write<Usbhost_phy_control::Enable>(0);
|
||||
write<Usbdrd_phy_control::Enable>(0);
|
||||
write<Usbhost_phy1_control::Enable>(0);
|
||||
write<Usbhost_phy2_control::Enable>(0);
|
||||
break;
|
||||
default:
|
||||
PWRN("Unsupported for %s", names[id].name);
|
||||
@ -151,26 +104,9 @@ class Pmu : public Regulator::Driver,
|
||||
Pmu() : Genode::Attached_mmio(Genode::Board_base::PMU_MMIO_BASE,
|
||||
Genode::Board_base::PMU_MMIO_SIZE)
|
||||
{
|
||||
write<Hdmi_phy_control ::Enable>(0);
|
||||
write<Usbdrd_phy_control ::Enable>(0);
|
||||
write<Usbhost_phy_control::Enable>(0);
|
||||
write<Efnand_phy_control ::Enable>(0);
|
||||
write<Adc_phy_control ::Enable>(0);
|
||||
write<Mtcadc_phy_control ::Enable>(0);
|
||||
write<Dptx_phy_control ::Enable>(0);
|
||||
|
||||
|
||||
_disable_domain<Gscl_configuration, Gscl_status>();
|
||||
_disable_domain<Isp_configuration, Isp_status>();
|
||||
_disable_domain<Mfc_configuration, Mfc_status>();
|
||||
_disable_domain<G3d_configuration, G3d_status>();
|
||||
_disable_domain<Disp1_configuration, Disp1_status>();
|
||||
_disable_domain<Mau_configuration, Mau_status>();
|
||||
|
||||
_disable_domain<Vpll_sysclk_configuration, Vpll_sysclk_status>();
|
||||
_disable_domain<Epll_sysclk_configuration, Epll_sysclk_status>();
|
||||
_disable_domain<Cpll_sysclk_configuration, Cpll_sysclk_status>();
|
||||
_disable_domain<Gpll_sysclk_configuration, Gpll_sysclk_status>();
|
||||
write<Usbhost_phy1_control::Enable>(0);
|
||||
write<Usbhost_phy2_control::Enable>(0);
|
||||
}
|
||||
|
||||
|
||||
@ -207,7 +143,7 @@ class Pmu : public Regulator::Driver,
|
||||
{
|
||||
switch (id) {
|
||||
case PWR_USB20:
|
||||
return read<Usbhost_phy_control::Enable>();
|
||||
return read<Usbdrd_phy_control::Enable>();
|
||||
default:
|
||||
PWRN("Unsupported for %s", names[id].name);
|
||||
}
|
||||
|
||||
Loading…
Reference in New Issue
Block a user